summaryrefslogtreecommitdiffstats
path: root/src/mesa
Commit message (Collapse)AuthorAgeFilesLines
* i965/fs: Remove one more fixed brw_null_reg() from the visitor.Francisco Jerez2015-06-121-1/+1
| | | | | | | | | | Instead use fs_builder::null_reg_f() which has the correct register width. Avoids the assertion failure in fs_builder::emit() hit by the "ES3-CTS.shaders.loops.for_dynamic_iterations.unconditional_break_fragment" GLES3 conformance test introduced by 4af4cfba9ee1014baa4a777660fc9d53d57e4c82. Reported-and-reviewed-by: Tapani Pälli <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* Revert "i965: Advertise a line width of 40.0 on Cherryview and Skylake."Kenneth Graunke2015-06-111-5/+1
| | | | | | | | | | | | | This reverts commit f3b709c0ac073cd0ec90a3a0d91d1ee94668e043. The "dEQP-GLES3.functional.rasterization.fbo.rbo_multisample_4. interpolation.lines_wide" test appears to be broken on Cherryview when we expose line widths greater than 12.0. I'm not sure why. For now, just go back to the limits we used on older platforms. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=90902 Acked-by: Matt Turner <[email protected]>
* i965: Re-index SSA definitions before printing NIR code.Kenneth Graunke2015-06-111-0/+6
| | | | | | | | | | This makes the SSA definitions use sequential numbers (0, 1, 2, ...) instead of seemingly random ones. There's not much point normally, but it makes debug output much easier to read. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Iago Toral Quiroga <[email protected]> Reviewed-by: Connor Abbott <[email protected]>
* mesa/main: Don't use ONCE_FLAG_INIT as a r-value.Jose Fonseca2015-06-111-1/+2
| | | | | | | | | It should only be used as an initializer expression. Trivial, and fixes Windows builds. Nevertheless, overwriting an once_flag like this seems dangerous and should be revised.
* i965/gen8: Fix antialiased line rendering with width < 1.5Iago Toral Quiroga2015-06-114-49/+30
| | | | | | | | | | | The same fix Marius implemented for gen6 (commit a9b04d8a) and gen7 (commit 24ecf37a). Also, we need the same code to handle special cases of line width in gen6, gen7 and now gen8, so put that in the helper function we use to compute the line width. Reviewed-by: Kenneth Graunke <[email protected]>
* mesa/es3.1: enable DRAW_INDIRECT_BUFFER_BINDING for gles3.1Tapani Pälli2015-06-112-2/+18
| | | | | | | | | | (increases ES31-CTS.draw_indirect.basic.* passing tests) v2: only expose DRAW_INDIRECT_BUFFER_BINDING for GL core + ES3.1 Signed-off-by: Tapani Pälli <[email protected]> Reviewed-by: Martin Peres <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* mesa/main: avoid null access in format_array_table_init()Juha-Pekka Heikkila2015-06-111-0/+10
| | | | | | | | If _mesa_hash_table_create failed we'd get null pointer. Report error and go away. Signed-off-by: Juha-Pekka Heikkila <[email protected]> Reviewed-by: Anuj Phogat <[email protected]>
* mesa/main: Remove _mesa_HashClone()Juha-Pekka Heikkila2015-06-112-31/+0
| | | | | | | | I didn't find this being used anywhere. Signed-off-by: Juha-Pekka Heikkila <[email protected]> Reviewed-by: Timothy Arceri <[email protected]> Reviewed-by: Anuj Phogat <[email protected]>
* i965: do_blit_drawpixels: decode array formatsAlexander Monakov2015-06-111-0/+2
| | | | | | | | | | | | Correct a regression introduced by commit 922c0c9fd526 by converting "array format", if received from _mesa_format_from_format_and_type, to mesa_format. References: https://bugs.freedesktop.org/show_bug.cgi?id=90839 Signed-off-by: Alexander Monakov <[email protected]> Tested-by: AnAkkk <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Cc: [email protected]
* i965: do not round line width when multisampling or antialiaing are enabledIago Toral Quiroga2015-06-115-15/+25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In commit fe74fee8fa721a we rounded the line width to the nearest integer to match the GLES3 spec requirements stated in section 13.4.2.1, but that seems to break a dEQP test that renders wide lines in some multisampling scenarios. Ian noted that the Open 4.4 spec has the following similar text: "The actual width of non-antialiased lines is determined by rounding the supplied width to the nearest integer, then clamping it to the implementation-dependent maximum non-antialiased line width." and suggested that when ES removed antialiased lines, they removed "non-antialised" from that paragraph but probably should not have. Going by that note, this patch restricts the quantization implemented in fe74fee8fa721a only to regular aliased lines. This seems to keep the tests fixed with that commit passing while fixing the broken test. v2: - Drop one of the clamps (Ken, Marius) - Add a rule to prevent advertising line widths that when rounded go beyond the limits allowed by the hardware (Ken) - Update comments in the code accordingly (Ian) - Put the code in a utility function (Ian) Fixes: dEQP-GLES3.functional.rasterization.fbo.rbo_multisample_max.primitives.lines_wide Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=90749 Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Ian Romanick <[email protected]> Cc: "10.6" <[email protected]>
* i965: Momentarily pretend to support ARB_texture_stencil8 for blits.Kenneth Graunke2015-06-101-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | Broadwell's stencil blitting code attempts to bind a renderbuffer as a texture, using dd->BindRenderbufferTexImage(). This calls _mesa_init_teximage_fields(), which then attempts to set img->_BaseFormat = _mesa_base_tex_format(ctx, internalFormat), which assert fails if internalFormat is GL_STENCIL_INDEX8 but ARB_texture_stencil8 is unsupported. To work around this, just pretend to support the extension momentarily, during the blit. Meta has already munged a variety of other things in the context (including the API!), so it's not that much worse than what we're already doing. Fixes regressions since commit f7aad9da20b13c98f77d6a690b327716f39c0a47 (mesa/teximage: use correct extension for accept stencil texture.). v2: Add an XXX comment explaining the situation (requested by Jason Ekstrand and Martin Peres), and an assert that we don't support the extension so we remember to remove this hack (requested by Neil Roberts). Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* mesa: add GL_RED, GL_RG support for floating point texturesTapani Pälli2015-06-101-3/+34
| | | | | | | | | | | | | | | | | Mesa supports EXT_texture_rg and OES_texture_float. This patch adds support for using unsized enums GL_RED and GL_RG for floating point targets and writes proper checks for internalformat when format is GL_RED or GL_RG and type is of GL_FLOAT or GL_HALF_FLOAT. Later, internalformat will get adjusted by adjust_for_oes_float_texture after these checks. v2: simplify to check vs supported enums v3: follow the style and break out if internalFormat ok (Kenneth) Signed-off-by: Tapani Pälli <[email protected]> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=90748 Reviewed-by: Kenneth Graunke <[email protected]>
* mesa: allow unsized formats GL_RG, GL_RED for GLES 3.0 with half floatTapani Pälli2015-06-101-0/+4
| | | | | | | | v2: && -> ||, we enable on gles3 or if ARB_texture_rg is enabled Signed-off-by: Tapani Pälli <[email protected]> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=90748 Reviewed-by: Kenneth Graunke <[email protected]>
* android: generate files by $(call es-gen)Chih-Wei Huang2015-06-091-4/+12
| | | | | | | | | | | | | Use the pre-defined macro es-gen to generate new added files instead of writing new rules manually. The handmade rules that may generate the files before the directory is created result in such an error: /bin/bash: out/target/product/x86/gen/STATIC_LIBRARIES/libmesa_st_mesa_intermediates/main/format_pack.c: No such file or directory make: *** [out/target/product/x86/gen/STATIC_LIBRARIES/libmesa_st_mesa_intermediates/main/format_pack.c] Error 1 Signed-off-by: Chih-Wei Huang <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* android: export more dirs from libmesa_dri_commonChih-Wei Huang2015-06-091-1/+3
| | | | | | | | The include paths of libmesa_dri_common are also used by modules that need libmesa_dri_common. Signed-off-by: Chih-Wei Huang <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* i965/gen9: Use raw PS invocation count for queriesBen Widawsky2015-06-091-1/+1
| | | | | | | | | | | | Previously the number needed to be divided by 4 to get the proper results. Now the hardware does the right thing. Through experimentation it seems Braswell (CHV) does also need the division by 4. Fixes piglit test: arb_pipeline_statistics_query-frag Signed-off-by: Ben Widawsky <[email protected]> Reviewed-by: Anuj Phogat <[email protected]>
* mesa: remove some MAX_NV_FRAGMENT_PROGRAM_* macrosBrian Paul2015-06-092-13/+4
| | | | | | | GL_NV_fragment_program support was removed a while ago. This is just some clean-up. Reviewed-by: Matt Turner <[email protected]>
* fs/reg_allocate: Remove the MRF hack helpers from fs_visitorJason Ekstrand2015-06-092-16/+13
| | | | | | | These are helpers that only exist in this one file. No reason to put them in the visitor. Reviewed-by: Neil Roberts <[email protected]>
* i965/fs: Don't let the EOT send message interfere with the MRF hackJason Ekstrand2015-06-092-3/+17
| | | | | | | | | | | | | Previously, we just put the message for the EOT send as high in the file as it would go. This is because the register pre-filling hardware will stop all over the early registers in the file in preparation for the next thread while you're still sending the last message. However, if something happens to spill, then the MRF hack interferes with the EOT send message and, if things aren't scheduled nicely, will stomp on it. Cc: "10.5 10.6" <[email protected]> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=90520 Reviewed-by: Neil Roberts <[email protected]>
* i965/fs: Drop fs_inst::force_uncompressed.Francisco Jerez2015-06-091-1/+0
| | | | | | This is now unused. Saves a whole bit of memory per instruction. Reviewed-by: Matt Turner <[email protected]>
* i965/fs: Remove dead IR construction code from the visitor.Francisco Jerez2015-06-094-439/+0
| | | | Reviewed-by: Matt Turner <[email protected]>
* i965/fs: Migrate test_fs_cmod_propagation to the IR builder.Francisco Jerez2015-06-091-52/+50
| | | | | | | v2: Use set_predicate/condmod. Use fs_builder::OPCODE instead of ::emit. Reviewed-by: Matt Turner <[email protected]>
* i965/fs: Migrate test_fs_saturate_propagation to the IR builder.Francisco Jerez2015-06-091-35/+34
| | | | | | v2: Use set_saturate. Use fs_builder::OPCODE instead of ::emit. Reviewed-by: Matt Turner <[email protected]>
* i965/fs: Migrate translation of NIR texturing instructions to the IR builder.Francisco Jerez2015-06-092-5/+6
| | | | | | v2: Don't remove assignments of base_ir just yet. Reviewed-by: Matt Turner <[email protected]>
* i965/fs: Migrate translation of NIR intrinsics to the IR builder.Francisco Jerez2015-06-092-41/+42
| | | | | | v2: Use fs_builder::SEL instead of ::emit. Use set_condmod(). Reviewed-by: Matt Turner <[email protected]>
* i965/fs: Migrate translation of NIR ALU instructions to the IR builder.Francisco Jerez2015-06-093-99/+99
| | | | Reviewed-by: Matt Turner <[email protected]>
* i965/fs: Migrate translation of NIR control flow to the IR builder.Francisco Jerez2015-06-092-12/+14
| | | | Reviewed-by: Matt Turner <[email protected]>
* i965/fs: Migrate NIR variable handling to the IR builder.Francisco Jerez2015-06-091-11/+10
| | | | Reviewed-by: Matt Turner <[email protected]>
* i965/fs: Migrate NIR emit_percomp() to the IR builder.Francisco Jerez2015-06-092-7/+12
| | | | Reviewed-by: Matt Turner <[email protected]>
* i965/fs: Migrate CS terminate message to the IR builder.Francisco Jerez2015-06-091-3/+2
| | | | Reviewed-by: Matt Turner <[email protected]>
* i965/fs: Migrate VS output writes to the IR builder.Francisco Jerez2015-06-091-13/+11
| | | | Reviewed-by: Matt Turner <[email protected]>
* i965/fs: Migrate FS framebuffer writes to the IR builder.Francisco Jerez2015-06-093-34/+35
| | | | | | | | | | | | | | The explicit call to fs_builder::group() in emit_single_fb_write() is required by the builder (otherwise the assertion in fs_builder::emit() would fail) because the subsequent LOAD_PAYLOAD and FB_WRITE instructions are in some cases emitted with a non-native execution width. The previous code would always use the channel enables for the first quarter, which is dubious but probably worked in practice because FB writes are never emitted inside non-uniform control flow and we don't pass the kill-pixel mask via predication in the cases where we have to fall-back to SIMD8 writes. Reviewed-by: Matt Turner <[email protected]>
* i965/fs: Migrate FS alpha test to the IR builder.Francisco Jerez2015-06-091-5/+5
| | | | Reviewed-by: Matt Turner <[email protected]>
* i965/fs: Migrate FS discard handling to the IR builder.Francisco Jerez2015-06-091-3/+3
| | | | Reviewed-by: Matt Turner <[email protected]>
* i965/fs: Migrate FS gl_SamplePosition/ID computation code to the IR builder.Francisco Jerez2015-06-091-25/+24
| | | | | | v2: Use fs_builder::AND/SHR/MOV instead of ::emit. Reviewed-by: Matt Turner <[email protected]>
* i965/fs: Migrate FS interpolation code to the IR builder.Francisco Jerez2015-06-092-48/+46
| | | | | | v2: Fix some preexisting trivial codestyle issues. Reviewed-by: Matt Turner <[email protected]>
* i965/fs: Migrate shader time to the IR builder.Francisco Jerez2015-06-092-36/+23
| | | | | | v2: Change null register destination type to UD so it can be compacted. Reviewed-by: Matt Turner <[email protected]>
* i965/fs: Migrate untyped surface read and atomic to the IR builder.Francisco Jerez2015-06-091-28/+27
| | | | Reviewed-by: Matt Turner <[email protected]>
* i965/fs: Migrate texturing implementation to the IR builder.Francisco Jerez2015-06-091-81/+78
| | | | | | v2: Remove tabs from modified lines. Reviewed-by: Matt Turner <[email protected]>
* i965/fs: Migrate pull constant loads to the IR builder.Francisco Jerez2015-06-093-31/+21
| | | | Reviewed-by: Matt Turner <[email protected]>
* i965/fs: Migrate Gen4 send dependency workarounds to the IR builder.Francisco Jerez2015-06-092-17/+11
| | | | | | v2: Change brw_null_reg() to bld.null_reg_f(). Reviewed-by: Matt Turner <[email protected]>
* i965/fs: Migrate lower_integer_multiplication to the IR builder.Francisco Jerez2015-06-091-13/+11
| | | | Reviewed-by: Matt Turner <[email protected]>
* i965/fs: Migrate lower_load_payload to the IR builder.Francisco Jerez2015-06-091-23/+11
| | | | Reviewed-by: Matt Turner <[email protected]>
* i965/fs: Migrate register spills and fills to the IR builder.Francisco Jerez2015-06-091-14/+15
| | | | | | | | | | | | | | | Yes, it's incorrect to use the 0-th channel enable group unconditionally without considering the execution and regioning controls of the instruction that uses the spilled value, but it matches the previous behaviour exactly, the builder just makes the preexisting problem more obvious because emitting an instruction of non-native SIMD width without having called .group() or .exec_all() explicitly would have led to an assertion failure. I'll fix the problem in a follow-up series, as the solution is going to be non-trivial. Reviewed-by: Matt Turner <[email protected]>
* i965/fs: Migrate try_replace_with_sel to the IR builder.Francisco Jerez2015-06-091-9/+9
| | | | Reviewed-by: Matt Turner <[email protected]>
* i965/fs: Migrate opt_sampler_eot to the IR builder.Francisco Jerez2015-06-091-2/+3
| | | | Reviewed-by: Matt Turner <[email protected]>
* i965/fs: Migrate opt_peephole_sel to the IR builder.Francisco Jerez2015-06-091-13/+12
| | | | Reviewed-by: Matt Turner <[email protected]>
* i965/fs: Create and emit instructions in one step in opt_peephole_sel.Francisco Jerez2015-06-091-24/+20
| | | | | | | | | | This simplifies opt_peephole_sel() slightly by emitting the SEL instructions immediately after they are created, what makes the sel_inst and mov_imm_inst arrays unnecessary and will make it possible to get rid of the explicit inserts when the pass is migrated to the IR builder. Reviewed-by: Matt Turner <[email protected]>
* i965/fs: Migrate opt_cse to the IR builder.Francisco Jerez2015-06-091-15/+12
| | | | Reviewed-by: Matt Turner <[email protected]>
* i965/fs: Don't drop force_writemask_all and _sechalf when copying a CSE ↵Francisco Jerez2015-06-091-1/+2
| | | | | | | | | | temporary. LOAD_PAYLOAD instructions need the same treatment as any other generator instructions, at least FB writes and typed surface messages will need a payload built with non-zero execution controls. Reviewed-by: Matt Turner <[email protected]>
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-26 10:16:27 +0000