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* i965: Add format/modifier advertisingVarad Gautam2017-06-081-4/+72
| | | | | | | | | v2: Rebase and reuse tiling/modifier map. (Daniel Stone) v3: bump DRIimageExtension to version 15, fill external_only array. v4: Y-tiling works since gen 6 Reviewed-by: Daniel Stone <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* i965: Support dmabuf import with modifiersVarad Gautam2017-06-081-18/+76
| | | | | | | | | | | | Add support for createImageFromDmaBufs2, adding a modifier to the original, and allow importing CCS resources with auxiliary data from dmabufs. v2: avoid DRIimageExtension version bump, pass single modifier to createImageFromDmaBufs2. Reviewed-by: Daniel Stone <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* i965: Improve same-buffer restriction for importsDaniel Stone2017-06-081-5/+13
| | | | | | | | | | | | | | | | Intel hardware requires that all planes of an image come from the same buffer, which is currently implemented by testing that all FDs are numerically the same. However, when going through a winsys (e.g.) or anything which transits FDs individually, the FDs may be different even if the underlying buffer is the same. Instead of checking the FDs for equality, we must check if they actually point to the same buffer (Jason). Reviewed-by: Varad Gautam <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* i965: Allocate tile aligned heightBen Widawsky2017-06-081-5/+26
| | | | | | | | | | | | | | | This patch shouldn't actually do anything because the libdrm function should already do this alignment. However, it preps us for a future patch where we add in the CCS AUX size, and in the process it serves as a good place to find bisectable issues if libdrm or kernel does something incorrectly. v2: Do proper alignment for X tiling, and make sure non-tiled case is handled (Jason) v3: Rebase (Daniel) Reviewed-by: Daniel Stone <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* i965: Move fallback size assignment out of bufmgrDaniel Stone2017-06-083-9/+17
| | | | | | | | | | | | | | The bufmgr took a mandatory size argument, which would only be used if the kernel size query failed, i.e. an older kernel. It didn't actually check that the BO size was sufficient for use. Pull the check out of the bufmgr, and actually check that the BO is sufficiently-sized for our import one level up. This also resolves a chicken/egg we have when importing bufers without explicit modifiers, namely that we need the tiling mode to calculate the size, but we need the BO imported to query the tiling mode. Reviewed-by: Jason Ekstrand <[email protected]>
* i965: Invert image modifier/tiling inferenceDaniel Stone2017-06-081-17/+18
| | | | | | | | | | | | When allocating images, we record a tiling mode and then work backwards to infer the modifier. Unfortunately this is the wrong way around, since it is a one:many mapping (e.g. TILING_Y can be plain Y-tiling, or Y-tiling with CCS). Invert the mapping, so we record a modifier first and then map this to a tiling mode. Reviewed-by: Jason Ekstrand <[email protected]>
* glsl: Fix gl_shader_stage enum unsigned comparisonRob Herring2017-06-083-0/+8
| | | | | | | | | | | Replace -1 with MESA_SHADER_NONE enum value to fix sign related warning: external/mesa3d/src/compiler/glsl/link_varyings.cpp:1415:25: warning: comparison of constant -1 with expression of type 'gl_shader_stage' is always true [-Wtautological-constant-out-of-range-compare] (consumer_stage != -1 && consumer_stage != MESA_SHADER_FRAGMENT))) { ~~~~~~~~~~~~~~ ^ ~~ Reviewed-by: Nicolai Hähnle <[email protected]> Signed-off-by: Rob Herring <[email protected]>
* i965: Delete intel_resolve_mapJason Ekstrand2017-06-077-213/+2
| | | | | | | | Now that we've moved over to the new array mechanism, it's no longer needed. Reviewed-by: Topi Pohjolainen <[email protected]> Acked-by: Chad Versace <[email protected]>
* i965: Use the new tracking mechanism for HiZJason Ekstrand2017-06-073-128/+127
| | | | | | | | | | | | | | This is similar to the previous commit only for HiZ. For HiZ, apart from everything looking different, there is really only one functional change: We now track the ISL_AUX_STATE_COMPRESSED_NO_CLEAR state. Previously, if you rendered to a resolved slice of the miptree and then did a fast-clear with a different clear color, that slice would get resolved even though it hadn't been fast-cleared. Now that we can track COMPRESSED_NO_CLEAR, we know that it doesn't have any blocks in the "clear" state so we can skip the resolve. Reviewed-by: Topi Pohjolainen <[email protected]> Acked-by: Chad Versace <[email protected]>
* i965/miptree: Make level_has_hiz take a const miptreeJason Ekstrand2017-06-072-2/+2
| | | | Acked-by: Chad Versace <[email protected]>
* i965: Wholesale replace the color resolve tracking codeJason Ekstrand2017-06-073-259/+313
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This commit reworks the resolve tracking for CCS and MCS to use the new isl_aux_state enum. This should provide much more accurate and easy to reason about tracking. In order to understand, for instance, the intel_miptree_prepare_ccs_access function, one only has to go look at the giant comment for the isl_aux_state enum and follow the arrows. Unfortunately, there's no good way to split this up without making a real mess so there are a bunch of changes in here: 1) We now do partial resolves. I really have no idea how this ever worked before. So far as I can tell, the only time the old code ever did a partial resolve was when it was using CCS_D where a partial resolve and a full resolve are the same thing. 2) We are now tracking 4 states instead of 3 for CCS_E. In particular, we distinguish between compressed with clear and compressed without clear. The end result is that you will never get two partial resolves in a row. 3) The texture view rules are now more correct. Previously, we would only bail if compression was not supported by the destination format. However, this is not actually correct. Not all format pairs are supported for texture views with CCS even if both support CCS individually. Fortunately, ISL has a helper for this. 4) We are no longer using intel_resolve_map for tracking aux state but are instead using a simple array of enum isl_aux_state indexed by level and layer. This is because, now that we're tracking 4 different states, it's no longer clear which should be the "default" and array lookups are faster than linked list searches. 5) The new code is very assert-happy. Incorrect transitions will now get caught by assertions rather than by rendering corruption. Reviewed-by: Topi Pohjolainen <[email protected]> Acked-by: Chad Versace <[email protected]>
* i965: Delete most of the old resolve interfaceJason Ekstrand2017-06-072-131/+10
| | | | | Reviewed-by: Topi Pohjolainen <[email protected]> Acked-by: Chad Versace <[email protected]>
* i965: Use the new get/set_aux_state functions for color clearsJason Ekstrand2017-06-071-7/+6
| | | | | Reviewed-by: Topi Pohjolainen <[email protected]> Acked-by: Chad Versace <[email protected]>
* i965: Move blorp to the new resolve functionsJason Ekstrand2017-06-071-45/+19
| | | | | Reviewed-by: Topi Pohjolainen <[email protected]> Acked-by: Chad Versace <[email protected]>
* i965: Move depth to the new resolve functionsJason Ekstrand2017-06-075-20/+54
| | | | | Reviewed-by: Topi Pohjolainen <[email protected]> Reviewed-by: Chad Versace <[email protected]>
* i965: Move images to the new resolve functionsJason Ekstrand2017-06-073-8/+13
| | | | | Reviewed-by: Topi Pohjolainen <[email protected]> Reviewed-by: Chad Versace <[email protected]>
* i965: Move framebuffer fetch to the new resolve functionsJason Ekstrand2017-06-073-11/+36
| | | | | Reviewed-by: Topi Pohjolainen <[email protected]> Reviewed-by: Chad Versace <[email protected]>
* i965: Remove an unneeded render_cache_set_check_flushJason Ekstrand2017-06-071-3/+3
| | | | | | | | | This is only needed to fix rendering corruptions caused by not flushing after doing a resolve operation. The resolve now does all the needed flushing so this is unnecessary. Reviewed-by: Topi Pohjolainen <[email protected]> Reviewed-by: Chad Versace <[email protected]>
* i965: Move color rendering to the new resolve functionsJason Ekstrand2017-06-074-34/+62
| | | | | | | | | | This also removes an unneeded brw_render_cache_set_check_flush() call. We were calling it in the case where the surface got resolved to satisfy the flushing requirements around resolves. However, blorp now does this itself, so the extra is just redundant. Reviewed-by: Topi Pohjolainen <[email protected]> Reviewed-by: Chad Versace <[email protected]>
* i965: Move texturing to the new resolve functionsJason Ekstrand2017-06-073-46/+71
| | | | | Reviewed-by: Topi Pohjolainen <[email protected]> Reviewed-by: Chad Versace <[email protected]>
* i965: Use the new resolve function for several simple casesJason Ekstrand2017-06-078-24/+32
| | | | | Reviewed-by: Topi Pohjolainen <[email protected]> Reviewed-by: Chad Versace <[email protected]>
* i965/miptree: Add new entrypoints for resolve managementJason Ekstrand2017-06-072-0/+259
| | | | | | | | | | | | This commit adds a new unified interface for doing resolves. The basic format is that, prior to any surface access such as texturing or rendering, you call intel_miptree_prepare_access. If the surface was written, you call intel_miptree_finish_write. These two functions take parameters which tell them whether or not auxiliary compression and fast clears are supported on the surface. Later commits will add wrappers around these two functions for texturing, rendering, etc. Reviewed-by: Topi Pohjolainen <[email protected]>
* i965: Combine render target resolve codeJason Ekstrand2017-06-072-52/+29
| | | | | | | | | We have two different bits of resolve code for render targets: one in brw_draw where it's always been and one in brw_context to deal with sRGB on gen9. Let's pull them together. Reviewed-by: Topi Pohjolainen <[email protected]> Reviewed-by: Chad Versace <[email protected]>
* i965: Be a bit more conservative about certain resolvesJason Ekstrand2017-06-074-8/+12
| | | | | | | | | There are several places where we were resolving the entire miptree when we really only needed to resolve a single slice. Let's avoid the unneeded resolving. Reviewed-by: Topi Pohjolainen <[email protected]> Reviewed-by: Chad Versace <[email protected]>
* i965/blorp: Move MCS allocation earlier for clearsJason Ekstrand2017-06-071-14/+14
| | | | | | | This way it happens before we call get_aux_state. Reviewed-by: Topi Pohjolainen <[email protected]> Reviewed-by: Chad Versace <[email protected]>
* i965/blorp: Refactor do_single_blorp_clearJason Ekstrand2017-06-071-17/+23
| | | | | | | | | | | Previously, we had two checks for can_fast_clear and a tiny bit of shared code in between. This commit pulls all of the fast clear code together and duplicates the tiny bit that declares some surface structs and calls blorp_surf_for_miptree. The duplication is no real loss and we're about to change the two in slightly different ways. Reviewed-by: Topi Pohjolainen <[email protected]> Reviewed-by: Chad Versace <[email protected]>
* i965/blorp: Take an explicit fast clear op in resolve_colorJason Ekstrand2017-06-073-15/+18
| | | | | Reviewed-by: Topi Pohjolainen <[email protected]> Reviewed-by: Chad Versace <[email protected]>
* i965/miptree: Move color resolve on map to intel_miptree_mapJason Ekstrand2017-06-071-5/+1
| | | | | | | | None of the other methods such as blit work with CCS either so we need to do the resolve for all maps. This change also makes us only resolve the one slice we're mapping and not the entire image. Reviewed-by: Topi Pohjolainen <[email protected]>
* i965: Inline renderbuffer_att_set_needs_depth_resolveJason Ekstrand2017-06-074-21/+21
| | | | Reviewed-by: Topi Pohjolainen <[email protected]>
* i965: Get rid of intel_renderbuffer_resolve_*Jason Ekstrand2017-06-073-52/+5
| | | | | | | | There is exactly one caller so it's a bit pointless to have all of this plumbing. Just inline it at the one place it's used. Reviewed-by: Topi Pohjolainen <[email protected]> Reviewed-by: Chad Versace <[email protected]>
* i965/miptree: Refactor intel_miptree_resolve_colorJason Ekstrand2017-06-076-38/+35
| | | | | | | | | The new version now takes a range of levels as well as a range of layers. It should also be a tiny bit faster because it only walks the resolve_map list once instead of once per layer. Reviewed-by: Topi Pohjolainen <[email protected]> Reviewed-by: Chad Versace <[email protected]>
* i965/miptree: Clean up the depth resolve helpers a littleJason Ekstrand2017-06-071-40/+30
| | | | | | Reviewed-by: Topi Pohjolainen <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Chad Versace <[email protected]>
* i965/surface_state: Images can't handle CCS at allJason Ekstrand2017-06-071-6/+6
| | | | | | Reviewed-by: Topi Pohjolainen <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Chad Versace <[email protected]>
* i965: Mark depth surfaces as needing a HiZ resolve after blittingJason Ekstrand2017-06-071-0/+2
| | | | | | | Cc: "17.0 17.1" <[email protected]> Reviewed-by: Topi Pohjolainen <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Chad Versace <[email protected]>
* st_glsl_to_tgsi: cleanup variable storage search.Dave Airlie2017-06-081-6/+4
| | | | | | I forgot to put the cleanup in earlier. Signed-off-by: Dave Airlie <[email protected]>
* mesa/main: fix gl_buffer_index enum comparisonRob Herring2017-06-073-7/+8
| | | | | | | | | | | | | | For clang, enums are unsigned by default and gives the following warning: external/mesa3d/src/mesa/main/buffers.c:764:21: warning: comparison of constant -1 with expression of type 'gl_buffer_index' is always false [-Wtautological-constant-out-of-range-compare] if (srcBuffer == -1) { ~~~~~~~~~ ^ ~~ Replace -1 with an enum value to fix this. Reviewed-by: Ian Romanick <[email protected]> Reviewed-by: Samuel Pitoiset <[email protected]> Signed-off-by: Rob Herring <[email protected]>
* st_glsl_to_tgsi: replace variables tracking list with a hash tableDave Airlie2017-06-081-13/+33
| | | | | | | | This removes the linear search which is fail when number of variables goes up to 30000 or so. Reviewed-by: Timothy Arceri <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* st_glsl_to_tgsi: rewrite rename registers to use array fully.Dave Airlie2017-06-081-26/+23
| | | | | | | | | | Instead of having to search the whole array, just use the whole thing and store a valid bit in there with the rename. Removes this from the profile on some of the fp64 tests Reviewed-by: Timothy Arceri <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* st_glsl_to_tgsi: bump index back up to 32-bitDave Airlie2017-06-081-2/+2
| | | | | | | | | | | | with some of the fp64 emulation, we are seeing shaders coming in with > 32K temps, they go out with 40 or so used, but while doing register renumber we need to store a lot of them. So bump this fields back up to 32-bit. Reviewed-by: Timothy Arceri <[email protected]> Reviewed-by: Marek Olšák <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* dri/vmwgfx: Disable a couple of glx extensions also for Ubuntu unity / compizThomas Hellstrom2017-06-071-0/+4
| | | | | | | | | | | It appears like the GLX_EXT_buffer_age extension also prevents Compiz / Ubuntu Unity from performing partial buffer swaps when it otherwise feels like doing so. So try to get them back again. We also disable GLX_OML_sync_control since it appears it had a favourable impact on gnome-shell. Signed-off-by: Thomas Hellstrom <[email protected]> Reviewed-by: Sinclair Yeh <[email protected]>
* dri: Turn of a couple of glx extensions for gnome-shell on vmwgfx.Thomas Hellstrom2017-06-071-0/+7
| | | | | | | | Increases performance on vmwgfx since we're avoiding full buffer damage and since we can't sync to vertical retrace anyway. Signed-off-by: Thomas Hellstrom <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* dri: Optionally turn off a couple of GLX extensions based on driconf optionsThomas Hellstrom2017-06-071-0/+10
| | | | | | | | | | | | With GLX_EXT_buffer_age turned on, gnome-shell will use full-screen damage with GLX, which severely hurts performance with architectures that emulate page-flips with copies. Like vmware. We would like to be able to turn off that extension. Similarly, typically the GLX_OML_sync_control doesn't make much sense on a virtual architecture since we don't really sync to the host's vertical retrace. We'd like to be able to turn it off as well. Signed-off-by: Thomas Hellstrom <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* st/mesa: don't keep framebuffer state in st_contextMarek Olšák2017-06-077-51/+48
| | | | | Reviewed-by: Samuel Pitoiset <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* st/mesa: cache pipe_surface for GL_FRAMEBUFFER_SRGB changesMarek Olšák2017-06-074-29/+41
| | | | | Reviewed-by: Samuel Pitoiset <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* st/mesa: use gl_driver_flags::NewFramebufferSRGBMarek Olšák2017-06-071-3/+6
| | | | | | | also call st_init_driver_flags when st_context is initialized. Reviewed-by: Samuel Pitoiset <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* mesa: add gl_driver_flags::NewFramebufferSRGBMarek Olšák2017-06-072-1/+7
| | | | | | | _NEW_BUFFERS updates too much stuff. Reviewed-by: Samuel Pitoiset <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* i965: Use BLORP for all HiZ opsJason Ekstrand2017-06-073-162/+10
| | | | | | | | BLORP has been capable of doing gen8-style HiZ ops for a while now. We might as well start using it. The one downside is that this may cause a bit more state emission since we still re-emit most things for BLORP. Reviewed-by: Topi Pohjolainen <[email protected]>
* i965: Move the post-HiZ-clear flush/stall to intel_hiz_execJason Ekstrand2017-06-072-16/+18
| | | | | | | | This also changes it to be predicated so we only do the flush/stall on clears and HiZ resolves. The docs only say it's needed for clears but empirical evidence says it's also needed for HiZ resolves. Reviewed-by: Topi Pohjolainen <[email protected]>
* intel/blorp: Plumb through access to the workaround BOJason Ekstrand2017-06-071-0/+13
| | | | | Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=101283 Reviewed-by: Topi Pohjolainen <[email protected]>
* intel/blorp: Refactor the HiZ op interfaceJason Ekstrand2017-06-071-2/+1
| | | | | | | | | | This commit does a few things: 1) Now that BLORP can do HiZ ops on gen8+, drop the gen6 prefix. 2) Switch parameters to uint32_t to match the rest of blorp. 3) Take a range of layers and loop internally. Reviewed-by: Topi Pohjolainen <[email protected]>
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