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* scons: add code to generate the various GL API filesBrian Paul2012-05-312-2/+15
| | | | | | | This fixes recent build breakage when we began building the generated API files from xml as part of the normal build process. Fixes http://bugs.freedesktop.org/show_bug.cgi?id=50475
* draw: simplify index buffer specificationBrian Paul2012-05-311-5/+4
| | | | | Replace draw_set_index_buffer() and draw_set_mapped_index_buffer() with draw_set_indexes() which simply takes a pointer and an index size.
* mesa: don't compile integer clear shaders for unsupported APIsOliver McFadden2012-05-301-1/+1
| | | | | | | | | | | | | | Discovered while running the Khronos conformance test suite and receiving "implementation error: meta program compile failed." This bug was recently introduced by the i965 clear patch set and would only be detected while using the ES2 API and only on gen6+ hardware. Signed-off-by: Oliver McFadden <[email protected]> Reviewed-by: Brian Paul <[email protected]> Reviewed-by: Eric Anholt <[email protected]> Reviewed-by: Ian Romanick <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965/blorp: Implement destination clipping and scissoringPaul Berry2012-05-291-5/+67
| | | | | This patch implements clipping and scissoring of the destination rect for blits that use the blorp engine (e.g. MSAA blits).
* mesa: Clean up some dricore-related detritus in the old Makefile.Eric Anholt2012-05-291-23/+7
| | | | | Reviewed-by: Matt Turner <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* automake: Convert dricore building to automake.Eric Anholt2012-05-293-42/+93
| | | | | | | | | | | This is performed in a subdirectory to avoid needing to convert all of src/mesa/Makefile in one go. I can now cherry-pick a commit containing glapi XML changes, do "(cd src/mapi/glapi/gen && make) && make", and get a working driver. Reviewed-by: Matt Turner <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* automake: Add a prefix variable to the common sources lists.Eric Anholt2012-05-293-277/+279
| | | | | | | | | | | In order to do the minimal change for libdricore conversion to automake, I need to put its Makefile.am in a subdirectory. Automake gets whiny/broken if you use GNU make features like "addprefix" or "$(FILES:%=../%)" to munge your *_SOURCES. So, use a plain old variable to be able to substitute in that "../" Reviewed-by: Matt Turner <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* automake: Rename variables in sources.mak to be automake compatible.Eric Anholt2012-05-293-67/+67
| | | | | | | | *_SOURCES is reserved for files lists for particular automake targets. Also, "-" in the variable names is not allowed. Reviewed-by: Matt Turner <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* mesa: Remove generated source files during make clean.Eric Anholt2012-05-291-0/+12
| | | | | Reviewed-by: Matt Turner <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* mesa: Restore installing of libGL for non-dri builds.Eric Anholt2012-05-291-3/+7
| | | | | | Reported-by: Sven Joachim <[email protected]> Reviewed-by: Matt Turner <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* mesa: Remove the generated glapi from source control, and just build it.Eric Anholt2012-05-294-25414/+3
| | | | | | | | | | | Mesa already always depends on python to build. The checked in changes are not reviewed (because any trivial change rewrites the world). We also have been pushing commits between xml change and regen where at-build-time xml-generated code disagrees with committed xml-generated code. And worst of all, sometimes we ("I") check in *stale* xml-generated code. Acked-by: Ian Romanick <[email protected]>
* i830: Fix crash for GL_STENCIL_TEST in i830Enable()Kurt Roeckx2012-05-291-1/+1
| | | | | | | | | | | commit 87f12bb2d95236c7b025d1a8be56b5ab1683d702 tried to fix rb->mt being NULL, but change this case wrong. NOTE: This is a candidate for the 8.0 branch. Signed-off-by: Kurt Roeckx <[email protected]> Reviewed-by: Eric Anholt <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* gallium: add st_api feature mask to prevent advertising MS visualsChristoph Bumiller2012-05-291-0/+1
| | | | | | | | | | | | | | v2: use a define for the maximum sample count v3: also test odd sample counts (r300 supports MS3) While multisample renderbuffers are supported by mesa, MS visuals are not, so we need a way to tell dri/st not to advertise them even if the gallium driver does support multisampled surfaces. Otherwise applications selecting these non-functional visuals would run into trouble ... Reviewed-by: Brian Paul <[email protected]>
* i965/msaa: Enable 4x MSAA on Gen7.Paul Berry2012-05-252-9/+9
| | | | | | | | | | | | | | | | | | Basic 4x MSAA support now works on Gen7. This patch enables it. As with Gen6, MSAA support is still fairly preliminary. In particular, the following are not yet supported: - 8x oversampling (Gen7 has hardware support for this, but we do not yet expose it). - Fully general blits between MSAA and non-MSAA buffers. - Formats other than RGBA8, DEPTH24, and STENCIL8. - Centrold interpolation. - Coverage parameters (glSampleCoverage, GL_SAMPLE_ALPHA_TO_COVERAGE, GL_SAMPLE_ALPHA_TO_ONE, GL_SAMPLE_COVERAGE, GL_SAMPLE_COVERAGE_VALUE, GL_SAMPLE_COVERAGE_INVERT). Reviewed-by: Ian Romanick <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965/msaa: Implement manual blending operation for Gen7.Paul Berry2012-05-251-23/+67
| | | | | | | | | | | | | | | On Gen6, the blending necessary to blit an MSAA surface to a non-MSAA surface could be accomplished with a single texturing operation. On Gen7, the WM program must fetch each sample and blend them together manually. From the Bspec (Shared Functions/Messages/Initiating Message/Message Types/sample): [DevIVB+]:Number of Multisamples on the associated surface must be MULTISAMPLECOUNT_1. This patch implements the manual blend operation. Acked-by: Kenneth Graunke <[email protected]>
* i965/msaa: Modify blorp code to account for Gen7 MSAA layouts.Paul Berry2012-05-253-68/+151
| | | | | | | | | | | | | | | | | | | Since blorp uses color textures and render targets to do all its work (even when blitting stencil and depth data), it always has to configure the Gen7 GPU to use the new "sliced" MSAA layout. However, when blitting stencil or depth data, the actual MSAA layout is interleaved (as in Gen6). Therefore, blorp has to do extra coordinate transformation work to account for the interleaving manually. This patch causes blorp to perform the necessary extra coordinate transformations. It also modifies the blorp SURFACE_STATE setup code for Gen7, so that it does not try to correct the surface width and height to account for MSAA, since "sliced" MSAA layout doesn't affect the surface width or height. Acked-by: Kenneth Graunke <[email protected]>
* i965/msaa: Validate Gen7 surface state constraints.Paul Berry2012-05-253-3/+109
| | | | | | | | | When a Gen7 SURFACE_STATE is configured for MSAA, a number of additional constaints come in to play. This patch adds a function gen7_check_surface_setup() which verifies that all of those constraints are met. Reviewed-by: Kenneth Graunke <[email protected]>
* i965/msaa: Properly handle sliced layout for Gen7.Paul Berry2012-05-2510-58/+162
| | | | | | | | | | | | | | | | | | | | | | | | | Starting in Gen7, there are two possible layouts for MSAA surfaces: - Interleaved, in which additional samples are accommodated by scaling up the width and height of the surface. This is the only layout available in Gen6. On Gen7 it is used for depth and stencil surfaces only. - Sliced, in which the surface is stored as a 2D array, with array slice n containing all pixel data for sample n. On Gen7 this layout is used for color surfaces. The "Sliced" layout has an additional requirement: it must be used in ARYSPC_LOD0 mode, which means that the surface doesn't leave any extra room between array slices for miplevels other than 0. This patch modifies the surface allocation functions to use the correct layout when allocating MSAA surfaces in Gen7, and to set the array offsets properly when using ARYSPC_LOD0 mode. It also modifies the code that populates SURFACE_STATE structures to ensure that ARYSPC_LOD0 mode is selected in the appropriate circumstances. Reviewed-by: Kenneth Graunke <[email protected]>
* i965/msaa: Add defines for Gen7.Paul Berry2012-05-251-0/+5
| | | | | | Reviewed-by: Chad Versace <[email protected]> Reviewed-by: Ian Romanick <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965/blorp: Enable blorp blits on Gen7.Paul Berry2012-05-252-2/+4
| | | | | | | | | | | | | Gen7 support for blorp (blits using the render bath) now works for non-MSAA purposes. This patch enables it. Since blorp operations re-use the logic for HiZ ops, this required adding a case to the switch statement in gen7_blorp_emit_wm_config(), to allow for the case where no HiZ op is being performed. Reviewed-by: Chad Versace <[email protected]> Reviewed-by: Ian Romanick <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965/blorp: Implement proper texel fetch messages for Gen7.Paul Berry2012-05-252-2/+31
| | | | | | | | | | | | | | | | | On Gen6, texel fetch is always accomplished using the SAMPLE_LD message, which accepts arguments (u, v, r, lod, si). On Gen7, there are two* texel fetch messages: SAMPLE_LD for non-MSAA surfaces, taking arguments (u, lod, v), and SAMPLE_LD2DSS for MSAA surfaces, taking arguments (si, u, v). *Technically, there are other texel fetch messages, but they are used for "compressed" MSAA surfaces, which we don't yet support. This patch adds the proper message types and argument orderings for Gen7. Reviewed-by: Ian Romanick <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965/blorp: Use 16 pixel dispatch on Gen7.Paul Berry2012-05-251-1/+9
| | | | | | | | | | | | | | | | | Gen7 hardware requires us to enable at least one WM dispatch mode, even if there is no program being dispatched to. When this code was only used for HiZ operations (which don't use a WM program), we used 32-pixel dispatch, because it didn't matter. But blit programs are compiled for 16-pixel dispatch. So just enable 16-wide dispatch unconditionally. Reviewed-by: Chad Versace <[email protected]> Reviewed-by: Ian Romanick <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> v2: Enable 16-wide dispatch unconditionally rather than add the unnecessary complication of using 32-wide dispatch when there is no WM program.
* i965/blorp: Allocate space for push constants on Gen7.Paul Berry2012-05-253-30/+28
| | | | | | | | | | | | | | | | | | On Gen7, push constants for shader programs are stored in the URB, so blorp code needs to set aside space for them. This was previously unnecessary because blorp code was based on HiZ operations, which don't require any shaders. This patch adds a call from gen7_blorp_exec() to gen7_allocate_push_constants(), to ensure that push constants are assigned the correct location in the URB. It also extracts a new function gen7_emit_urb_state() from gen7_upload_urb(), which is re-used by gen7_blorp_emit_urb_config() to ensure that the URB regions used by all the pipeline stages leave room for the push constants. Reviewed-by: Chad Versace <[email protected]> Reviewed-by: Ian Romanick <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965/blorp: Set the dynamic state upper bound.Paul Berry2012-05-251-1/+6
| | | | | | | | | | | We know from previous bug fixes (commits c25e5300cba7628b58df93ead14ebc3cc32f338c and b2ace06cbbbb1021e2d7ace12a985c6406821939) that texture border color doesn't work if the dynamic state upper bound is set to 0. Although the blorp engine doesn't make use of texture borders, it seems like we ought to err on the safe side and set this value properly. Reviewed-by: Kenneth Graunke <[email protected]>
* i965/blorp: Factor gen6_blorp_emit_batch_head into separate functions.Paul Berry2012-05-253-34/+49
| | | | | | | | | | | | This patch separates out the portions of gen6_blorp_emit_batch_head() that emit 3DSTATE_MULTISAMPLE, 3DSTATE_SAMPLE_MASK, and STATE_BASE_ADDRESS. This paves the way for making the blorp code work on Gen7, where additional command packets (3DSTATE_PUSH_CONSTANT_ALLOC_VS and 3DSTATE_PUSH_CONSTANT_ALLOC_PS) need to be emitted before 3DSTATE_MULTISAMPLE. Reviewed-by: Chad Versace <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965/blorp: Use MSDISPMODE_PERSAMPLE rendering when necessaryPaul Berry2012-05-254-27/+87
| | | | | | | | | | | | | | This patch modifies the "blorp" WM program so that it can be run in MSDISPMODE_PERSAMPLE (which means that every single sample of a multisampled render target is dispatched to the WM program, not just every pixel). Previously we were using the ugly hack of configuring multisampled destination surfaces as single-sampled, and generating sample indices other than zero by swizzling the pixel coordinates in the WM program. Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* i965/blorp: Emit sample index in SAMPLE_LD message when necessaryPaul Berry2012-05-252-21/+36
| | | | | | | | | | | | | This patch modifies the function brw_blorp_blit_program::texel_fetch() to emit the SI (sample index) argument to the SAMPLE_LD message when reading from a sample index other than zero. Previously we were using the ugly hack of configuring multisampled source surfaces as single-sampled, and accessing sample indices other than zero by swizzling the texture coordinates in the WM program. Reviewed-by: Ian Romanick <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965/blorp: Generalize sampling code in preparation for Gen7Paul Berry2012-05-251-26/+61
| | | | | | | | | | | | | | | | This patch generalizes the function brw_blorp_blit_program::texture_lookup() so that it prepares the arguments to the sampler message based on a caller-provided array rather than assuming the argument order is always (u, v). This paves the way for the messages we will need to use in Gen7, which use argument orders (u, lod, v) and (si, u, v) (si=sample index). It will also will allow us to read from arbitrary sample indices on Gen6, by supplying the arguments (u, v, r, lod, si) to the SAMPLE_LD message instead of just (u, v). Reviewed-by: Kenneth Graunke <[email protected]>
* i965/msaa: Expand odd-sized MSAA surfaces to account for interleaving pattern.Paul Berry2012-05-251-5/+40
| | | | | | | | | | | | | | | Gen6 MSAA buffers (and Gen7 MSAA depth/stencil buffers) interleave MSAA samples in a complex pattern that repeats every 2x2 pixel block. Therefore, when allocating an MSAA buffer, we need to make sure to allocate an integer number of 2x2 blocks; if we don't, then some of the samples in the last row and column will be cut off. Fixes piglit tests "EXT_framebuffer_multisample/unaligned-blit {2,4} color msaa" on i965/Gen6. Acked-by: Kenneth Graunke <[email protected]> Reviewed-by: Chad Versace <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* i965: Gut the separate OpenGL ES extension enabling.Kenneth Graunke2012-05-237-148/+4
| | | | | | | | | | | | | | | | | | | | | | | | We should just set the bits of functionality that we support; the GL/ES1/ES2 flags in extensions.c will take care of advertising the appropriate extensions for the current API. This enables the GL_EXT_texture_compression_dxt1 extension on ES1/ES2 when libtxc_dxtn is installed or the force_s3tc driconf option is set. The main extension code set this up properly, but the ES-specific code failed to do so. Otherwise, the extension strings reported by es1_info, es2_info, and glxinfo all remain the same. This patch manually disables the ARB_framebuffer_object bit on ES to preserve the behavior of 1c0f5d8324c4db2720247989ddc4a45315b55a85. v2: Rebase, fix the i915 Makefile, and unconditionally set the OES_draw_texture bit as core Mesa will only apply it to ES1 now. Tested-by: Daniel Charles <[email protected]> [v1] Reviewed-by: Chad Versace <[email protected]> [v1] Signed-off-by: Kenneth Graunke <[email protected]>
* mesa: Remove the OES_draw_texture extension from ES2.Kenneth Graunke2012-05-231-1/+1
| | | | | | | | | This extension appears to be written against ES 1.0. In ES 2.0, you really want to be using FBOs instead. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Ian Romanick <[email protected]> Reviewed-by: Chad Versace <[email protected]>
* i965: use cut index to handle primitive restart when possibleJordan Justen2012-05-231-1/+80
| | | | | | | | | | | | | If the primitive restart index and the primitive type can be handled by the cut index feature, then use the hardware to handle the primitive restart feature. The VBO module's software handling of primitive restart is used as a fall back. Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* i965: add flag to enable cut_indexJordan Justen2012-05-234-1/+12
| | | | | | | | | When brw->prim_restart.enable_cut_index is set, the cut index will be enabled when uploading index_buffer commands. Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* i965: create code path to handle primitive restart in hardwareJordan Justen2012-05-237-0/+112
| | | | | | | | | | | | | | For newer hardware we disable the VBO module's software handling of primitive restart. We now handle primitive restarts in brw_handle_primitive_restart. The initial version of brw_handle_primitive_restart simply calls vbo_sw_primitive_restart, and therefore still uses the VBO module software primitive restart support. Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* mesa: Use initializers to configure samplersIan Romanick2012-05-231-32/+9
| | | | | | | | | Now that the linker handles initializers of samplers just like any other uniform, a bunch of this annoying code is unnecessary. Signed-off-by: Ian Romanick <[email protected]> Reviewed-by: Eric Anholt <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* ir_to_mesa: Don't set initial uniform values againIan Romanick2012-05-231-104/+0
| | | | | | | | | This work is now done by the linker, so we don't need to keep doing it here. Signed-off-by: Ian Romanick <[email protected]> Reviewed-by: Eric Anholt <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* ir_to_mesa: Propagate initial values in _mesa_associate_uniform_storageIan Romanick2012-05-231-0/+9
| | | | | | | | | The linker may have set initial values for uniforms. Propagate these values to the driver's backing storage when it is first associated. Signed-off-by: Ian Romanick <[email protected]> Reviewed-by: Eric Anholt <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* glsl: Initialize samplers to 0, propagate sampler values to the gl_programIan Romanick2012-05-231-0/+1
| | | | | | | | | | | | | The spec requires that samplers be initialized to 0. Since this differs from the 1-to-1 mapping of samplers to texture units assumed by ARB assembly shaders (and the gl_program structure), be sure to propagate this date from the gl_shader_program to the gl_program. Signed-off-by: Ian Romanick <[email protected]> Reviewed-by: Eric Anholt <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> CC: Vadim Girlin <[email protected]> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=49088
* i965/gen6+: Add support for GL_ARB_blend_func_extended.Eric Anholt2012-05-2313-8/+112
| | | | | | | v2: Add support for gen6, and don't turn it on if blending is disabled. (fixes GPU hang), and note it in docs/GL3.txt Reviewed-by: Kenneth Graunke <[email protected]>
* mesa: Keep a computed value for dual source blend func with each buffer.Eric Anholt2012-05-233-17/+32
| | | | | | | | | The i965 driver needed this as well for hardware setup, so instead of duplicating the logic, just save it off. Reviewed-by: Ian Romanick <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Dave Airlie <[email protected]>
* i965/gen6+: Add support for fast depth clears.Eric Anholt2012-05-238-12/+150
| | | | | | | | | | Improves citybench high-res performance 3.0% +- 0.4%, n=10. Improves Lightsmark 1024x768 performance 0.74% +/- 0.20% (n=78). No significant difference on openarena (n=5, didn't fast clear) or nexuiz (n=3). Reviewed-by: Ian Romanick <[email protected]> Reviewed-by: Chad Versace <[email protected]>
* i965/gen6: Add CC viewport state setup to blorp code.Eric Anholt2012-05-231-0/+26
| | | | | | | | While it doesn't have the same warning in the simulator as in gen7, let's emit it out of paranoia. We wouldn't want our resolves of some previous clear to get clamped to some current clamping value. Suggested-by: pretty much everyone
* i965/gen7: Add CC viewport setup to blorp code.Eric Anholt2012-05-231-0/+21
| | | | | | | | | | | | | | | When doing fast clears, a fulsim warning said that the batch was being emitted without the viewport set up. While the fast clear pass I was looking at doesn't use the clear value, the later resolves which also didn't set up the vieport would trigger the same. It's not obvious from the error message whether it meant "fast clear value gets clamped to something you haven't defined" or "fast clear value doesn't get clamped, and I saw it was out of the current (uninitialized) range, and you probably wanted it clamped to that (uninitialized) range". Be paranoid and assume the first case. Reviewed-by: Ian Romanick <[email protected]> Reviewed-by: Chad Versace <[email protected]>
* i965: Drop a layer of indirection in doing HiZ resolves.Eric Anholt2012-05-237-120/+9
| | | | | Reviewed-by: Ian Romanick <[email protected]> Reviewed-by: Chad Versace <[email protected]>
* i965: Replace intel_need_resolve with the hiz ops it maps to.Eric Anholt2012-05-233-17/+21
| | | | | | | | Having this enum separate caused us to need a bunch of helper functions to translate to the op to be executed. Reviewed-by: Ian Romanick <[email protected]> Reviewed-by: Chad Versace <[email protected]>
* i965: Add an interface for doing hiz ops from C code.Eric Anholt2012-05-234-15/+44
| | | | | | | | This required moving gen6_hiz_op, and I put it in intel_resolve_map.h for the next commit. Reviewed-by: Ian Romanick <[email protected]> Reviewed-by: Chad Versace <[email protected]>
* i965: Rename the clear function for this driver.Eric Anholt2012-05-231-2/+2
| | | | | Reviewed-by: Ian Romanick <[email protected]> Reviewed-by: Chad Versace <[email protected]>
* i965: Simplify the remaining clear logic by relying on the meta clear.Eric Anholt2012-05-231-47/+11
| | | | | | | | The GLSL clear path doesn't need any buffer presence checks, since those are already handled in the normal drawing path code. Reviewed-by: Ian Romanick <[email protected]> Reviewed-by: Chad Versace <[email protected]>
* i965: Switch blit color clears to tri clears on gen4/5.Eric Anholt2012-05-231-28/+2
| | | | | | | | | | | | | | Our understanding is that the 3D engine is supposed to be faster anyway. We used to have more overhead in our tri clear path than we do today, which would have led to this choice. But given that we almost always see a depth clear along with a color clear, the path was hardly exercised anyway. Also, the color mask logic was broken in the presence of GL_EXT_draw_buffers2's per-buffer colormask. Reviewed-by: Ian Romanick <[email protected]> Reviewed-by: Chad Versace <[email protected]>
* i965: Remove dead logic for non-tri depth/stencil clears.Eric Anholt2012-05-231-26/+2
| | | | | Reviewed-by: Ian Romanick <[email protected]> Reviewed-by: Chad Versace <[email protected]>
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