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* i965: Implement ARB_query_buffer_object for HSW+Jordan Justen2016-05-048-3/+501
| | | | | | | | | | | | | | | v2: * Declare loop index variable at loop site (idr) * Make arrays of MI_MATH instructions 'static const' (idr) * Remove commented debug code (idr) * Updated comment in set_query_availability (Ken) * Replace switch with if/else in hsw_result_to_gpr0 (Ken) * Only divide GL_FRAGMENT_SHADER_INVOCATIONS_ARB by 4 on hsw and gen8 (Ken) Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* i965/gen6+: Add load register immediate helper functionsJordan Justen2016-05-042-0/+36
| | | | | Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965/hsw+: Add support for copying a registerJordan Justen2016-05-043-0/+18
| | | | | Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965/gen6+: Add support for storing immediate data into a bufferJordan Justen2016-05-043-0/+50
| | | | | Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Add MI_MATH reg defs for HSW+Jordan Justen2016-05-041-0/+38
| | | | | Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Add brw_store_register_mem32Jordan Justen2016-05-042-0/+28
| | | | | Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Use offset instead of index in brw_store_register_mem64Jordan Justen2016-05-045-54/+52
| | | | | | | | | | This matches the byte based offset of brw_load_register_mem*. The function is also moved into intel_batchbuffer.c like brw_load_register_mem*. Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Delete stale perf_debug().Kenneth Graunke2016-05-041-2/+0
| | | | MOCS for 3DSTATE_SO_BUFFER has existed for ages.
* i965: Silence unused variable warningKenneth Graunke2016-05-041-2/+0
| | | | I added this when deleting some unnecessary code in a rebase.
* mesa/main: handle double uniform matrices properlyJuan A. Suarez Romero2016-05-041-1/+1
| | | | | | | | When computing the offset in the uniform storage table, take into account the size multiplier so double precision matrices are handled correctly. Signed-off-by: Juan A. Suarez Romero <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* nir: Separate 32 and 64-bit fmod loweringSamuel Iglesias Gonsálvez2016-05-041-1/+1
| | | | | | | | Split 32-bit and 64-bit fmod lowering as the drivers might need to lower them separately inside NIR depending on the HW support. Signed-off-by: Samuel Iglesias Gonsálvez <[email protected]> Reviewed-by: Jordan Justen <[email protected]>
* i965: Define GEN_GE/GEN_LE macros in terms of GEN_LT.Matt Turner2016-05-031-2/+3
| | | | | | | | GEN_LT has a straightforward implementation on which we can build the GEN_GE and GEN_LE macros. Suggested-by: Ilia Mirkin <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Add disassembler support for remaining opcodes.Matt Turner2016-05-032-18/+92
| | | | | | | | | For opcodes that changed meaning on different generations, we store a pointer to a secondary table and the table's size in a tagged union in place of the mnemonic and number of sources. Acked-by: Francisco Jerez <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Make opcode_descs and gen_from_devinfo() static.Matt Turner2016-05-032-6/+2
| | | | | | | | | The previous commit replaced direct uses of opcode_descs with calls to the wrapper function, which should be the only method of accessing opcode_descs's data. As a result gen_from_devinfo() can also be made static. Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Actually check whether the opcode is supported.Matt Turner2016-05-032-4/+3
| | | | Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Merge inst_info and opcode_desc tables.Matt Turner2016-05-035-149/+73
| | | | | | | I merged opcode_desc into inst_info (instead of the other way around) because inst_info was sorted by opcode number. Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Move inst_info from brw_eu_validate.c to brw_eu.c.Matt Turner2016-05-033-245/+249
| | | | | | | | | Drop the uses of 'enum gen' to a plain int, so that we don't have to expose the bitfield definitions and GEN_GE/GEN_LE macros to other users of brw_eu.h. As a result, s/.gen/.gens/ to avoid confusion with devinfo->gen. Reviewed-by: Kenneth Graunke <[email protected]>
* i965/disasm: Wrap opcode_desc look-up in a function.Francisco Jerez2016-05-035-14/+42
| | | | | | | | | | | | | | The function takes a device info struct as argument in addition to the opcode number in order to disambiguate between multiple opcode_desc entries for different instructions with the same opcode number. Reviewed-by: Iago Toral Quiroga <[email protected]> [v1] [v2] mattst88: Put brw_opcode_desc() in brw_eu.c instead of moving it there in a later patch. Reviewed-by: Kenneth Graunke <[email protected]> [v2] [v3] mattst88: Return NULL if opcode >= ARRAY_SIZE(opcode_descs) Reviewed-by: Matt Turner <[email protected]>
* i965: Pass devinfo pointer to is_3src() helpers.Francisco Jerez2016-05-038-10/+11
| | | | | | | | | | | | | | This is not strictly required for the following changes because none of the three-source opcodes we support at the moment in the compiler back-end has been removed or redefined, but that's likely to change in the future. In any case having hardware instructions specified as a pair of hardware device and opcode number explicitly in all cases will simplify the opcode look-up interface introduced in a subsequent commit, since the opcode number alone is in general ambiguous. Reviewed-by: Iago Toral Quiroga <[email protected]> Reviewed-by: Matt Turner <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Pass devinfo pointer to brw_instruction_name().Francisco Jerez2016-05-034-4/+5
| | | | | | | | | | | | A future series will implement support for an instruction that happens to have the same opcode number as another instruction we support already on a disjoint set of hardware generations. In order to disambiguate which instruction it is brw_instruction_name() will need some way to find out which device we are generating code for. Reviewed-by: Iago Toral Quiroga <[email protected]> Reviewed-by: Matt Turner <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Write a scalar TCS backend that runs in SINGLE_PATCH mode.Kenneth Graunke2016-05-037-15/+510
| | | | | | | | | | | | | | | | | | | | | | | Unlike most shader stages, the Hull Shader hardware makes us explicitly tell it how many threads to dispatch and manually configure the channel mask. One perk of this is that we have a lot of flexibility - we can run it in either SIMD4x2 or SIMD8 mode. Treating it as SIMD8 means that shaders with 8 or fewer output vertices (which is overwhemingly the common case) can be handled by a single thread. This has several intriguing properties: - Accessing input arrays with gl_InvocationID as the index is a simple SIMD8 URB read with g1 as the header. No indirect addressing required. - Barriers are no-ops. - We could potentially do output shadowing to combine writes, as the concurrency concerns are gone. (We don't do this yet, though.) v2: Drop first_non_payload_grf change, as it was always adding 0 (caught by Jordan Justen). Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Jordan Justen <[email protected]>
* i965: Rework the TCS passthrough shader to use NIR.Kenneth Graunke2016-05-033-56/+85
| | | | | | | | | | | | | | | I'm about to implement a scalar TCS backend, and I'd rather not duplicate all of this code there. One change is that we now write the tessellation levels from all TCS threads, rather than just the first. This is pretty harmless, and was easier. The IF/ENDIF needed for that are gone; otherwise the generated code is basically identical. I chose to emit load/store intrinsics directly because it was easier. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Jordan Justen <[email protected]>
* mesa/objectlabel: handle NULL src stringMark Janes2016-05-031-3/+4
| | | | | | | | | | This prevents a crash when a NULL src is passed with a non-NULL length. fixes: dEQP-GLES31.functional.debug.object_labels.query_length_only Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=95252 Signed-off-by: Mark Janes <[email protected]> Reviewed-by: Dave Airlie <[email protected]>
* swrast: Add texfetch_funcs entries for astc 3d formatsAnuj Phogat2016-05-031-1/+22
| | | | | Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Brian Paul <[email protected]>
* mesa: Enable translation between astc 3d gl formats and mesa formatsAnuj Phogat2016-05-031-0/+80
| | | | | Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Brian Paul <[email protected]>
* mesa: Handle astc 3d formats in _mesa_get_compressed_formats()Anuj Phogat2016-05-031-0/+29
| | | | | Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Brian Paul <[email protected]>
* mesa: Handle astc 3d formats in _mesa_base_tex_format()Anuj Phogat2016-05-031-2/+4
| | | | | Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Brian Paul <[email protected]>
* mesa: Account for astc 3d formats in _mesa_is_astc_format()Anuj Phogat2016-05-031-3/+13
| | | | | Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Brian Paul <[email protected]>
* mesa: Add a helper function is_astc_3d_format()Anuj Phogat2016-05-031-0/+32
| | | | | Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Brian Paul <[email protected]>
* mesa: Add the missing defines for GL_OES_texture_compression_astcAnuj Phogat2016-05-031-0/+23
| | | | | Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Brian Paul <[email protected]>
* mesa: Align the values of #define's in glheader.hAnuj Phogat2016-05-031-29/+29
| | | | | Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Brian Paul <[email protected]>
* mesa: Add OES_texture_compression_astc to extension table and gl_extensionsAnuj Phogat2016-05-032-0/+2
| | | | | Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Brian Paul <[email protected]>
* mesa: Add entries for astc 3d formats initializing struct gl_format_infoAnuj Phogat2016-05-031-0/+21
| | | | | Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Brian Paul <[email protected]>
* mesa: Add mesa formats for astc 3d formatsAnuj Phogat2016-05-031-0/+21
| | | | | Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Brian Paul <[email protected]>
* mesa: Account for block depth in _mesa_format_image_size()Anuj Phogat2016-05-031-21/+23
| | | | | Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Brian Paul <[email protected]>
* mesa: Handle 3d block sizes in _mesa_compute_compressed_pixelstoreAnuj Phogat2016-05-031-3/+3
| | | | | Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Brian Paul <[email protected]>
* mesa: Handle 3d block sizes in teximage error checksAnuj Phogat2016-05-031-6/+13
| | | | | Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Brian Paul <[email protected]>
* mesa: Handle 3d block sizes in getteximage error checksAnuj Phogat2016-05-031-4/+17
| | | | | Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Brian Paul <[email protected]>
* mesa: Add an assert for BlockDepth in _mesa_get_format_block_size()Anuj Phogat2016-05-031-0/+3
| | | | | Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Brian Paul <[email protected]>
* mesa: Add a helper function to query 3D block sizesAnuj Phogat2016-05-032-0/+25
| | | | | Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Brian Paul <[email protected]>
* mesa: Add block depth field in struct gl_format_infoAnuj Phogat2016-05-034-274/+279
| | | | | | | This will be later required for 3D ASTC formats. Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Brian Paul <[email protected]>
* mesa/copyimage: make sure number of samples match.Dave Airlie2016-05-031-0/+14
| | | | | | | | | This fixes GL43-CTS.copy_image.samples_missmatch which otherwise asserts in the radeonsi driver. Reviewed-by: Anuj Phogat <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* mesa/objectlabel: don't do memcpy if bufSize is 0 (v2)Dave Airlie2016-05-031-0/+5
| | | | | | | | | | This prevents GL43-CTS.khr_debug.labels_non_debug from memcpying all over the stack and crashing. v2: actually fix the test. Reviewed-by: Alejandro Piñeiro <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* mesa/textureview: move error checks up higherDave Airlie2016-05-031-24/+26
| | | | | | | | | | | | GL43-CTS.texture_view.errors checks for GL_INVALID_VALUE here but we catch these problems in the dimensionsOK check and return the wrong error value. This fixes: GL43-CTS.texture_view.errors. Reviewed-by: Anuj Phogat <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* st/mesa: fix blit-based GetTexImage for non-finalized texturesMarek Olšák2016-05-021-1/+2
| | | | | | | | This fixes getteximage-depth piglit failures on radeonsi. Cc: 11.1 11.2 <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* vbo: avoid leaking prim on vbo bind failureIlia Mirkin2016-05-011-1/+3
| | | | | | | Spotted by Coverity Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Vinson Lee <[email protected]>
* mesa: add LOCATION_COMPONENT support to GetProgramResourceivTimothy Arceri2016-05-012-0/+15
| | | | | | | | | | | | From Section 7.3.1.1 (Naming Active Resources) of the OpenGL 4.5 spec: "For the property LOCATION_COMPONENT, a single integer indicating the first component of the location assigned to an active input or output variable is written to params. For input and output variables with a component specified by a layout qualifier, the specified component is written. For all other input and output variables, the value zero is written." Reviewed-by: Anuj Phogat <[email protected]>
* glShaderSource must not change compile status.Jamey Sharp2016-05-011-1/+0
| | | | | | | | | | | | | | | | OpenGL 4.5 Core Profile section 7.1, in the documentation for CompileShader, says: "Changing the source code of a shader object with ShaderSource does not change its compile status or the compiled shader code." According to Karol Herbst, the game "Divinity: Original Sin - Enhanced Edition" depends on this odd quirk of the spec. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=93551 Signed-off-by: Jamey Sharp <[email protected]> Reviewed-by: Ian Romanick <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Timothy Arceri <[email protected]>
* i965: don't forget to ship brw_nir_trig_workarounds.pyEmil Velikov2016-05-011-0/+3
| | | | | | Otherwise we won't be able to regenerate the source file(s). Signed-off-by: Emil Velikov <[email protected]>
* glx: Refactor the configure options for glx implementation choice (v3)Chuck Atkins2016-05-011-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Instead of cascading support for various different implementations of GLX, all three options are now specified through the --enable-glx option: --enable-glx=dri : Enable the DRI-based GLX --enable-glx=xlib : Enable the classic Xlib-based GLX --enable-glx=gallium-xlib : Enable the gallium Xlib-based GLX --enable-glx[=yes] : Defaults to dri if DRI is enabled, else gallium-xlib if gallium is enabled, else xlib This removes the --enable-xlib-glx option and fixes a bug in which both the classic xlib-glx and gallium xlib-glx implementations were getting built causing different versioned and conflicting libGL libraries to be installed. v2: Changes from various review feedback from Emil: a) Fixed typos b) Corrected help docs for new option c) Added appropriate a-b and r-b tags in commit msg d) Fixed various GLX related dependency checks. v3: Rebased to current master and added changelog in commit msg Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=94086 Acked-by: Brian Paul <[email protected]> Reviewed-by: Emil Velikov <[email protected]>
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