summaryrefslogtreecommitdiffstats
path: root/src/mesa
Commit message (Expand)AuthorAgeFilesLines
...
* r200: Drop unused variable.Eric Anholt2015-02-121-1/+0
* i965: Quiet another compiler warning about uninitialized values.Eric Anholt2015-02-121-2/+2
* i965: Move some asserts to unreachable.Eric Anholt2015-02-121-2/+2
* i965: Shut up a compiler warning about uninitialized var.Eric Anholt2015-02-121-1/+1
* Revert use of Mesa IR optimizer for ARB_fragment_programsCarl Worth2015-02-121-3/+0
* i965/vs/skl: Use vec4 datatypes for message headerBen Widawsky2015-02-111-2/+2
* i965: Add LINTERP/CINTERP to can_do_cmod().Matt Turner2015-02-111-0/+2
* program: Remove _mesa_nop_vertex_program/_mesa_nop_fragment_program.Matt Turner2015-02-112-97/+0
* i965/fs: Remove conditional mod when optimizing a SEL into a MOV.Matt Turner2015-02-111-0/+1
* i965/vec4: Emit MADs from (x + abs(y * z)).Matt Turner2015-02-101-3/+15
* i965/vec4: Emit MADs from (x + -(y * z)).Matt Turner2015-02-101-0/+12
* i965/skl: Implement WaDisable1DDepthStencilNeil Roberts2015-02-101-0/+12
* i965/gen7-8: Implement glMemoryBarrier().Francisco Jerez2015-02-102-0/+41
* i965: Generalize the update_null_renderbuffer_surface vtbl hook to non-render...Francisco Jerez2015-02-104-56/+55
* i965: Allocate binding table space for shader images.Francisco Jerez2015-02-102-0/+12
* i965: Don't tile 1D miptrees.Francisco Jerez2015-02-101-0/+7
* i965/vec4: Don't set any dependency control bits for F32TO16 on Gen8.Francisco Jerez2015-02-101-0/+5
* i965: Handle negated unsigned immediate values in constant propagation.Francisco Jerez2015-02-103-19/+19
* i965/vec4: Take into account non-zero reg_offset during register allocation.Francisco Jerez2015-02-101-1/+3
* i965/vec4: Add register classes up to MAX_VGRF_SIZE.Francisco Jerez2015-02-103-7/+9
* i965/vec4: Init mlen for several send from GRF instructions.Francisco Jerez2015-02-103-5/+11
* i965/vec4: Don't infer MRF dependencies for send from GRF instructions.Francisco Jerez2015-02-101-14/+18
* i965/vec4: Fix the scheduler to take into account reads and writes of multipl...Francisco Jerez2015-02-103-5/+29
* i965/vec4: Make vec4_visitor::implied_mrf_writes() return zero for sends from...Francisco Jerez2015-02-101-1/+1
* i965/vec4: Pass dst register to the vec4_instruction constructor.Francisco Jerez2015-02-101-7/+5
* i965/vec4: Initialize vec4_instruction::predicate and ::predicate_inverse.Francisco Jerez2015-02-101-0/+2
* i965/vec4: Implement equals() method for dst_reg too.Francisco Jerez2015-02-102-0/+18
* i965/fs: Fix fs_inst::regs_written calculation for instructions with scalar dst.Francisco Jerez2015-02-101-1/+2
* i965/fs: Fix stack allocation of fs_inst and stop stealing src array provided...Francisco Jerez2015-02-102-37/+39
* i965/fs: Remove duplicate include of brw_shader.hFrancisco Jerez2015-02-101-1/+0
* i965: Move up fs_inst::flag_subreg to backend_instruction.Francisco Jerez2015-02-105-7/+16
* i965: Move up fs_inst::regs_written to backend_instruction.Francisco Jerez2015-02-103-1/+2
* i965/vec4: Remove dependency of vec4_instruction on the visitor class.Francisco Jerez2015-02-103-36/+32
* i965/fs: Remove dependency of fs_inst on the visitor class.Francisco Jerez2015-02-107-13/+12
* i965: Move IR object definitions to separate header files.Francisco Jerez2015-02-104-381/+450
* i965: Factor out virtual GRF allocation to a separate object.Francisco Jerez2015-02-1018-201/+235
* mesa: Bump MAX_IMAGE_UNIFORMS to 32.Francisco Jerez2015-02-101-1/+1
* mesa: Rename the CEILING() macro to DIV_ROUND_UP().Francisco Jerez2015-02-103-3/+3
* i965: Fix integer border color on Haswell.Kenneth Graunke2015-02-093-0/+66
* i965: Use a gl_color_union for sampler border color.Kenneth Graunke2015-02-091-53/+52
* i965: Override swizzles for integer luminance formats.Kenneth Graunke2015-02-091-0/+8
* mesa: Make renderbuffer FBO attachments not layeredJames Legg2015-02-081-0/+1
* i965: Add more stringent blitter assertionsBen Widawsky2015-02-071-0/+3
* i965: Consolidate some of the intel_blit logicBen Widawsky2015-02-071-20/+8
* i965/vec4: Correct MUL destination hazardBen Widawsky2015-02-061-4/+4
* i965: Fix INTEL_DEBUG=shader_time for SIMD8 VS (and GS).Kenneth Graunke2015-02-051-9/+25
* i965/fs: Use inst->eot rather than opcodes in register allocation.Kenneth Graunke2015-02-051-11/+10
* i965/fs: Delete is_last_send(); just check inst->eot.Kenneth Graunke2015-02-051-14/+1
* st/mesa: Don't use PIPE_USAGE_STREAM for GL_PIXEL_UNPACK_BUFFER_ARBMichel Dänzer2015-02-061-2/+9
* i965: Remove now unnecessary Gen8 CMP destination type override.Matt Turner2015-02-041-8/+0
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-27 13:42:39 +0000