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* st/mesa: add double input support including lowering (v3.1)Dave Airlie2015-05-085-45/+164
| | | | | | | | | | | | | | | | | This takes a different approach to previously, we cannot index into the inputMapping with anything but the mesa attribute index, so we can't use the just add one to index trick, we need more info to add one to it after we've mapped the input. (Fixed copy propgation and cleaned up a little) v2: drop float64 format check, just attr->Doubles. merge enable patch. v3: cleanup code a bit. v3.1: minor review fixups (comment, newline) (Ilia) Reviewed-by: Ilia Mirkin <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* mesa/vbo: add support for 64-bit vertex attributes. (v1)Dave Airlie2015-05-0813-55/+377
| | | | | | | | | | | | This adds support in the vbo and array code to handle double vertex attributes. v0.2: merge code to handle doubles in vbo layer. v1: don't use v0, merge api_array elt code. Acked-by: Ilia Mirkin <[email protected]> Reviewed-by: Ian Romanick <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* glsl: track which program inputs are doublesDave Airlie2015-05-081-0/+1
| | | | | | | | instead of doing the attempts at dual slot handling here, let the backend do it. Reviewed-by: Ilia Mirkin <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* mesa: add ARB_vertex_attrib_64bit to extensions. (v2)Dave Airlie2015-05-083-1/+3
| | | | | | | | | | Just add the boilerplate bits. v2: add to version.c Reviewed-by: Ilia Mirkin <[email protected]> Reviewed-by: Ian Romanick <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* mapi: add GL_ARB_vertex_attrib_64bit supportDave Airlie2015-05-085-12/+77
| | | | | | | | This just adds the glapi bits. Reviewed-by: Ilia Mirkin <[email protected]> Reviewed-by: Ian Romanick <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* st/glsl_to_tgsi: fix ir_assignment hack doing bad things for doublesDave Airlie2015-05-081-0/+1
| | | | | | | | | | | This hack for fixing gl_FragDepth apparantly caused a GLSL shader outputting a single double to try and output a dvec4, but we hadn't assigned outputs for the secondary bit. This avoids going into the hack code for scalar doubles. Reviewed-by: Ilia Mirkin <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* i965/wm/gen6: Add option for disabling statistics collectionTopi Pohjolainen2015-05-072-4/+13
| | | | | | | | Normally this is always needed but for internal blits and clears we need to be able to disable it. Reviewed-by: Kenneth Graunke <[email protected]> Signed-off-by: Topi Pohjolainen <[email protected]>
* i965/wm/gen6: Refactor state setupTopi Pohjolainen2015-05-072-45/+77
| | | | | Reviewed-by: Kenneth Graunke <[email protected]> Signed-off-by: Topi Pohjolainen <[email protected]>
* i965: Remove unused variablesAnuj Phogat2015-05-071-2/+0
| | | | | Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Jordan Justen <[email protected]>
* i965: Change the order of conditions tested in ifAnuj Phogat2015-05-071-3/+4
| | | | | | | | Reduces the number of conditions tested in if to one in case of non-integer formats. Makes no functional changes. Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* i965/sync: Implement DRI2_Fence extensionChad Versace2015-05-073-39/+158
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This enables EGL_KHR_fence_sync and EGL_KHR_wait_sync. Below is the difference in piglit results, before and after this patch. No regressions and several tests improve from 'skip' to 'pass'. Out of EGL_KHR_fence_sync tests, two of the multithreaded tests skip; all other tests pass. cmdline: piglit run -p gbm -t sync tests/quick.py mesa: master@1ac7db0 piglit: 4069bec hw: Ivybridge | before after ------+------------- pass | 32 46 fail | 0 0 crash | 0 0 skip | 35 21 total | 67 67 v2: - Set fence->signalled = true in brw_fence_has_completed() too. Reviewed-by: Daniel Stone <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965/sync: Replace prefix 'intel_sync' -> 'intel_gl_sync'Chad Versace2015-05-072-28/+31
| | | | | | | | | | | | | | | | | | I'm about to implement DRI2_Fenc in intel_syncobj.c. To prevent madness, we need to prefix functions for GL_ARB_sync with 'gl' and functions for DRI2_Fence with 'dri'. Otherwise, the file will become a jumble of similiarly named functions. For example: old-name: intel_client_wait_sync() new-name: intel_gl_client_wait_sync() soon-to-come: intel_dri_client_wait_sync() I wrote this renaming commit separately from the commit that implements DRI2_Fence because I wanted the latter diff to be reviewable. Reviewed-by: Daniel Stone <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i915/sync: Return early when calloc failsChad Versace2015-05-071-0/+2
| | | | | Reviewed-by: Daniel Stone <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965/sync: Return NULL when calloc failsChad Versace2015-05-071-0/+2
| | | | | Reviewed-by: Daniel Stone <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i915/sync: Don't crash when deleting sync objectChad Versace2015-05-071-1/+3
| | | | | | | | | Don't pass NULL to drm_intel_bo_unreference(). It doesn't like that. Bug found by code inspection. Reviewed-by: Daniel Stone <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965/sync: Don't crash when deleting sync objectChad Versace2015-05-071-1/+3
| | | | | | | | | Don't pass NULL to drm_intel_bo_unreference(). It doesn't like that. Bug found by code inspection. Reviewed-by: Daniel Stone <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Sort extension enable listsIan Romanick2015-05-061-33/+42
| | | | | | | Sort by GEN, then sort by extension name. Signed-off-by: Ian Romanick <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* i965/fs: Allow copy propagation on ATTR file registers.Kenneth Graunke2015-05-061-1/+4
| | | | | | | | | | | | | | | | | | | | | | This especially helps with NIR because we currently emit MOVs at the top of the shader to copy from various ATTR registers to a giant VGRF array of all inputs. (This could potentially be done better, but since there's only ever one write to each register, it should be trivial to copy propagate away...) With NIR - only vertex shaders: total instructions in shared programs: 3129373 -> 2889581 (-7.66%) instructions in affected programs: 3119717 -> 2879925 (-7.69%) helped: 20833 Without NIR - only vertex shaders: total instructions in shared programs: 2745901 -> 2724483 (-0.78%) instructions in affected programs: 693426 -> 672008 (-3.09%) helped: 3516 Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Matt Turner <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* i965/fs_inst: Get rid of the effective_width fieldJason Ekstrand2015-05-063-37/+3
| | | | | | | | The effective_width field was an ill-concieved hack to get around issues in the LOAD_PAYLOAD instruction. Now that the LOAD_PAYLOAD instruction is far more sane, this field can die. Reviewed-by: Kenneth Graunke <[email protected]>
* i965/fs: Rework the fs_visitor LOAD_PAYLOAD instructionJason Ekstrand2015-05-064-236/+179
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The newly reworked instruction is far more straightforward than the original. Before, the LOAD_PAYLOAD instruction was lowered by a the complicated and broken-by-design pile of heuristics to try and guess force_writemask_all, exec_size, and a number of other factors on the sources. Instead, we use the header_size on the instruction to denote which sources are "header sources". Header sources are required to be a single physical hardware register that is copied verbatim. The registers that follow are considered the actual payload registers and have a width that correspond's to the LOAD_PAYLOAD's exec_size and are treated as being per-channel. This gives us a fairly straightforward lowering: 1) All header sources are copied directly using force_writemask_all and, since they are guaranteed to be a single register, there are no force_sechalf issues. 2) All non-header sources are copied using the exact same force_sechalf and force_writemask_all modifiers as the LOAD_PAYLOAD operation itself. 3) In order to accommodate older gens that need interleaved colors, lower_load_payload detects when the destination is a COMPR4 register and automatically interleaves the non-header sources. The lower_load_payload pass does the right thing here regardless of whether or not the hardware actually supports COMPR4. This patch commit itself is made up of a bunch of smaller changes squashed together. Individual change descriptions follow: i965/fs: Rework fs_visitor::LOAD_PAYLOAD We rework LOAD_PAYLOAD to verify that all of the sources that count as headers are, indeed, exactly one register and that all of the non-header sources match the destination width. We then take the exec_size for LOAD_PAYLOAD directly from the destination width. i965/fs: Make destinations of load_payload have the appropreate width i965/fs: Rework fs_visitor::lower_load_payload v2: Don't allow the saturate flag on LOAD_PAYLOAD instructions i965/fs_cse: Support the new-style LOAD_PAYLOAD i965/fs_inst::is_copy_payload: Support the new-style LOAD_PAYLOAD i965/fs: Simplify setup_color_payload Previously, setup_color_payload was a a big helper function that did a lot of gen-specific special casing for setting up the color sources of the LOAD_PAYLOAD instruction. Now that lower_load_payload is much more sane, most of that complexity isn't needed anymore. Instead, we can do a simple fixup pass for color clamps and then just stash sources directly in the LOAD_PAYLOAD. We can trust lower_load_payload to do the right thing with respect to COMPR4. Reviewed-by: Kenneth Graunke <[email protected]>
* i965/fs: Make LOAD_PAYLOAD take a header sizeJason Ekstrand2015-05-064-12/+20
| | | | Reviewed-by: Kenneth Graunke <[email protected]>
* i965/fs: Make emit_single_fb_write take an explicit exec_sizeJason Ekstrand2015-05-062-8/+10
| | | | Reviewed-by: Kenneth Graunke <[email protected]>
* i965/fs_inst: Add an is_copy_payload helperJason Ekstrand2015-05-064-35/+25
| | | | | | | | | | This commit adds a new is_copy_payload helper to fs_inst that takes the place of the similarly named functions in cse and register coalesce. The two is_copy_payload functions in CSE and register coalesce were subtly different and potentially subtly broken. The new version unifies the two and should be more correct. Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Change header_present to header_size in backend_instructionJason Ekstrand2015-05-069-52/+56
| | | | Reviewed-by: Kenneth Graunke <[email protected]>
* i965/fs_cse: Factor out code to create copy instructionsJason Ekstrand2015-05-061-37/+38
| | | | | | | | v2: Get rid of the block parameter and make src a const reference Reviewed-by: Topi Pohjolainen <[email protected]> Reviewed-by: Matt Turner <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965/fs: Make half(fs_reg, unsigned) handle register files more explicitlyJason Ekstrand2015-05-061-5/+16
| | | | | | | | | Previously, we had a special case for uniforms and immediates and then a bunch of asserts for various other pessimal things. This commit changes it so that it explicitly does something on each register file. Some of them are disallowed and others are treated properly. Reviewed-by: Kenneth Graunke <[email protected]>
* i965/fs: Fix passing an immediate to half().Francisco Jerez2015-05-061-2/+2
| | | | | | | Immediates are generally uniform, they yield the same value to both halves of any instruction. Reviewed-by: Matt Turner <[email protected]>
* swrast: Build fix for darwinJeremy Huddleston Sequoia2015-05-061-0/+16
| | | | | | | | | | | Fixes regression from commit 64b1dc44495890cbc2c7c5509cb830264020998c Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=90147 Signed-off-by: Jeremy Huddleston Sequoia <[email protected]> Reviewed-by: Brian Paul <[email protected]> CC: Emil Velikov <[email protected]> CC: [email protected] CC: [email protected]
* main/queryobj: add GL_QUERY_TARGET support to GetQueryObjectiv()Martin Peres2015-05-061-0/+12
| | | | | | | | This was missing from my patchset to support the query-related entry points of Direct State Access. Reported-by: Ilia Mirkin <[email protected]> Signed-off-by: Martin Peres <[email protected]>
* mesa: support compute stage in _mesa_program_resource_propTapani Pälli2015-05-061-6/+16
| | | | | | | | | | Increases pass rate of ES31-CTS.*program_interface_query* tests when run with MESA_EXTENSION_OVERRIDE='GL_ARB_compute_shader'. Many of the negative tests that happen to use compute stage in queries start passing. Signed-off-by: Tapani Pälli <[email protected]> Reviewed-by: Martin Peres <[email protected]>
* i965/gen6: Enable ARB_viewport_array and AMD_vertex_shader_viewport_indexChris Forbes2015-05-061-8/+8
| | | | | Signed-off-by: Chris Forbes <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965/gen6: Upload all the SF viewportsChris Forbes2015-05-062-12/+19
| | | | | Signed-off-by: Chris Forbes <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965/gen6: Upload all the clip viewportsChris Forbes2015-05-061-19/+21
| | | | | Signed-off-by: Chris Forbes <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965/gen6: setup limits for ARB_viewport_arrayChris Forbes2015-05-062-3/+3
| | | | | Signed-off-by: Chris Forbes <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* st/mesa: fix pipe_query_result result initializerBrian Paul2015-05-051-1/+1
| | | | | | Fixes MSVC build error. Reviewed-by: Ilia Mirkin <[email protected]>
* st/mesa: fix st_NewPerfMonitor() declarationBrian Paul2015-05-051-1/+1
| | | | | | Was missing the context parameter. Fixes MSVC warning. Reviewed-by: Ilia Mirkin <[email protected]>
* st/mesa: also try PIPE_FORMAT_R10G10B10A2_UNORM for GL_RGB10Brian Paul2015-05-051-1/+1
| | | | Reviewed-by: Ilia Mirkin <[email protected]>
* st/mesa: implement GL_AMD_performance_monitorChristoph Bumiller2015-05-064-0/+500
| | | | | | | | | | | | | | | | | | | | This is based on the original patch of Christoph Bumiller. v2 (Samuel Pitoiset): - improve Gallium interface for this extension - rewrite some parts of the original code - fix compilation errors and piglit tests v3: - only enable this extension when the underlying driver expose GPU counters - get rid of the ring buffer of queries v4: - add a debug message when the maximum number of counters has been reached Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Martin Peres <[email protected]>
* mesa: fix shininess check for ffvertex_prog v2Tim Rowley2015-05-051-1/+1
| | | | | | | | Switch to using VERT_BIT_GENERIC macro, as varying_vp_inputs is a bitmask. Reviewed-by: Ilia Mirkin <[email protected]> Cc: [email protected]
* i965/aa: fixing anti-aliasing bug for thinnest width lines - GEN7Marius Predut2015-05-051-3/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | On SNB and IVB hw, for 1 pixel line thickness or less, the general anti-aliasing algorithm give up - garbage line is generated. Setting a Line Width of 0.0 specifies the rasterization of the “thinnest” (one-pixel-wide), non-antialiased lines. Lines rendered with zero Line Width are rasterized using Grid Intersection Quantization rules as specified by bspec section 6.3.12.1 Zero-Width (Cosmetic) Line Rasterization. v2: Daniel Stone: Fix = used instead of == in an if-statement. v3: Ian Romanick: Use "._Enabled" flag insteed ".Enabled". Add code comments. re-word wrap the commit message. Add a complete bugzillia list. Improve the hardcoded values to produce better results. v4: Matt Turner: typo fixes and adjust <= 1.49 to become < 1.5 Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=28832 Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=9951 Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=27007 Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=60797 Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=15006 Acked-by: Chris Forbes <[email protected]> Acked-by: Kenneth Graunke <[email protected]> Signed-off-by: Marius Predut <[email protected]>
* i965: Fix missing type in local variable declaration.Kenneth Graunke2015-05-051-1/+1
| | | | | | | | | Trivial. Fixes the following compiler warning (from GCC 5.1.0): brw_context.c:629:10: warning: type defaults to ‘int’ in declaration of ‘simd_size’ [-Wimplicit-int] Signed-off-by: Kenneth Graunke <[email protected]>
* i965/vec4: Use same type for immediate, for compaction.Matt Turner2015-05-051-1/+1
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* i965/aa: fixing anti-aliasing bug for thinnest width lines - GEN6Marius Predut2015-05-051-3/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | On SNB and IVB hw, for 1 pixel line thickness or less, the general anti-aliasing algorithm give up - garbage line is generated. Setting a Line Width of 0.0 specifies the rasterization of the “thinnest” (one-pixel-wide), non-antialiased lines. Lines rendered with zero Line Width are rasterized using Grid Intersection Quantization rules as specified by bspec section 6.3.12.1 Zero-Width (Cosmetic) Line Rasterization. v2: Daniel Stone: Fix = used instead of == in an if-statement. v3: Ian Romanick: Use "._Enabled" flag insteed ".Enabled". Add code comments. re-word wrap the commit message. Add a complete bugzillia list. Improve the hardcoded values to produce better results. v4: Matt Turner: typo fixes and adjust <= 1.49 to become < 1.5 Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=28832 Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=9951 Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=27007 Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=60797 Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=15006 Acked-by: Chris Forbes <[email protected]> Acked-by: Kenneth Graunke <[email protected]> Signed-off-by: Marius Predut <[email protected]>
* i965: Remove end-of-thread SEND alignment code.Matt Turner2015-05-051-12/+3
| | | | | | | This was present in Eric's initial implementation of the compaction code for Sandybridge (commit 077d01b6). There is no documentation saying this is necessary, and removing it causes no regressions in piglit on any platform.
* i965: Add XRGB8888 format to intel_screen_make_configsBoyan Ding2015-05-051-1/+2
| | | | | | | | | | | | | | Some application, such as drm backend of weston, uses XRGB8888 config as default. i965 doesn't provide this format, but before commit 65c8965d, the drm platform of EGL takes ARGB8888 as XRGB8888. Now that commit 65c8965d makes EGL recognize format correctly so weston won't start because it can't find XRGB8888. Add XRGB8888 format to i965 just as other drivers do. Cc: [email protected] Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=89689 Signed-off-by: Boyan Ding <[email protected]> Reviewed-by: Kristian Høgsberg <[email protected]>
* i965/skl: Align compressed textures to four times the block sizeNeil Roberts2015-05-051-4/+27
| | | | | | | | | | | | On Skylake it is possible to choose your own alignment values for compressed textures but they are expressed as a multiple of the block size. The minimum alignment value we can use is 4 so we effectively have to align to 4 times the block size. This patch makes it initially set mt->align_[wh] to the large alignment value and then later divides it by the block size so that it can be uploaded as part of the surface state. Reviewed-by: Ben Widawsky <[email protected]>
* mesa/es3.1: Add _mesa_is_gles31 helperIan Romanick2015-05-041-1/+11
| | | | | Signed-off-by: Ian Romanick <[email protected]> Reviewed-by: Tapani Pälli <[email protected]>
* mesa: Use bool in _mesa_is_ helpers instead of GLbooleanIan Romanick2015-05-041-4/+4
| | | | | | | Signed-off-by: Ian Romanick <[email protected]> Reviewed-by: Anuj Phogat <[email protected]> Reviewed-by: Dylan Baker <[email protected]> Reviewed-by: Tapani Pälli <[email protected]>
* mesa: Trivial coding standards cleanupsIan Romanick2015-05-041-15/+10
| | | | | | | Signed-off-by: Ian Romanick <[email protected]> Reviewed-by: Anuj Phogat <[email protected]> Reviewed-by: Dylan Baker <[email protected]> Reviewed-by: Tapani Pälli <[email protected]>
* mesa: Use bool instead of GLbooleanIan Romanick2015-05-041-158/+157
| | | | | | | | | | v2: Squash in whitespace fixes. Signed-off-by: Ian Romanick <[email protected]> Reviewed-by: Anuj Phogat <[email protected]> Reviewed-by: Dylan Baker <[email protected]> Reviewed-by: Tapani Pälli <[email protected]> Reviewed-by: Topi Pohjolainen <[email protected]>
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