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* mesa: use _mesa_reference_buffer_object() in a few placesBrian Paul2009-06-123-4/+10
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* r300: add support for EXT_texture_sRGBMaciej Cencora2009-06-124-0/+27
| | | | Tested with glean/texture_srgb and wine/d3d9 tests on RV535
* set/mesa: enable GL_NV_texture_env_combine4Brian Paul2009-06-121-0/+1
| | | | | This is handled entirely in core Mesa where the combiner state is converted into a fragment program.
* st/mesa: additional debug code (disabled)Brian Paul2009-06-121-0/+20
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* Merge branch 'mesa_7_5_branch'Jakob Bornecrantz2009-06-125-24/+88
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| * mesa: Enable uploads of only depth to z24s8 texturesJakob Bornecrantz2009-06-121-3/+36
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| * mesa: rework vertex shader output / fragment shader input attribute matchingBrian Paul2009-06-111-20/+33
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Before, if a vertex shader's outputs didn't exactly match a fragment shader's inputs we could wind up with invalid TGSI shader declarations. For example: Before patch: DCL OUT[0], POSITION DCL OUT[1], COLOR[1] DCL OUT[2], GENERIC[0] DCL OUT[3], GENERIC[0] <- note duplicate [0] DCL OUT[4], GENERIC[2] After patch: DCL OUT[0], POSITION DCL OUT[1], COLOR[1] DCL OUT[2], GENERIC[0] DCL OUT[3], GENERIC[1] DCL OUT[4], GENERIC[2]
| * mesa: add default function for ctx->Driver.CheckQuery() hookBrian Paul2009-06-113-1/+19
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* | radeon: fix size of mipmap texture arrayDave Airlie2009-06-121-1/+3
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* | radeon/r200/r300: fix max texture levels assertDave Airlie2009-06-122-6/+3
| | | | | | | | use the actual value set in the context
* | Merge remote branch 'main/radeon-rewrite'Dave Airlie2009-06-12118-18854/+16421
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| * | r300: fix VAP setupMaciej Cencora2009-06-111-5/+6
| | | | | | | | | | | | If GL context had e.g. tex0, tex2 and fog the VAPOutputCntl1 returned 0x104 instead of 0x124 - that meaned we're sending only 8 texcoords (instead of 12) which ended up in GPU hang.
| * | r300: fix for SW TCL pathMaciej Cencora2009-06-111-1/+1
| | | | | | | | | | | | | | | We shouldn't use i variable for SWTCL_OVM_TEX because textures doesn't have to be enabled in "packed" order. We could have tex1,tex3 and fog which would receive 7,9,8 OVM locations instead of 6,7,8.
| * | r300: don't send unused attributes for SW TCL pathMaciej Cencora2009-06-111-14/+14
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| * | r300: send only RS_IP_* regs that we are going to useMaciej Cencora2009-06-112-10/+4
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| * | r300: fix RS setup when no colors and textures are sent to FPMaciej Cencora2009-06-111-4/+6
| | | | | | | | | | | | RS_COL_FMT field is part of RS_IP_* reg not RS_INST_*
| * | r300: r500 fragment program fixesMaciej Cencora2009-06-111-12/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | - when rewriting per component negate swizzle, first instruction should get not negated source - KIL instruction ignores swizzles TODO: - tex instructions does not support saturation - tex instructions cannot read from consant memory
| * | radeon: increase max bo countMaciej Cencora2009-06-111-1/+1
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| * | r300: fix a GPU lock upMaciej Cencora2009-06-113-21/+24
| | | | | | | | | | | | | | | | | | Sending from VAP more texture coordinates than RS expects results in GPU hang. Fixes BumpSelfShadow from DirectX8 SDK.
| * | r300: fix vertex program bugMaciej Cencora2009-06-111-6/+10
| | | | | | | | | | | | | | | | | | If the vertex program didn't write position attribute, the position invariant function would add necessary instructions, but the vertex position would be overwritten by artificial outputs insts added to satisfy fragment program requirements. Fixes "whole screen is gray" problem for HW TCL path in sauerbraten when shaders are enabled, and whole slew of wine d3d9 tests.
| * | r300: move some code for easier debuggingMaciej Cencora2009-06-111-17/+37
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| * | r300: print vertex program when debugging is enabledMaciej Cencora2009-06-111-3/+14
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| * | r300: fix output register allocation for vertex shadersMaciej Cencora2009-06-111-9/+19
| | | | | | | | | | | | If the vertex program wrote secondary color without primary color, the secondary color output register index would be 0 which resulted in overwriting vertex position in some cases.
| * | r300: hw doesn't support saturation for tex instructionsMaciej Cencora2009-06-111-0/+3
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| * | r300: fix indexed primitive rendering when using memory managerJerome Glisse2009-06-111-2/+2
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| * | r300: make sure indexed rendering doesn't try to use more than the num of ↵Jerome Glisse2009-06-101-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | vertices When with memory manager we need to make sure the GPU won't try to access beyond vertex buffer size, do so by enforcing that the maximun index is the last vertex of the buffer.
| * | radeon: fix mipmap_limits crasher.Dave Airlie2009-06-091-1/+1
| | | | | | | | | | | | This gets the correct srclvl image map when uploading images to the new mipmap.
| * | r300: fix regression caused by 056bc77547c304021a0faf204897ed238a5cf424Maciej Cencora2009-06-081-0/+1
| | | | | | | | | | | | Fixes GPU hangs in software TCL path
| * | Merge remote branch 'origin/master' into radeon-rewriteDave Airlie2009-06-07104-5624/+6821
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| * | | r300: Endianness fixes for recent vertex path changes.Michel Dänzer2009-06-072-9/+37
| | | | | | | | | | | | | | | | Signed-off-by: Maciej Cencora <[email protected]>
| * | | r300: vertex array stride = 0 means that data are tightly packed in the arrayMaciej Cencora2009-06-071-5/+8
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| * | | r300: GL_(U)SHORT and GL_(U)BYTE with < 4 components can also be HW acceleratedMaciej Cencora2009-06-071-20/+29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Also when index format is GL_UBYTE, convert it to GL_USHORT not GL_UINT. Fix license header too. Reported by: Nicolai Hähnle <[email protected]>
| * | | r300: remove unused codeMaciej Cencora2009-06-074-55/+1
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| * | | r300: rewrite vertex setup for software T&L path using functions from ↵Maciej Cencora2009-06-074-209/+54
| | | | | | | | | | | | | | | | software TCL path
| * | | r300: prepare for some code duplication removalMaciej Cencora2009-06-072-5/+15
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| * | | r300: enable EXT_vertex_array_bgra extensionsMaciej Cencora2009-06-071-0/+1
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| * | | r300: add hw accelerated support for different vertex data formatsMaciej Cencora2009-06-077-57/+485
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| * | | r300: prepare for different vertex data type supportMaciej Cencora2009-06-076-120/+116
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| * | | r300: fixup vertex attributes orderingMaciej Cencora2009-06-071-17/+10
| | | | | | | | | | | | | | | | Always allocate the vertex program input registers in the same order as the vertex attributes are passed in vertex arrays.
| * | | r300: always pass 4 color components to RS unitMaciej Cencora2009-06-071-42/+6
| | | | | | | | | | | | | | | | Even if we don't pass all 4 color components to vertex shader unit, the vertex program can generate the missing components.
| * | | radeon: Provide a more detailled GL_RENDERER string.Nicolai Hähnle2009-06-013-5/+47
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Display the chip family and PCI ID. This can be parsed easily, and essentially all information that the driver has about the chip can be deduced from it. Signed-off-by: Nicolai Hähnle <[email protected]>
| * | | r300: when using cs path emit scissor in the cmdbufferJerome Glisse2009-05-284-0/+43
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| * | | r300: rework texture offset emission.Jerome Glisse2009-05-281-7/+13
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| * | | radeon: emit scissor before emiting verticesJerome Glisse2009-05-271-3/+1
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| * | | radeon: emit scissor when using cs submission style.Jerome Glisse2009-05-271-0/+28
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| * | | radeon: on update drawable don't firevertices as it might be call from GetLockJerome Glisse2009-05-251-3/+1
| | | | | | | | | | | | | | | | | | | | To avoid locking bug we shouldn't not call firevertices from this path as it's call from radeon get lock.
| * | | r200: emit scissor when dri2 is enabledJerome Glisse2009-05-251-0/+31
| | | | | | | | | | | | | | | | | | | | In DRI1 kernel emit scissor but in dri2 cs path we have to explicitly program them.
| * | | r200: fix multitexturing in dri2 pathJerome Glisse2009-05-251-1/+1
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| * | | r200: emit cliprect with indexed primitiveJerome Glisse2009-05-251-1/+1
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| * | | radeon: realloc dma if needed after revalidateJerome Glisse2009-05-241-0/+6
| | | | | | | | | | | | | | | | | | | | Revalidate can trigger flushing and dma buffer deallocation, so retry allocation on such case.
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