summaryrefslogtreecommitdiffstats
path: root/src/mesa
Commit message (Collapse)AuthorAgeFilesLines
* meta: add offset, width, height parameters to decompress_texture_image()Brian Paul2015-07-211-5/+5
| | | | | | In preparation for decompressing texture sub images. Reviewed-by: Ilia Mirkin <[email protected]>
* meta: handle subimages in _mesa_meta_setup_texture_coords()Brian Paul2015-07-213-33/+65
| | | | | | v2: fix depth, total_depth mix-up in meta.h, per Laura Ekstrand. Reviewed-by: Anuj Phogat <[email protected]>
* mesa: assorted whitespace, formatting fixes in teximage.cBrian Paul2015-07-211-20/+10
| | | | Trivial.
* mesa: allow GL_TEXTURE_CUBE_MAP_ARRAY case for glCompressedTexSubImage3D()Brian Paul2015-07-211-1/+1
| | | | | | | | | | | Since s3tc works for cube maps and 2D arrays, it should also work for cube arrays. NVIDIA's driver supports this too. Seems like the spec should say this. This is a minor follow-on fix for the commit "mesa: fix up some texture error checks". Reviewed-by: Roland Scheidegger <[email protected]>
* mesa: include stdarg.h for va_listJonathan Gray2015-07-211-0/+1
| | | | | | | | | | | Include stdarg.h for va_list. Unbreaks the build on OpenBSD: In file included from mesa/program/dummy_errors.c:24: ../src/mesa/main/errors.h:85: error: expected declaration specifiers or '...' before 'va_list' Signed-off-by: Jonathan Gray <[email protected]> Acked-by: Matt Turner <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* gallium: replace INLINE with inlineIlia Mirkin2015-07-211-1/+1
| | | | | | | | | | | | | | | | Generated by running: git grep -l INLINE src/gallium/ | xargs sed -i 's/\bINLINE\b/inline/g' git grep -l INLINE src/mesa/state_tracker/ | xargs sed -i 's/\bINLINE\b/inline/g' git checkout src/gallium/state_trackers/clover/Doxyfile and manual edits to src/gallium/include/pipe/p_compiler.h src/gallium/README.portability to remove mentions of the inline define. Signed-off-by: Ilia Mirkin <[email protected]> Acked-by: Marek Olšák <[email protected]>
* st/mesa: Silence GCC unused-variable warning.Vinson Lee2015-07-211-0/+1
| | | | | | | | | | | | Silence a release build warning. st_glsl_to_tgsi.cpp: In function 'pipe_error st_translate_program(gl_context*, uint, ureg_program*, glsl_to_tgsi_visitor*, const gl_program*, GLuint, const GLuint*, const GLuint*, const ubyte*, const ubyte*, const GLuint*, const GLuint*, GLuint, const GLuint*, const GLuint*, const ubyte*, const ubyte*, boolean, boolean)': st_glsl_to_tgsi.cpp:5461:36: warning: unused variable 'pscreen' [-Wunused-variable] struct pipe_screen *pscreen = st->pipe->screen; ^ Signed-off-by: Vinson Lee <[email protected]> Reviewed-by: Brian Paul <[email protected]>
* Revert "i965/gen9: Plugin the code for selecting YF/YS tiling on skl+"Anuj Phogat2015-07-211-92/+17
| | | | | | | | | | | | | | Commit c9dbdc0 introduced some dead code which is supposed to be used once we have Yf/Ys tiling working and performing better. Ken reported the issue that static analysis tool now shows warnings due to the dead code. To fix these warnings, this patch reverts the changes made in commit c9dbdc0. It'll be better to add the Yf/Ys tiling selection code later, when we are ready to use it. Signed-off-by: Anuj Phogat <[email protected]> Acked-by: Kenneth Graunke <[email protected]>
* i965: Fix stride field for the result of emit_uniformize().Francisco Jerez2015-07-214-19/+26
| | | | | | | | | | | | | | | | | | | This is essentially the same problem fixed in an earlier patch for immediates. Setting the stride to zero will be particularly useful for my future SIMD lowering pass, because we will be able to just check whether the stride of a source register is zero and skip emitting the copies required to unzip it in that case. Instead of setting stride to zero in every caller of emit_uniformize() I've changed the function to return the result as its return value (previously it was being written into a caller-provided destination register), because this way we can enforce that the result is used with the correct regioning from the function itself. The changes to the prototype of its VEC4 counterpart are mainly for the sake of symmetry, VEC4 registers don't have stride. Reviewed-by: Samuel Iglesias Gonsálvez <[email protected]>
* i965/fs: Fix stride field for uniforms.Francisco Jerez2015-07-211-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This fixes essentially the same problem as for immediates. Registers of the UNIFORM file are typically accessed according to the formula: read_uniform(r, channel_index, array_index) = read_element(r, channel_index * 0 + array_index * 1) Which matches the general direct addressing formula for stride=0: read_direct(r, channel_index, array_index) = read_element(r, channel_index * stride + array_index * max{1, stride * width}) In either case if reladdr is present the access will be according to the composition of two register regions, the first one determining the per-channel array_index used for the second, like: read_indirect(r, channel_index, array_index) = read_direct(r, channel_index, read(r.reladdr, channel_index, array_index)) where: read(r, channel_index, array_index) = if r.reladdr == NULL then read_direct(r, channel_index, array_index) else read_indirect(r, channel_index, array_index) In conclusion we can handle uniforms consistently with the other register files if we set stride to zero. After lowering to a GRF using VARYING_PULL_CONSTANT_LOAD in demote_pull_constant_loads() the stride of the source is set to one again because the result of VARYING_PULL_CONSTANT_LOAD is generally non-uniform. Reviewed-by: Samuel Iglesias Gonsálvez <[email protected]>
* i965/fs: Fix stride for immediate registers.Francisco Jerez2015-07-212-0/+7
| | | | | | | | | | | | | | | | | | | When the width field was removed from fs_reg the BROADCAST handling code in opt_algebraic() started to miss a number of trivial optimization cases resulting in the ugly indirect-addressing sequence to be emitted unnecessarily for some variable-indexed texturing and UBO loads regardless of one of the sources of BROADCAST being immediate. Apparently the reason was that we were setting the stride field to one for immediates even though they are typically uniform. Width used to be set to one too which is why this optimization used to work previously until the "reg.width == 1" check was removed. The stride field of vector immediates is intentionally left equal to one, because they are strictly speaking not uniform. The assertion in fs_generator makes sure that immediates have the expected stride as consistency check. Reviewed-by: Samuel Iglesias Gonsálvez <[email protected]>
* i965/vec4: Fix liveness analysis with BRW_OPCODE_SELIago Toral Quiroga2015-07-211-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | We only consider a vgrf defined by a given block if the block writes to it unconditionally. So far we have been checking this by testing that the instruction is not predicated, however, in the case of BRW_OPCODE_SEL, the predication is used to select the value to write, not to decide if the write is actually done. The consequence of this was increased life spans for affected vgrfs, which could lead to additional register pressure. Since NIR generates selects for conditional writes this was causing massive register pressure in a handful of piglit and dEQP tests that had a large number of select operations with the NIR-vec4 backend. Fixes the following piglit tests with the NIR-vec4 backend: spec/glsl-1.50/execution/variable-indexing/vs-output-array-vec4-index-wr-before-gs spec/glsl-1.50/execution/variable-indexing/gs-input-array-vec4-index-rd spec/glsl-1.50/execution/variable-indexing/vs-output-array-vec2-index-wr-before-gs spec/glsl-1.50/execution/variable-indexing/vs-output-array-vec3-index-wr-before-gs spec/glsl-1.50/execution/variable-indexing/vs-output-array-float-index-wr-before-gs Fixes 80 dEQP tests with the NIR-vec4 backend in the following category: dEQP-GLES3.functional.ubo.* Reviewed-by: Francisco Jerez <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* mesa: Rename _mesa_lookup_enum_by_nr() to _mesa_enum_to_string().Kenneth Graunke2015-07-2085-422/+422
| | | | | | | Generated by sed; no manual changes. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Brian Paul <[email protected]>
* i965/nir/fs: removed unneeded support for global variablesAlejandro Piñeiro2015-07-203-14/+4
| | | | | | | As functions are inlined, and nir_lower_global_vars_to_local gets run, all global variables are lowered to local variables. Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Disable resource streamer in BLORPAbdiel Janulgue2015-07-181-0/+2
| | | | | | | | | | | Switch off hardware-generated binding tables and gather push constants in the blorp. Blorp requires only a minimal set of simple constants. There is no need for the extra complexity to program a gather table entry into the pipeline. Cc: [email protected] Reviewed-by: Kenneth Graunke <[email protected]> Signed-off-by: Abdiel Janulgue <[email protected]>
* i965: Upload binding tables in hw-generated binding table format.Abdiel Janulgue2015-07-181-9/+57
| | | | | | | | | | | | | | | | | | | | | | | | When hardware-generated binding tables are enabled, use the hw-generated binding table format when uploading binding table state. Normally, the CS will will just consume the binding table pointer commands as pipelined state. When the RS is enabled however, the RS flushes whatever edited surface state entries of our on-chip binding table to the binding table pool before passing the command on to the CS. Note that the the binding table pointer offset is relative to the binding table pool base address when resource streamer instead of the surface state base address. v2: Fix possible buffer overflow when allocating a chunk out of the hw-binding table pool (Ken). v3: Remove extra newline and add missing brace around if-statement (Matt). v4: Fix broken INTEL_DEBUG=shader_time for hw-generated binding tables. Document PRM WaStateBindingTableOverfetch workaround. Cc: [email protected] Cc: [email protected] Reviewed-by: Kenneth Graunke <[email protected]> Signed-off-by: Abdiel Janulgue <[email protected]>
* i965: Implement interface to edit binding table entriesAbdiel Janulgue2015-07-182-0/+64
| | | | | | | | | | | | | | | | Unlike normal software binding tables where the driver has to manually generate and fill a binding table array which are then uploaded to the hardware, the resource streamer instead presents the driver with an option to fill out slots for individual binding table indices. The hardware accumulates the state for these combined edits which it then automatically flushes to a binding table pool when the binding table pointer state command is invoked. v2: Clarify binding table edit bit aligment (Topi). v3: Make comments and function names more clearer (Ken). Reviewed-by: Kenneth Graunke <[email protected]> Signed-off-by: Abdiel Janulgue <[email protected]>
* i965: Enable hardware-generated binding tables on render path.Abdiel Janulgue2015-07-188-4/+128
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch implements the binding table enable command which is also used to allocate a binding table pool where where hardware-generated binding table entries are flushed into. Each binding table offset in the binding table pool is unique per each shader stage that are enabled within a batch. Also insert the required brw_tracked_state objects to enable hw-generated binding tables in normal render path. v2: - Use MOCS in binding table pool alloc for GEN8 - Fix spurious offset when allocating binding table pool entry and start from zero instead. v3: - Include GEN8 fix for spurious offset above. v4: - Fixup wrong packet length in enable/disable hw-binding table for GEN8 (Ville). - Don't invoke HW-binding table disable command when we dont have resource streamer (Chris). v5: - Reorder the state cache invalidate flush so it happens in-between enabling hw-generated binding tables and the previous sw-binding table GPU state (Chris). v6: - Do the same fix in v5 for gen7_disable_hw_binding_tables(). - Adhere to coding guidelines and make comments more informative. Cc: [email protected] Cc: [email protected] Cc: [email protected] Reviewed-by: Kenneth Graunke <[email protected]> Signed-off-by: Abdiel Janulgue <[email protected]>
* i965: Enable resource streamer for the batchbufferAbdiel Janulgue2015-07-187-2/+36
| | | | | | | | | | | | | | | | | | | | | Check first if the hardware and kernel supports resource streamer. If this is allowed, tell the kernel to enable the resource streamer enable bit on MI_BATCHBUFFER_START by specifying I915_EXEC_RESOURCE_STREAMER execbuffer flags. v2: - Use new I915_PARAM_HAS_RESOURCE_STREAMER ioctl to check if kernel supports RS (Ken). - Add brw_device_info::has_resource_streamer and toggle it for Haswell, Broadwell, Cherryview, Skylake, and Broxton (Ken). v3: - Update I915_PARAM_HAS_RESOURCE_STREAMER to match updated kernel. v4: - Always inspect the getparam.value (Chris Wilson). v5: - Fold redundant devinfo->has_resource_streamer check in context create into init screen. Cc: [email protected] Cc: [email protected] Reviewed-by: Kenneth Graunke <[email protected]> Signed-off-by: Abdiel Janulgue <[email protected]>
* i965: Define HW-binding table and resource streamer control opcodesAbdiel Janulgue2015-07-182-0/+33
| | | | | | | | | | | v2: Use macros for HW binding table edits (Topi) v3: Add Broadwell support. v4: Make hardware binding table bit definitions even more clearer (Ken) Cc: [email protected] Reviewed-by: Topi Pohjolainen <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Signed-off-by: Abdiel Janulgue <[email protected]>
* mesa: fix up some texture error checksRoland Scheidegger2015-07-182-21/+21
| | | | | | | | | | | In particular, we were incorrectly accepting s3tc (and lots of others) for CompressedTexSubImage3D (but not CompressedTexImage3D) calls with 3d targets. At this time, the only allowed formats for these calls are the bptc ones, since none of the specific extensions allow it (astc hdr would). Also, fix up a bug in _mesa_target_can_be_compressed - 3d target needs to be allowed for bptc formats. Reviewed-by: Brian Paul <[email protected]>
* i965/fs: don't make unused payload registers interfereConnor Abbott2015-07-171-1/+6
| | | | | | | | | | | | | | | | | Before, we were setting payload_last_use_ip for unused payload registers to 0, which made them interfere with whatever the first instruction wrote to due to the workaround for SIMD16 uniform arguments. Just use -1 to mean "unused" instead, and then skip setting any interferences for unused payload registers. instructions in affected programs: 0 -> 0 helped: 0 HURT: 0 GAINED: 1 LOST: 0 Reviewed-by: Jordan Justen <[email protected]> Signed-off-by: Connor Abbott <[email protected]>
* i965/fs: remove special case in setup_payload_interference()Connor Abbott2015-07-171-20/+0
| | | | | | | | | | | | | | | | | | regs_read() will handle LINTERP for us since the previous commit. In addition, we were being too conservative, since it will only read 2 registers on SIMD8. instructions in affected programs: 9061 -> 8893 (-1.85%) helped: 10 HURT: 0 GAINED: 0 LOST: 0 All of the changes were due to spills being eliminated, mostly in KSP shaders. Reviewed-by: Jordan Justen <[email protected]> Signed-off-by: Connor Abbott <[email protected]>
* i965/fs: Mark last used ip for all regs read in the payloadJordan Justen2015-07-171-1/+4
| | | | | | | | | | | | | | | | | | | If a source register in the push constant registers uses more than one register, then we wouldn't update payload_last_use_ip for subsequent registers. Unlike most uniform data pushed into registers, the CS gl_LocalInvocationID data varies per execution channel. Therefore for SIMD16 mode, we have vec16 data in the payload. In this case we then need to mark 2 registers in payload_last_use_ip as last used by the instruction. There's a similar situation for the z and w coordinates of gl_FragCoord for fragment shaders, where it had only happened to work before because of some bogus interferences which the next commit removes. (Connor: added bit about gl_FragCoord to commit message) Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Connor Abbott <[email protected]>
* i965/fs: fix regs_read() for LINTERPConnor Abbott2015-07-171-1/+2
| | | | | | | | The second source always stays within the same SIMD8 register. Reviewed-by: Jordan Justen <[email protected]> Reviewed-by: Matt Turner <[email protected]> Signed-off-by: Connor Abbott <[email protected]>
* i965/cs: Use dispatch width of 8 for cs terminate payload setupJordan Justen2015-07-161-1/+1
| | | | | | | | This prevents an assertion failure in brw_fs_live_variables.cpp, fs_live_variables::setup_one_write: Assertion `var < num_vars' failed. Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* i965/cs: Return 1 for regs_read on CS_OPCODE_CS_TERMINATEJordan Justen2015-07-161-0/+3
| | | | | | | | This prevents an assertion failure in brw_fs_live_variables.cpp, fs_live_variables::setup_one_read: Assertion `var < num_vars' failed. Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* program: Allow redundant OPTION ARB_fog_* directives.Kenneth Graunke2015-07-161-13/+37
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | A fragment program from "Pixel Piracy" contains redundant OPTION directives: !!ARBfp1.0 OPTION ARB_precision_hint_fastest; OPTION ARB_fog_exp2; OPTION ARB_precision_hint_fastest; OPTION ARB_fog_exp2; ... We already allow redundant ARB_precision_hint_fastest directives, but disallow the redundant (yet consistent) ARB_fog_exp2 directives, failing to compile the program. The specification seems to contradict itself - the main text says that only one fog application option may be specified, but then backpedals, indicating the intent is to disallow /contradictory/ flags. One of the issues suggests that specifying contradictory ones is stupid, but allowed, and only the last one should take effect. Accepting multiple redundant (but consistent) directives seems harmless, and like a reasonable interpretation of the specification. It also fixes a fragment program found in the wild. Cc: [email protected] Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* i965: Push miptree tiling request into flagsBen Widawsky2015-07-167-47/+51
| | | | | | | | | | | | | | | | | | | | | With the last few patches a way was provided to influence lower layer miptree layout and allocation decisions via flags (replacing bools). For simplicity, I chose not to touch the tiling requests because the change was slightly less mechanical than replacing the bools. The goal is to organize the code so we can continue to add new parameters and tiling types while minimizing risk to the existing code, and not having to constantly add new function parameters. v2: Rebased on Anuj's recent Yf/Ys changes Fix non-msrt MCS allocation (was only happening in gen8 case before) v3: small fix in assertion requested by Chad v4: Use parens to get the order right from v3. Signed-off-by: Ben Widawsky <[email protected]> Reviewed-by: Jordan Justen <[email protected]>
* Revert "i965: Push miptree tiling request into flags"Ben Widawsky2015-07-167-51/+47
| | | | This reverts commit 51e8d549e110f86cb7107cf712843aebd956fb9a.
* i965: Push miptree tiling request into flagsBen Widawsky2015-07-167-47/+51
| | | | | | | | | | | | | | | | | | | | | With the last few patches a way was provided to influence lower layer miptree layout and allocation decisions via flags (replacing bools). For simplicity, I chose not to touch the tiling requests because the change was slightly less mechanical than replacing the bools. The goal is to organize the code so we can continue to add new parameters and tiling types while minimizing risk to the existing code, and not having to constantly add new function parameters. v2: Rebased on Anuj's recent Yf/Ys changes Fix non-msrt MCS allocation (was only happening in gen8 case before) v3: small fix in assertion requested by Chad Signed-off-by: Ben Widawsky <[email protected]> Reviewed-by: Jordan Justen <[email protected]> (v2) Reviewed-by: Anuj Phogat <[email protected]> (v2) Reviewed-by: Chad Versace <[email protected]> (v2)
* i965/fs: Factor out universally broken calculation of the register component ↵Francisco Jerez2015-07-164-12/+23
| | | | | | | | | | | | | | size. This in principle simple calculation was being open-coded in a number of places (in a series I haven't yet sent for review there will be a couple more), all of them were subtly broken in one way or another: None of them were handling the HW_REG case correctly as pointed out by Connor, and fs_inst::regs_read() was handling the stride=0 case rather naively. This patch solves both problems and factors out the calculation as a new fs_reg method. Reviewed-by: Jason Ekstrand <[email protected]>
* i965: Implement nir_op_uadd_carry and _usub_borrow without accumulator.Francisco Jerez2015-07-163-35/+12
| | | | | | | | | | | | | | | | | | This gets rid of two no16() fall-backs and should allow better scheduling of the generated IR. There are no uses of usubBorrow() or uaddCarry() in shader-db so no changes are expected. However the "arb_gpu_shader5/execution/built-in-functions/fs-usubBorrow" and "arb_gpu_shader5/execution/built-in-functions/fs-uaddCarry" piglit tests go from 40 to 28 instructions. The reason is that the plain ADD instruction can easily be CSE'ed with the original addition, and the b2i negation can easily be propagated into the source modifier of another instruction, so effectively both operations are performed with just one instruction. v2: Rely on carry_to_arith() and borrow_to_arith() to lower these (Ilia Mirkin). Reviewed-by: Matt Turner <[email protected]>
* i965: Implement b2f and b2i using negation.Francisco Jerez2015-07-162-9/+2
| | | | | | | | | | | | | | | | | Booleans are represented as 0/-1 on modern hardware which means we can just negate them to convert them into a numeric type. Negation has the benefit that it can be implemented using a source modifier which can easily be propagated into some other instruction. shader-db results on HSW: total instructions in shared programs: 6349082 -> 6346693 (-0.04%) instructions in affected programs: 40948 -> 38559 (-5.83%) helped: 123 HURT: 1 GAINED: 1 LOST: 0 Reviewed-by: Matt Turner <[email protected]>
* i965/gen9: Use custom MOCS entries set up by the kernel.Francisco Jerez2015-07-162-7/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | Instead of relying on hardware defaults the i915 kernel driver is going program custom MOCS tables system-wide on Gen9 hardware. The "WT" entry previously used for renderbuffers had a number of problems: It disabled caching on eLLC, it used a reserved L3 cacheability setting, and it used to override the PTE controls making renderbuffers always WT on LLC regardless of the kernel's setting. Instead use an entry from the new MOCS tables with parameters: TC=LLC/eLLC, LeCC=PTE, L3CC=WB. The "WB" entry previously used for anything other than renderbuffers has moved to a different index in the new MOCS tables but it should have the same caching semantics as the old entry. Even though the corresponding kernel change ("drm/i915: Added Programming of the MOCS") is in a way an ABI break it doesn't seem necessary to check that the kernel is recent enough because the change should only affect Gen9 which is still unreleased hardware. v2: Update MOCS values for the new Android-incompatible tables introduced in v7 of the kernel patch. Cc: 10.6 <[email protected]> Reference: http://lists.freedesktop.org/archives/intel-gfx/2015-July/071080.html Reviewed-by: Ben Widawsky <[email protected]>
* r200: fix some potential big endian issuesRoland Scheidegger2015-07-165-129/+140
| | | | | | | | | | | | The formats chosen (both by texture format choser, fbo storage allocation) are different for big endian not just for rgba8 but also lower bit width formats (why I don't actually know). Even the function to test for renderable formats used different formats, however the actual colorbuffer setup did not. And the blitter did not take that into account neither. Untested (what could possibly go wrong...). Same as for r100. Acked-by: Marek Olšák <[email protected]>
* radeon: fix some potential big endian issuesRoland Scheidegger2015-07-164-90/+76
| | | | | | | | | | | The formats chosen (both by texture format choser, fbo storage allocation) are different for big endian not just for rgba8 but also lower bit width formats (why I don't actually know). Even the function to test for renderable formats used different formats, however the actual colorbuffer setup did not. And the blitter did not take that into account neither. Untested (what could possibly go wrong...). Acked-by: Marek Olšák <[email protected]>
* radeon/r200: mark state atoms as dirty after blitsRoland Scheidegger2015-07-162-0/+24
| | | | | | | | | | | Blit submits lots of packets which are usually handled by state atoms, so these must be dirtied. Not sure if this fixes anything, but it was a concern raised by bug 51658 (with this all issues there seen as actual bugs should be fixed, with the exception of the patch to upload non-used texenv state atoms which I just don't understand). Acked-by: Marek Olšák <[email protected]>
* r200: fix fbo rendering by disabling optimized texture format chooserRoland Scheidegger2015-07-161-1/+13
| | | | | | | | | | | | It is rather unfortunate that we don't know if a texture is going to be used as a rt later, and we lack the means to do something about a format chosen which we can't render to directly, so disable this and always chose renderable format for rgba8 textures. This addresses an issue raised on (old) bug, https://bugs.freedesktop.org/show_bug.cgi?id=51658 with gnome-shell, don't know if that's still applicable but it might fix other things as well. Acked-by: Marek Olšák <[email protected]>
* i965: Fix 32 bit build warnings in intel_get_yf_ys_bo_size()Anuj Phogat2015-07-151-3/+3
| | | | | | | | | | | | | | | Along with fixing the type of pitch parameter, patch also changes the types of few local variables and function return type. Warnings fixed are: intel_mipmap_tree.c:671:7: warning: passing argument 3 of 'intel_get_yf_ys_bo_size' from incompatible pointer type intel_mipmap_tree.c:563:1: note: expected 'uint64_t *' but argument is of type 'long unsigned int *' Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Optimize batchbuffer macros.Matt Turner2015-07-156-42/+70
| | | | | | | | | | | | | | | | | | | | | | | | | | Previously OUT_BATCH was just a macro around an inline function which does brw->batch.map[brw->batch.used++] = dword; When making consecutive calls to intel_batchbuffer_emit_dword() the compiler isn't able to recognize that we're writing consecutive memory locations or that it doesn't need to write batch.used back to memory each time. We can avoid both of these problems by making a local pointer to the next location in the batch in BEGIN_BATCH(). Cuts 18k from the .text size. text data bss dec hex filename 4946956 195152 26192 5168300 4edcac i965_dri.so before 4928956 195152 26192 5150300 4e965c i965_dri.so after This series (including commit c0433948) improves performance of Synmark OglBatch7 by 8.01389% +/- 0.63922% (n=83) on Ivybridge. Reviewed-by: Chris Wilson <[email protected]>
* i965: Add and use USED_BATCH macro.Matt Turner2015-07-156-22/+25
| | | | | | | The next patch will replace the .used field with an on-demand calculation of batchbuffer usage. Reviewed-by: Chris Wilson <[email protected]>
* i965: Split batch emission from relocation functions.Matt Turner2015-07-152-34/+30
| | | | | | | So that everything writing to the batch between BEGIN_BATCH() and ADVANCE_BATCH() goes through OUT_BATCH. Reviewed-by: Chris Wilson <[email protected]>
* i965: Move BEGIN_BATCH() into same control flow as ADVANCE_BATCH().Matt Turner2015-07-151-2/+2
| | | | | | | | | | BEGIN_BATCH() and ADVANCE_BATCH() will contain "do {" and "} while (0)" respectively to allow declaring local variables used by intervening OUT_BATCH macros. As such, BEGIN_BATCH() and ADVANCE_BATCH() need to be in the same control flow. Reviewed-by: Iago Toral Quiroga <[email protected]> Reviewed-by: Chris Wilson <[email protected]>
* osmesa: fix OSMesaPixelsStore typoBrian Paul2015-07-151-1/+1
| | | | | | | Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=91337 Cc: 10.6 <[email protected]> Reviewed-by: Emil Velikov <[email protected]>
* i965/cs: Initialize GPGPU Thread CountJordan Justen2015-07-142-0/+25
| | | | | | | | | | | | | | | | This field should always be set for gen8. In the bdw PRM, Volume 2d: Command Reference: Structures under INTERFACE_DESCRIPTOR_DATA, DWORD 6, Bits 9:0, Number of Threads in GPGPU Thread Group: "This field should not be set to 0 even if the barrier is disabled, since an accurate value is needed for proper pre-emption." In the HSW PRM, the it doesn't mention that it must always be set, but it should not hurt. Reported-by: Kristian Høgsberg <[email protected]> Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Ben Widawsky <[email protected]>
* i965: Mark constant static data as const.Matt Turner2015-07-142-23/+23
| | | | Reviewed-by: Topi Pohjolainen <[email protected]>
* mesa: Implement _mesa_BindBufferRange for target GL_SHADER_STORAGE_BUFFERIago Toral Quiroga2015-07-141-0/+37
| | | | Reviewed-by: Jordan Justen <[email protected]>
* mesa: Implement _mesa_BindBufferBase for target GL_SHADER_STORAGE_BUFFERIago Toral Quiroga2015-07-141-0/+56
| | | | Reviewed-by: Jordan Justen <[email protected]>
* mesa: Implement _mesa_BindBuffersRange for target GL_SHADER_STORAGE_BUFFERIago Toral Quiroga2015-07-141-0/+110
| | | | | | | v2: - Fix error message (Jordan) Reviewed-by: Jordan Justen <[email protected]>
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-15 09:55:14 +0000