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* mesa: make _mesa_get_proxy_target() staticBrian Paul2014-02-022-8/+5
| | | | | | Wasn't used in any other file. Reviewed-by: Kenneth Graunke <[email protected]>
* mesa: remove unused _mesa_select_tex_object() functionBrian Paul2014-02-022-27/+6
| | | | | | | The _mesa_get_current_tex_object() function is now used everywhere that _mesa_select_tex_object() was formerly used. Reviewed-by: Kenneth Graunke <[email protected]>
* swrast: use _mesa_get_current_tex_object() in swrastSetTexBuffer2()Brian Paul2014-02-021-3/+1
| | | | Reviewed-by: Kenneth Graunke <[email protected]>
* st/mesa: use _mesa_get_current_tex_object() in st_context_teximage()Brian Paul2014-02-021-2/+2
| | | | Reviewed-by: Kenneth Graunke <[email protected]>
* mesa: use _mesa_get_current_tex_object() in GetTexLevelParameteriv()Brian Paul2014-02-021-6/+3
| | | | | | And update a related comment. Reviewed-by: Kenneth Graunke <[email protected]>
* radeon: use _mesa_get_current_tex_object() in radeonSetTexBuffer2()Brian Paul2014-02-021-4/+2
| | | | Reviewed-by: Kenneth Graunke <[email protected]>
* r200: use _mesa_get_current_tex_object() in r200SetTexBuffer2()Brian Paul2014-02-021-4/+2
| | | | Reviewed-by: Kenneth Graunke <[email protected]>
* build: move ARCH_LIBS definition outside of ASM definitionPaul Seidler2014-02-011-6/+6
| | | | | | | _mesa_streaming_load_memcpy is also needed even if assembling is disabled Cc: "10.0" <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* i965: Silence unused variable 'ctx' warning.Kenneth Graunke2014-01-311-1/+0
| | | | | | Somehow I missed this before pushing the Broadwell PS state upload code. Signed-off-by: Kenneth Graunke <[email protected]>
* i965: Fix math instruction hstride assertions on Broadwell.Kenneth Graunke2014-01-311-1/+1
| | | | | | | | | | | | | | In the final revision of my gen8_generator patch, I updated the MATH instruction's assertion from (dst.hstride == 1) to check that source and destination hstride matched. Unfortunately, I didn't test this enough, and many Piglit tests fail this test. The documentation indicates that "scalar source is also supported", which we believe means <0,1,0> access mode (hstride == 0). If hstride is non-zero, then it must match the destination register. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* i965: Disable 3DSTATE_WM_HZ_OP fields.Kenneth Graunke2014-01-312-0/+10
| | | | | | | | | | | | | Eric believes this to be wrong and unnecessary, as the command is supposed to emit an implicit rectangle primitive. However, empirically the pixel pipeline is completely unreliable without it. So for now, it stays until someone comes up with a better solution. We'll need to do better than this when we implement multisampling, HiZ, or fast clears...but for now, this will do. Signed-off-by: Kenneth Graunke <[email protected]> Acked-by: Eric Anholt <[email protected]>
* i965: Update GS state for Broadwell.Kenneth Graunke2014-01-315-1/+155
| | | | | | | | | | | | | | | This is quite similar to the Gen7 code. The main changes: - 48-bit relocations - Thread count is specified as U/2-1 instead of U-1. - An extra DWord (DW9) with clip planes, URB entry output length/offsets - We need to program the "Expected Vertex Count" (VerticesIn) v2: Set the number of binding table entries so they can be prefetched (requested by Eric Anholt). v3: Add a WARN_ONCE for a missing workaround. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* i965: Update multisampling state for Broadwell.Kenneth Graunke2014-01-317-1/+135
| | | | | | | | | | | | | | | | | | | | On previous platforms, 3DSTATE_MULTISAMPLE contained the number of samples, pixel location, and the positions of each sample within a pixel for each multisampling mode (4x and 8x). It was also a non-pipelined command, presumably since changing the sample positions is fairly drastic. Broadwell improves upon this by splitting the sample positions out into a separate non-pipelined state packet, 3DSTATE_SAMPLE_PATTERN. With that removed, 3DSTATE_MULTISAMPLE becomes a pipelined state packet. Broadwell also supports 2x and 16x multisampling, in addition to the 4x and 8x supported by Gen7. This patch, however, does not implement 2x and 16x. Signed-off-by: Kenneth Graunke <[email protected]> Signed-off-by: Chad Versace <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* i965: Update 3DSTATE_{DEPTH,STENCIL,...}_BUFFER and such for Broadwell.Kenneth Graunke2014-01-314-1/+180
| | | | | | | | | | | | | | | | | | The amount of cut and paste from Gen7 is rather ugly, and should probably be cleaned up in the future. Even the Gen7 code is in need of some tidying though; many of the function parameters aren't used on platforms that use level/layer rather than tile offsets. Tidying both can be left to a future patch series. This at least gets things going. v2: Rebase on Paul's rename of NumLayers -> MaxNumLayers. v3: Shift QPitch by 2 when storing it in the packet. Bits 14:0 store bits 16:2 of the actual value. Fixes tests. v4: Add missing stencil buffer QPitch. Signed-off-by: Kenneth Graunke <[email protected]> Acked-by: Eric Anholt <[email protected]>
* i965: Update BLEND_STATE for Broadwell.Kenneth Graunke2014-01-314-1/+216
| | | | | | | | | | | v2: Allow logic ops on all surface types. The UNORM restriction was lifted with Haswell and I simply hadn't noticed. Also, add missing BRW_NEW_STATE_BASE_ADDRESS dirty bit. Both caught by Eric Anholt. v3: Fix swapped per-RT DWord pairs. Eliminates bizarre hacks. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* i965: Update SF_CLIP_VIEWPORT for Broadwell.Kenneth Graunke2014-01-314-1/+121
| | | | | | | | | | | It has additional fields to support clipping to the viewport even if guardband clipping is enabled. v2: Update for viewport array changes. v3: No, seriously, update for viewport array changes. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]> [v1]
* i965: Rework SURFACE_STATE entries for Broadwell.Kenneth Graunke2014-01-315-1/+385
| | | | | | | | | | | | | | | | | | | | | | v2: Add missing SCS setting in gen8_emit_buffer_surface_state (caught by Eric Anholt). v3: Use stored QPitch rather than recomputing it. v4: Shift QPitch by 2 when setting it in the packet; bits 14:0 store bits 16:2 of the actual value (fixes myriads of cube and array texturing tests). Also, only enable cube face bits for cubemaps (matches Chris Forbes' commit on master). Port to use offset64. v5: s/gl_format/mesa_format/g v6: Fix DW5 of renderbuffer state, which neglected to subtract irb->mt->first_level. Use vertical_alignment() rather than hardcoding 4. Use ffs for multisample counts rather than a large switch statement (all caught/suggested by Eric). Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* i965: Update SOL state for Broadwell.Kenneth Graunke2014-01-317-19/+215
| | | | | | | | | | | | | | | | | | | | Unlike on Gen7, we can directly set the offset via the state packet. We also -have- to: the kernel SOL reset code won't work anymore. v2: Fix copy and paste mistake in buffer stride setup; drop stale comment (caught by Eric Anholt). Add a perf_debug for missing MOCS setup. v3: Rebase on Paul Berry's changes to CurrentVertexProgram. v4: Fix SO Write Offset handling. We need to set bits 20 and 21 so the hardware both loads and saves the offset. There's also a restriction that 3DSTATE_SO_BUFFER can only be programmed once per buffer between primitives, so the "reset to zero" code needed reworking. Fixes most of the transform feedback Piglit tests. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]> [v2]
* i965: Update the code that disables unused shader stages for Broadwell.Kenneth Graunke2014-01-315-1/+122
| | | | | | | v2: Also disable 3DSTATE_WM_CHROMAKEY for safety. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]> [v1]
* i965: Update 3DSTATE_CLIP for Broadwell.Kenneth Graunke2014-01-312-3/+8
| | | | | | | | | | | Broadwell's winding order, polygon fill, and viewport Z test fields have moved to DWord 1 of 3DSTATE_RASTER. v2: Add a perf_debug for a future optimization and improve commit message (both suggested by Eric Anholt). Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* i965: Rework vertex uploads for Broadwell.Kenneth Graunke2014-01-317-3/+274
| | | | | | | | | | | | | | v2: Emit a dummy 3DSTATE_VF_SGVS packet when not needed. v3: Add WARN_ONCE and perf_debugs requested by Eric Anholt. v4: Program 3DSTATE_SGVS even in the no-elements case so gl_VertexID continues working. Fix 3DSTATE_VF_INSTANCING to not use an element index to access the buffers array. Some ARB_draw_indirect prep work. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* i965: Update STATE_BASE_ADDRESS for Broadwell.Kenneth Graunke2014-01-314-1/+76
| | | | | | | | | | | | | | | v2: Fix missing "change" bit on instruction state base address (caught by Haihao Xiang). v3: Add a perf_debug for missing MOCS setup, requested by Eric. v4: Fix buffer sizes. The value, specified at bit 12 and up, is actually measured in 4k pages. We need to round up to the next multiple of 4k. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]> [v3] Reviewed-by: Matt Turner <[email protected]> [v4]
* i965: Update 3DSTATE_PS, 3DSTATE_WM, and add 3DSTATE_PS_EXTRA.Kenneth Graunke2014-01-315-2/+237
| | | | | | | | | | | | | | | | v2: Fix setting of GEN8_PSX_ATTRIBUTE_ENABLE after rebases. v3: Add missing binding table entry counts. Don't worry about alpha testing or alpha to coverage when setting the "Kill Pixel" bit; those are specified in 3DSTATE_PS_BLEND (caught by Eric Anholt). Drop unused _NEW_BUFFERS. Tidy comments. v4: Rebase on Paul Berry's changes to CurrentFragmentProgram. v5: Re-enable line stippling. It doesn't crash or anything. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]> [v3]
* i965: Rework 3DSTATE_VS for Broadwell.Kenneth Graunke2014-01-315-3/+144
| | | | | | | | | | | | | | | | | | v2: Remove incorrect MOCS shifts; rename urb_entry_write_offset to urb_entry_output_offset to closer match the documentation. v3: Only emit a non-zero constant buffer read length when active. v4: Add missing binding table counts (caught by Eric). v5: Rebase on Paul Berry's changes to CurrentVertexProgram. v6: Drop bogus SBE read length/offset field code. We were programming the wrong values, and our 3DSTATE_SBE code overrides any value we put here anyway with the correct one. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]> [v4]
* i965: Add the new 3DSTATE_PS_BLEND state packet.Kenneth Graunke2014-01-315-0/+142
| | | | | | | | | | | v2: Only set GEN8_PS_BLEND_HAS_WRITEABLE_RT if color buffer writes are enabled (caught by Eric Anholt). v3: Set non-blending flags (writeable RT, alpha test, alpha to coverage) for integer formats too. +14 Piglits. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]> [v2]
* i965: Replace DEPTH_STENCIL_STATE with Gen8's 3DSTATE_WM_DEPTH_STENCIL.Kenneth Graunke2014-01-315-1/+131
| | | | | | | | | | | | | | | v2: Use stencil->_WriteEnabled instead of setting GEN8_WM_DS_STENCIL_BUFFER_WRITE_ENABLE twice (suggested by Eric). v3: Mask stencil->WriteMask and stencil->ValueMask with 0xff. The field is only 8-bits, so we'd trip the new SET_FIELD assertion when core Mesa gave us a value like 0xFFFFFFFF. The Gen7 code uses structure field widths to implicitly do this truncation. Fixes Piglit tests. v4: Use uint32_t for dw1/dw2, not uint8_t. Worst. Typo. Ever. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]> [v2]
* i965: Update SF, SBE, and RASTER state for Broadwell.Kenneth Graunke2014-01-315-2/+311
| | | | | | | | | | | | | | | | The attribute override portion of 3DSTATE_SBE was split out into 3DSTATE_SBE_SWIZ; various bits of 3DSTATE_SF were split out into 3DSTATE_RASTER. v2: Set Force URB Read Offset bit. Eventually the URB read offset should be set in 3DSTATE_VS, but that will require some refactoring. v3: Rebase on viewport array changes. v4: Improve comments about URB read length/offset overrides. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* i965: Bump generation assertions on workaround flushes.Kenneth Graunke2014-01-311-2/+2
| | | | | | | | I haven't investigated whether these are necessary on Broadwell or not, but for paranoia's sake, we may as well continue doing them for now. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Chad Versace <[email protected]>
* i965: Duplicate gen7_atoms to gen8_atoms.Kenneth Graunke2014-01-311-1/+79
| | | | | | | | It's going to diverge significantly. Starting out with a copy allows future patches to change atoms one by one. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* radeon: move driContextSetFlags(ctx) call after ctx var is initializedBrian Paul2014-01-311-2/+3
| | | | | CC: "10.0" <[email protected]> Reviewed-by: Alex Deucher <[email protected]>
* r200: move driContextSetFlags(ctx) call after ctx var is initializedBrian Paul2014-01-311-2/+3
| | | | | | | Otherwise, ctx was a garbage value. CC: "10.0" <[email protected]> Reviewed-by: Alex Deucher <[email protected]>
* mesa: use _mesa_align_free() in _mesa_delete_buffer_object()Brian Paul2014-01-311-1/+1
| | | | | | | To match _mesa_align_malloc() call in _mesa_buffer_data(). Found by Colin Harrison <[email protected]> Signed-off-by: Brian Paul <[email protected]>
* dri3, i915, i965: Add __DRI_IMAGE_FOURCC_SARGB8888Keith Packard2014-01-302-0/+6
| | | | | | | | | | | | | | | | The __DRIimage createImageFromFds function takes a fourcc code, but there was no fourcc code that match __DRI_IMAGE_FORMAT_SARGB8. This adds a define for that format, adds a translation in DRI3 from __DRI_IMAGE_FORMAT_SARGB8 to __DRI_IMAGE_FOURCC_SARGB8888 and then adds translations *back* to __IMAGE_FORMAT_SARGB8 in both the i915 and i965 drivers. I'll refrain from comments on whether I think having two separate sets of format defines in dri_interface.h is a good idea or not... Fixes piglit glx-tfp and glx-visuals-depth Signed-off-by: Keith Packard <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* mesa: Add warning to _REV pack/unpack functions with incorrect behaviorMark Mueller2014-01-312-1/+18
| | | | | Signed-off-by: Mark Mueller <[email protected]> Signed-off-by: Marek Olšák <[email protected]>
* mesa: Return after ScissorArrayv or ScissorIndexed detect a parameter errorCourtney Goeltzenleuchter2014-01-291-0/+2
| | | | | | | | Fixes piglit arb_viewport_array-scissor-ignore. Signed-off-by: Courtney Goeltzenleuchter <[email protected]> Reviewed-by: Ian Romanick <[email protected]> Reviewed-by: Jon Ashburn <[email protected]>
* mesa: GL_ARB_map_buffer_alignment is not optionalSiavash Eliasi2014-01-295-6/+2
| | | | | | | | | | | | | | | Every driver supports it. All current and future Gallium drivers always support it, and all existing classic drivers support it. v2: Making GL_ARB_map_buffer_alignment a desktop OpenGL extension only. v3: Squash two commits together. v4 (idr): MIN_MAP_BUFFER_ALIGNMENT queries don't have any dependencies. In previous versions of the patch it depended on EXTRA_API_GL which would prevent the query from working in core profile contexts. Signed-off-by: Ian Romanick <[email protected]>
* nouveau: Use gl_constants::MinMapBufferAlignment as the alignment in ↵Siavash Eliasi2014-01-291-1/+2
| | | | | | | | | nouveau_bo_new This driver does not support GL_ARB_map_buffer_range, so no special treatment is needed for unaligned offsets in the mapping. Reviewed-by: Ian Romanick <[email protected]>
* radeon / r200: Use gl_constants::MinMapBufferAlignment as the alignment in ↵Siavash Eliasi2014-01-291-1/+1
| | | | | | | | | radeon_bo_open These drivers do not support GL_ARB_map_buffer_range, so no special treatment is needed for unaligned offsets in the mapping. Reviewed-by: Ian Romanick <[email protected]>
* mesa: Use _mesa_align_malloc in _mesa_buffer_dataSiavash Eliasi2014-01-291-2/+5
| | | | | | v2: Fixed memory leak. Reviewed-by: Ian Romanick <[email protected]>
* mesa: Set gl_constants::MinMapBufferAlignment to 64 by defaultSiavash Eliasi2014-01-291-1/+1
| | | | Reviewed-by: Ian Romanick <[email protected]>
* mesa/st: Unconditionally enable ARB_map_buffer_alignment.Siavash Eliasi2014-01-291-3/+3
| | | | Reviewed-by: Ian Romanick <[email protected]>
* i965/fs: Add a saturation propagation optimization pass.Matt Turner2014-01-284-0/+107
| | | | | | | | | | | | | | | | | | | | | | Transforms, for example, mul vgrf3, vgrf2, vgrf1 mov.sat vgrf4, vgrf3 into mul.sat vgrf3, vgrf2, vgrf1 mov vgrf4, vgrf3 which gives register_coalescing an opportunity to remove the MOV instruction. total instructions in shared programs: 1515039 -> 1504634 (-0.69%) instructions in affected programs: 798586 -> 788181 (-1.30%) GAINED: 0 LOST: 4 Reviewed-by: Jordan Justen <[email protected]>
* i965: Add can_do_saturate() method to backend_instruction.Matt Turner2014-01-282-0/+45
| | | | Reviewed-by: Jordan Justen <[email protected]>
* mesa: Generate correct error code in glDrawBuffers()Anuj Phogat2014-01-281-3/+5
| | | | | | | | | | | | | | | | | | | | | | | OpenGL 3.3 spec expects GL_INVALID_OPERATION: "For both the default framebuffer and framebuffer objects, the constants FRONT, BACK, LEFT, RIGHT, and FRONT AND BACK are not valid in the bufs array passed to DrawBuffers, and will result in the error INVALID OPERATION." But OpenGL 4.0 spec changed the error code to GL_INVALID_ENUM: "For both the default framebuffer and framebuffer objects, the constants FRONT, BACK, LEFT, RIGHT, and FRONT_AND_BACK are not valid in the bufs array passed to DrawBuffers, and will result in the error INVALID_ENUM." This patch changes the behaviour to match OpenGL 4.0 spec Fixes Khronos OpenGL CTS draw_buffers_api.test. V2: Update the comment in code. Cc: [email protected] Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* i965: Ignore 'centroid' interpolation qualifier in case of persample shadingAnuj Phogat2014-01-281-1/+2
| | | | | | | | | | | | I missed this change in commit f5cfb4a. It fixes the incorrect rendering caused in Dolphin Emulator. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=73915 Cc: [email protected] Signed-off-by: Anuj Phogat <[email protected]> Tested-by: Markus Wick <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* mesa: Allow depth = 0 parameter for TexImage3D.Kevin Rogovin2014-01-281-2/+2
| | | | | | | | | | Fixes the tests for the depth parameter for TexImage3D calls when the target type is GL_TEXTURE_2D_ARRAY or GL_TEXTURE_CUBE_MAP_ARRAY so that a depth value of 0 is accepted. Previously, the check incorrectly required the depth argument to be atleast 1. Reviewed-by: Matt Turner <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* mesa: Fix Type A _INT formats to MESA_FORMAT naming standardMark Mueller2014-01-2714-368/+368
| | | | | | | | | | | | | | | | | | | | | | | | | Replace Type A _INT formats names with _SINT to match naming spec, and update type C formats as follows: s/MESA_FORMAT_R_INT8\b/MESA_FORMAT_R_SINT8/g s/MESA_FORMAT_R_INT16\b/MESA_FORMAT_R_SINT16/g s/MESA_FORMAT_R_INT32\b/MESA_FORMAT_R_SINT32/g s/MESA_FORMAT_RG_INT8\b/MESA_FORMAT_RG_SINT8/g s/MESA_FORMAT_RG_INT16\b/MESA_FORMAT_RG_SINT16/g s/MESA_FORMAT_RG_INT32\b/MESA_FORMAT_RG_SINT32/g s/MESA_FORMAT_RGB_INT8\b/MESA_FORMAT_RGB_SINT8/g s/MESA_FORMAT_RGB_INT16\b/MESA_FORMAT_RGB_SINT16/g s/MESA_FORMAT_RGB_INT32\b/MESA_FORMAT_RGB_SINT32/g s/MESA_FORMAT_RGBA_INT8\b/MESA_FORMAT_RGBA_SINT8/g s/MESA_FORMAT_RGBA_INT16\b/MESA_FORMAT_RGBA_SINT16/g s/MESA_FORMAT_RGBA_INT32\b/MESA_FORMAT_RGBA_SINT32/g s/\bMESA_FORMAT_RED_RGTC1\b/MESA_FORMAT_R_RGTC1_UNORM/g s/\bMESA_FORMAT_SIGNED_RED_RGTC1\b/MESA_FORMAT_R_RGTC1_SNORM/g s/\bMESA_FORMAT_RG_RGTC2\b/MESA_FORMAT_RG_RGTC2_UNORM/g s/\bMESA_FORMAT_SIGNED_RG_RGTC2\b/MESA_FORMAT_RG_RGTC2_SNORM/g s/\bMESA_FORMAT_L_LATC1\b/MESA_FORMAT_L_LATC1_UNORM/g s/\bMESA_FORMAT_SIGNED_L_LATC1\b/MESA_FORMAT_L_LATC1_SNORM/g s/\bMESA_FORMAT_LA_LATC2\b/MESA_FORMAT_LA_LATC2_UNORM/g s/\bMESA_FORMAT_SIGNED_LA_LATC2\b/MESA_FORMAT_LA_LATC2_SNORM/g
* mesa: Fix MESA_FORMAT names containg SIGNEDMark Mueller2014-01-2714-356/+356
| | | | | | | | | | | | | | | | | | | | | | | | Update comments. Replace format names containing SIGNED with SNORM appended w/decoration per the format name spec: s/MESA_FORMAT_SIGNED_R8\b/MESA_FORMAT_R_SNORM8/g s/MESA_FORMAT_SIGNED_RG88_REV\b/MESA_FORMAT_R8G8_SNORM/g s/MESA_FORMAT_SIGNED_RGBX8888\b/MESA_FORMAT_X8B8G8R8_SNORM/g s/MESA_FORMAT_SIGNED_RGBA8888\b/MESA_FORMAT_A8B8G8R8_SNORM/g s/MESA_FORMAT_SIGNED_RGBA8888_REV\b/MESA_FORMAT_R8G8B8A8_SNORM/g s/MESA_FORMAT_SIGNED_R16\b/MESA_FORMAT_R_SNORM16/g s/MESA_FORMAT_SIGNED_GR1616\b/MESA_FORMAT_R16G16_SNORM/g s/MESA_FORMAT_SIGNED_RGB_16\b/MESA_FORMAT_RGB_SNORM16/g s/MESA_FORMAT_SIGNED_RGBA_16\b/MESA_FORMAT_RGBA_SNORM16/g s/MESA_FORMAT_SIGNED_A8\b/MESA_FORMAT_A_SNORM8/g s/MESA_FORMAT_SIGNED_I8\b/MESA_FORMAT_I_SNORM8/g s/MESA_FORMAT_SIGNED_L8\b/MESA_FORMAT_L_SNORM8/g s/MESA_FORMAT_SIGNED_A16\b/MESA_FORMAT_A_SNORM16/g s/MESA_FORMAT_SIGNED_I16\b/MESA_FORMAT_I_SNORM16/g s/MESA_FORMAT_SIGNED_L16\b/MESA_FORMAT_L_SNORM16/g s/MESA_FORMAT_SIGNED_AL88\b/MESA_FORMAT_L8A8_SNORM/g s/MESA_FORMAT_SIGNED_RG88\b/MESA_FORMAT_G8R8_SNORM/g s/MESA_FORMAT_SIGNED_RG1616\b/MESA_FORMAT_G16R16_SNORM/g
* mesa: Fix MESA_FORMAT names with ALPH, INTENSITY, and LUMINANCEMark Mueller2014-01-2711-522/+522
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Compressed spelled out color components ALPHA, INTENSITY, and LUMINANCE to A, I, and L: s/MESA_FORMAT_ALPHA_UINT8\b/MESA_FORMAT_A_UINT8/g' s/MESA_FORMAT_ALPHA_UINT16\b/MESA_FORMAT_A_UINT16/g' s/MESA_FORMAT_ALPHA_UINT32\b/MESA_FORMAT_A_UINT32/g' s/MESA_FORMAT_ALPHA_INT32\b/MESA_FORMAT_A_SINT32/g' s/MESA_FORMAT_ALPHA_INT16\b/MESA_FORMAT_A_SINT16/g' s/MESA_FORMAT_ALPHA_INT8\b/MESA_FORMAT_A_SINT8/g' s/MESA_FORMAT_INTENSITY_UINT8\b/MESA_FORMAT_I_UINT8/g' s/MESA_FORMAT_INTENSITY_UINT16\b/MESA_FORMAT_I_UINT16/g' s/MESA_FORMAT_INTENSITY_UINT32\b/MESA_FORMAT_I_UINT32/g' s/MESA_FORMAT_INTENSITY_INT32\b/MESA_FORMAT_I_SINT32/g' s/MESA_FORMAT_INTENSITY_INT16\b/MESA_FORMAT_I_SINT16/g' s/MESA_FORMAT_INTENSITY_INT8\b/MESA_FORMAT_I_SINT8/g' s/MESA_FORMAT_LUMINANCE_UINT8\b/MESA_FORMAT_L_UINT8/g' s/MESA_FORMAT_LUMINANCE_UINT16\b/MESA_FORMAT_L_UINT16/g' s/MESA_FORMAT_LUMINANCE_UINT32\b/MESA_FORMAT_L_UINT32/g' s/MESA_FORMAT_LUMINANCE_INT32\b/MESA_FORMAT_L_SINT32/g' s/MESA_FORMAT_LUMINANCE_INT16\b/MESA_FORMAT_L_SINT16/g' s/MESA_FORMAT_LUMINANCE_INT8\b/MESA_FORMAT_L_SINT8/g' s/MESA_FORMAT_LUMINANCE_ALPHA_UINT8\b/MESA_FORMAT_LA_UINT8/g' s/MESA_FORMAT_LUMINANCE_ALPHA_UINT16\b/MESA_FORMAT_LA_UINT16/g' s/MESA_FORMAT_LUMINANCE_ALPHA_UINT32\b/MESA_FORMAT_LA_UINT32/g' s/MESA_FORMAT_LUMINANCE_ALPHA_INT32\b/MESA_FORMAT_LA_SINT32/g' s/MESA_FORMAT_LUMINANCE_ALPHA_INT16\b/MESA_FORMAT_LA_SINT16/g' s/MESA_FORMAT_LUMINANCE_ALPHA_INT8\b/MESA_FORMAT_LA_SINT8/g' s/MESA_FORMAT_ALPHA_FLOAT16\b/MESA_FORMAT_A_FLOAT16/g' s/MESA_FORMAT_ALPHA_FLOAT32\b/MESA_FORMAT_A_FLOAT32/g' s/MESA_FORMAT_INTESITY_FLOAT16\b/MESA_FORMAT_I_FLOAT16/g' s/MESA_FORMAT_INTESITY_FLOAT32\b/MESA_FORMAT_I_FLOAT32/g' s/MESA_FORMAT_INTENSITY_FLOAT16\b/MESA_FORMAT_I_FLOAT16/g' s/MESA_FORMAT_INTENSITY_FLOAT32\b/MESA_FORMAT_I_FLOAT32/g' s/MESA_FORMAT_LUMINANCE_FLOAT16\b/MESA_FORMAT_L_FLOAT16/g' s/MESA_FORMAT_LUMINANCE_FLOAT32\b/MESA_FORMAT_L_FLOAT32/g' s/MESA_FORMAT_LUMINANCE_ALPHA_FLOAT16\b/MESA_FORMAT_LA_FLOAT16/g' s/MESA_FORMAT_LUMINANCE_ALPHA_FLOAT32\b/MESA_FORMAT_LA_FLOAT32/g'
* mesa: Change many Type P MESA_FORMATs to meet naming specMark Mueller2014-01-2772-1014/+1013
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Conversion of Type P formats as follows (w/related comment fixes): s/MESA_FORMAT_RGB565\b/MESA_FORMAT_B5G6R5_UNORM/g s/MESA_FORMAT_RGB565_REV\b/MESA_FORMAT_R5G6B5_UNORM/g s/MESA_FORMAT_ARGB4444\b/MESA_FORMAT_B4G4R4A4_UNORM/g s/MESA_FORMAT_ARGB4444_REV\b/MESA_FORMAT_A4R4G4B4_UNORM/g s/MESA_FORMAT_RGBA5551\b/MESA_FORMAT_A1B5G5R5_UNORM/g s/MESA_FORMAT_XBGR8888_SNORM\b/MESA_FORMAT_R8G8B8X8_SNORM/g s/MESA_FORMAT_XBGR8888_SRGB\b/MESA_FORMAT_R8G8B8X8_SRGB/g s/MESA_FORMAT_ARGB1555\b/MESA_FORMAT_B5G5R5A1_UNORM/g s/MESA_FORMAT_ARGB1555_REV\b/MESA_FORMAT_A1R5G5B5_UNORM/g s/MESA_FORMAT_AL44\b/MESA_FORMAT_L4A4_UNORM/g s/MESA_FORMAT_RGB332\b/MESA_FORMAT_B2G3R3_UNORM/g s/MESA_FORMAT_ARGB2101010\b/MESA_FORMAT_B10G10R10A2_UNORM/g s/MESA_FORMAT_Z24_S8\b/MESA_FORMAT_S8_UINT_Z24_UNORM/g s/MESA_FORMAT_S8_Z24\b/MESA_FORMAT_Z24_UNORM_S8_UINT/g s/MESA_FORMAT_X8_Z24\b/MESA_FORMAT_Z24_UNORM_X8_UINT/g s/MESA_FORMAT_Z24_X8\b/MESA_FORMAT_X8Z24_UNORM/g s/MESA_FORMAT_RGB9_E5_FLOAT\b/MESA_FORMAT_R9G9B9E5_FLOAT/g s/MESA_FORMAT_R11_G11_B10_FLOAT\b/MESA_FORMAT_R11G11B10_FLOAT/g s/MESA_FORMAT_Z32_FLOAT_X24S8\b/MESA_FORMAT_Z32_FLOAT_S8X24_UINT/g s/MESA_FORMAT_ABGR2101010_UINT\b/MESA_FORMAT_R10G10B10A2_UINT/g s/MESA_FORMAT_XRGB4444_UNORM\b/MESA_FORMAT_B4G4R4X4_UNORM/g s/MESA_FORMAT_XRGB1555_UNORM\b/MESA_FORMAT_B5G5R5X1_UNORM/g s/MESA_FORMAT_XRGB2101010_UNORM\b/MESA_FORMAT_B10G10R10X2_UNORM/g s/MESA_FORMAT_AL88\b/MESA_FORMAT_L8A8_UNORM/g s/MESA_FORMAT_AL88_REV\b/MESA_FORMAT_A8L8_UNORM/g s/MESA_FORMAT_AL1616\b/MESA_FORMAT_L16A16_UNORM/g s/MESA_FORMAT_AL1616_REV\b/MESA_FORMAT_A16L16_UNORM/g s/MESA_FORMAT_RG88\b/MESA_FORMAT_G8R8_UNORM/g s/MESA_FORMAT_GR88\b/MESA_FORMAT_R8G8_UNORM/g s/MESA_FORMAT_GR1616\b/MESA_FORMAT_R16G16_UNORM/g s/MESA_FORMAT_RG1616\b/MESA_FORMAT_G16R16_UNORM/g s/MESA_FORMAT_SRGBA8\b/MESA_FORMAT_A8B8G8R8_SRGB/g s/MESA_FORMAT_SARGB8\b/MESA_FORMAT_B8G8R8A8_SRGB/g s/MESA_FORMAT_SLA8\b/MESA_FORMAT_L8A8_SRGB/g Conflicts: src/mesa/drivers/dri/i965/brw_surface_formats.c src/mesa/main/format_pack.c src/mesa/main/format_unpack.c src/mesa/main/formats.c src/mesa/main/texformat.c src/mesa/main/texstore.c
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-26 22:33:37 +0000