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* r300: Fix handling of NV_vertex_program parametersNicolai Hähnle2009-09-212-6/+30
* Merge branch 'mesa_7_5_branch' into mesa_7_6_branchMichel Dänzer2009-09-211-1/+2
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| * intel: Fix crash in intel_flush().Michel Dänzer2009-09-211-1/+2
* | radeon: Fix legacy bo not to reuse dma buffers before refcount is 1.Pauli Nieminen2009-09-201-2/+7
* | r300/compiler: Fix trig instructions in R300 fpNicolai Hähnle2009-09-201-9/+9
* | radeon: Fix typo in variable name.Pauli Nieminen2009-09-201-1/+1
* | radeon: Improve WARN_ONCE macro to appear as single statement.Pauli Nieminen2009-09-201-5/+6
* | radeon: Fix "verts" debugging enableNicolai Hähnle2009-09-201-1/+1
* | Merge branch 'mesa_7_5_branch' into mesa_7_6_branchNicolai Hähnle2009-09-202-5/+14
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| * mesa/st: Initialize format bits of framebuffer renderbuffersNicolai Hähnle2009-09-201-0/+1
| * st/mesa: fix some incorrect branching/clean-up code in TexImage functionsBrian Paul2009-09-161-3/+3
| * st/mesa: fix texture memory allocation bugBrian Paul2009-09-161-2/+10
* | mesa/st: Create front renderbuffer on the fly when supplied with a surfaceNicolai Hähnle2009-09-201-3/+15
* | r300/compiler: Fix R300 fragment program regression introduced by 0723cd1...Nicolai Hähnle2009-09-201-1/+1
* | [i965] add a missing header fileZou Nan hai2009-09-181-0/+1
* | [i965] use intel_batchbuffer_flush to flush the clearZou Nan hai2009-09-181-1/+2
* | mesa: fix clip plane, fog issuesBrian Paul2009-09-161-4/+0
* | Merge branch 'mesa_7_5_branch' into mesa_7_6_branchIan Romanick2009-09-162-0/+667
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| * intel: Deassociated drawables from private context struct in intelUnbindContextIan Romanick2009-09-161-0/+8
| * mesa: compile glUniformMatrix() functions into display listsBrian Paul2009-09-151-0/+242
| * mesa: implement more glUniform display list functionsBrian Paul2009-09-151-1/+365
| * mesa: compile glUniform4f() into display listsBrian Paul2009-09-151-0/+26
| * mesa: compile glUseProgram/glUseProgramObjectARB into display listsBrian Paul2009-09-151-0/+28
* | i965: do a flush in clear, fix openarena render issue,Zou Nan hai2009-09-161-0/+1
* | Merge branch 'mesa_7_5_branch' into mesa_7_6_branchBrian Paul2009-09-153-3/+46
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| * glsl: added some link debug code (disabled)Brian Paul2009-09-141-0/+15
| * glsl: remove extra #version directives from concatenated shader sourcesBrian Paul2009-09-141-0/+28
| * mesa: raise GL_INVALID_ENUM not GL_INVALID_VALUE for glTexParamter errorsVinson Lee2009-09-111-3/+3
* | radeon: Remove structure allocation from iterator variable.Pauli Nieminen2009-09-111-1/+1
* | intel: disable intel_stencil_drawpixels() for nowBrian Paul2009-09-101-0/+16
* | Fix merge failIan Romanick2009-09-101-13/+0
* | mesa: need to set all stencil bits to 0 before setting the 1 bitsBrian Paul2009-09-101-0/+9
* | Merge branch 'mesa_7_5_branch' into mesa_7_6_branchIan Romanick2009-09-102-1/+6
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| * intel: add B43 chipset supportZhenyu Wang2009-09-102-1/+6
* | i965: Fix relocation delta for WM surfaces.Eric Anholt2009-09-101-1/+1
* | mesa: in texenvprogram code, only do saturation when really needed.Brian Paul2009-09-101-8/+53
* | radeon: Change debugging code to use macros instead of inline functions.Pauli Nieminen2009-09-102-43/+27
* | radeon: Add more verbose error message for failed command buffer.Pauli Nieminen2009-09-091-1/+3
* | Merge branch 'mesa_7_5_branch' into mesa_7_6_branchBrian Paul2009-09-095-1/+24
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| * mesa: bump version to 7.5.2Brian Paul2009-09-081-3/+3
| * i965: fix incorrect test for vertex position attributeBrian Paul2009-09-083-1/+4
| * i965: Fix warnings in intel_pixel_read.c.Eric Anholt2009-09-041-0/+4
| * intel: Also get the DRI2 front buffer when doing front buffer reading.Eric Anholt2009-09-044-1/+29
| * intel: Update Mesa state before span setup in glReadPixels.Eric Anholt2009-09-043-3/+13
| * intel: Move intel_pixel_read.c to shared for use with i965.Eric Anholt2009-09-042-306/+307
| * i965: Add missing state dependency of sf_unit on _NEW_BUFFERS.Eric Anholt2009-09-041-2/+4
| * intel: Align cubemap texture height to its padding requirements.Eric Anholt2009-09-041-0/+10
| * intel: Align untiled region height to 2 according to 965 docs.Eric Anholt2009-09-041-0/+7
| * i965: Fix source depth reg setting for FSes reading and writing to depth.Eric Anholt2009-09-043-1/+5
| * i965: Respect CondSwizzle in OPCODE_IF.Eric Anholt2009-09-041-1/+21
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