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* st/mesa: add st fp64 support (v7.1)Dave Airlie2015-02-202-125/+460
| | | | | | | | | | | | | | | | | | | | | | | | | | | This adds support to the state tracker for ARB_gpu_shader_fp64. The details are explained in comments within the code. v2 : add double to int/unsigned conversion v3: handle fp64 consts better v4: use DRSQ v4.1: add d2b v4.2: drop DDIV v5: split out some prep patches. v5.1: add some comments. v5.2: more comments v6: simplify down the double instruction generation loop. v7: Merge Ilia's two cleanup patches. v7.1: minor fixups for Ilia patch + cleanups Reviewed-by: Ilia Mirkin <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* mesa/st_tgsi_to_glsl: prepare add_constant for fp64Dave Airlie2015-02-201-20/+21
| | | | | | | | This just moves stuff around a little to make the next patch cleaner. Reviewed-by: Ilia Mirkin <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* st/glsl_to_tgsi: convert dst to an arrayDave Airlie2015-02-201-65/+65
| | | | | | | | This is just prep work for fp64 support where we need an array of 2 dst values. Reviewed-by: Ilia Mirkin <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* i965: just avoid warnings with fp64Dave Airlie2015-02-205-0/+42
| | | | | | | This just fills in some blanks to avoid warnings in the i965 driver. Reviewed-by: Chris Forbes <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* i965/vec4: Print "VS" or "GS" when compiles fail, not "vec4".Kenneth Graunke2015-02-191-1/+1
| | | | | | | | | | This is now trivial to do right. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> Reviewed-by: Ian Romanick <[email protected]> Reviewed-by: Kristian Høgsberg <[email protected]> Reviewed-by: Anuj Phogat <[email protected]>
* i965/vec4: Replace debug_flag with debug_enabled.Kenneth Graunke2015-02-196-10/+5
| | | | | | | | | | | backend_visitor now handles this, so we can delete the vec4_visitor specific code. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> Reviewed-by: Ian Romanick <[email protected]> Reviewed-by: Kristian Høgsberg <[email protected]> Reviewed-by: Anuj Phogat <[email protected]>
* i965: Make scheduler cycle estimates use the proper stage name.Kenneth Graunke2015-02-191-5/+6
| | | | | | | | | | | | | | | Previously, the vec4 backend labeled shaders as "vec4" - now it uses the specific names "VS" and "GS". The FS backend now correctly prints "VS" for vertex shaders (rather than "fs"). It also prints "FS" instead of "fs" for fragment shaders; preserving that behavior didn't seem essential. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> Reviewed-by: Ian Romanick <[email protected]> Reviewed-by: Kristian Høgsberg <[email protected]> Reviewed-by: Anuj Phogat <[email protected]>
* i965/fs: Un-hardcode DEBUG_WM, "FS", and "fragment".Kenneth Graunke2015-02-192-7/+8
| | | | | | | | | | These code paths can (or will) be used for other shader stages. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> Reviewed-by: Ian Romanick <[email protected]> Reviewed-by: Kristian Høgsberg <[email protected]> Reviewed-by: Anuj Phogat <[email protected]>
* i965: Create backend_visitor fields for debugging messages.Kenneth Graunke2015-02-192-0/+6
| | | | | | | | | | | | | We introduce three new fields in backend_visitor: - debug_enabled: whether or not INTEL_DEBUG & DEBUG_<stage flag> - stage_name: "vertex", "fragment", etc. for use in messages - stage_abbrev: "VS", "FS", etc. for use in messages Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> Reviewed-by: Ian Romanick <[email protected]> Reviewed-by: Kristian Høgsberg <[email protected]> Reviewed-by: Anuj Phogat <[email protected]>
* i965: Add a function to translate MESA_SHADER_* into DEBUG_* enums.Kenneth Graunke2015-02-192-0/+15
| | | | | | | | | | | | When compiling, we have a gl_shader_stage (MESA_SHADER_*) enum, and want to know whether debugging is enabled for that stage. This allows us to easily translate it into the corresponding debug flag. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> Reviewed-by: Ian Romanick <[email protected]> Reviewed-by: Kristian Høgsberg <[email protected]> Reviewed-by: Anuj Phogat <[email protected]>
* i965/fs: Use VARYING_SLOT checks rather than strcmp().Kenneth Graunke2015-02-192-3/+3
| | | | | | | | | | | | | | Comparing the location field is equivalent and more efficient. We'll also need this when we start using NIR for ARB programs, as our NIR converter will set the location field correctly, but probably won't use the GLSL names for these concepts. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> Reviewed-by: Ian Romanick <[email protected]> Reviewed-by: Kristian Høgsberg <[email protected]> Reviewed-by: Anuj Phogat <[email protected]>
* i965/fs: Remove type parameter from emit_vs_system_value().Kenneth Graunke2015-02-192-5/+4
| | | | | | | | | | | Every VS system value has type D. We can always add this back if that changes, but for now, it's extra typing. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> Reviewed-by: Ian Romanick <[email protected]> Reviewed-by: Kristian Høgsberg <[email protected]> Reviewed-by: Anuj Phogat <[email protected]>
* st/mesa: add GSL_TYPE_DOUBLE, new ir_unop_* switch casesBrian Paul2015-02-191-0/+12
| | | | | | | | To silence compiler warnings about unhandled switch cases. v2: move GSL_TYPE_DOUBLE case to the "Invalid type in type_size" section, per Ilia. Reviewed-by: Ilia Mirkin <[email protected]>
* st/mesa: fix sampler view reference counting bug in glDraw/CopyPixelsBrian Paul2015-02-191-6/+9
| | | | | | | | | | | Use pipe_sampler_view_reference() instead of ordinary assignment. Also add a new sanity check assertion. Fixes piglit gl-1.0-drawpixels-color-index test crash. But note that the test still fails. Cc: "10.4, 10.5" <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* swrast: fix multiple color buffer writingBrian Paul2015-02-191-11/+14
| | | | | | | | | | If a fragment program wrote to more than one color buffer, the first fragment color got replicated to all dest buffers. This fixes 5 piglit FBO tests, including fbo-drawbuffers-arbfp. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=45348 Cc: "10.4, 10.5" <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* mesa: remove unused _math_trans_4chan()Brian Paul2015-02-192-31/+0
| | | | | Reviewed-by: Matt Turner <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* i965/vec4: Calculate register allocation q values manually.Francisco Jerez2015-02-191-1/+17
| | | | | | | | | | | | This fixes a regression in the running time of Piglit introduced by commit 78e9043475d4bed8b50f7e413963c960fa0935bb, which increased the number of register allocation classes set up by the VEC4 back-end from 2 to 16. The algorithm used by ra_set_finalize() to calculate them is unnecessarily expensive, do it manually like the FS back-end does. Reported-by: Mark Janes <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* i965: Don't compact instructions with unmapped bits.Francisco Jerez2015-02-191-0/+53
| | | | | | | | | | | | | | | | | Some instruction bits don't have a mapping defined to any compacted instruction field. If they're ever set and we end up compacting the instruction they will be forced to zero. Avoid using compaction in such cases. v2: Align multiple lines of an expression to the same column. Change conditional compaction of 3-source instructions to an assertion. (Matt) v3: The 3-source instruction bit 105 is part of SourceIndex on CHV. Add assertion that reserved bit 7 is not set. (Matt) Document overlap with UIP and 64-bit immediate fields. v4: Make some more unmapped bit checks assertions. (Matt) Reviewed-by: Matt Turner <[email protected]>
* i965: Handle F16TO32/F32TO16 with dword src/dst consistently on both back-ends.Francisco Jerez2015-02-191-2/+12
| | | | | | | | | | | | | | Due to the way it's implemented in hardware, the F16TO32/F32TO16 instructions require the source/destination register to be of some 16-bit type in Align1 mode, while they require it to be some 32-bit type in Align16 mode (and as an undocumented feature the high 16 bits of the destination register are zeroed out in the case of the F32TO16 instruction on Gen7). Make their behaviour consistent so you can specify a 32 bit register type as source or destination and get predictable results in the most significant bits no matter what access mode is being used. Reviewed-by: Matt Turner <[email protected]>
* i965/gen8: Fix F32TO16 in vec4 mode if the source and destination registers ↵Francisco Jerez2015-02-191-9/+27
| | | | | | | | | | alias. We cannot zero out the destination register if it overlaps with the source. Use an Align1 instruction instead to zero out the high 16 bits after the conversion to half float. Reviewed-by: Matt Turner <[email protected]>
* i965/fs: Replace ud_reg_to_w() with a more general helper function.Francisco Jerez2015-02-192-24/+25
| | | | Reviewed-by: Matt Turner <[email protected]>
* i965/vec4: Don't attempt to reduce swizzles of send from GRF instructions.Francisco Jerez2015-02-191-1/+2
| | | | Reviewed-by: Matt Turner <[email protected]>
* i965/vec4: Fix constant propagation across different types.Francisco Jerez2015-02-191-0/+10
| | | | | | | | | | If the source type differs from the original type of the constant we need to bit-cast it before propagating, otherwise the original type information will be lost. If the constant was a vector float there isn't much we can do, because the result of bit-casting the component values of a vector float cannot itself be represented as an immediate. Reviewed-by: Matt Turner <[email protected]>
* mesa: Adds check for integer internal format and num samples in ↵Eduardo Lima Mitev2015-02-191-0/+10
| | | | | | | | | | | | | glRenderbufferStorageMultisample Per GLES3 specification, section 4.4 Framebuffer objects page 198, "If internalformat is a signed or unsigned integer format and samples is greater than zero, then the error INVALID_OPERATION is generated.". Fixes 1 dEQP test: * dEQP-GLES3.functional.negative_api.buffer.renderbuffer_storage_multisample Reviewed-by: Matt Turner <[email protected]>
* mesa: Returns correct error values from gl(Get)SamplerParameter*() on GL-ES 3.0+Eduardo Lima Mitev2015-02-191-12/+60
| | | | | | | | | | | | | | | | | | | '3.8.2 Sampler Objects' section of the GL-ES 3.0 specification states: "An INVALID_OPERATION error is generated if sampler is not the name of a sampler object previously returned from a call to GenSamplers." In desktop GL, an GL_INVALID_VALUE is returned instead. Fixes 6 dEQP failing tests: * dEQP-GLES3.functional.negative_api.shader.get_sampler_parameteriv * dEQP-GLES3.functional.negative_api.shader.get_sampler_parameterfv * dEQP-GLES3.functional.negative_api.shader.sampler_parameteri * dEQP-GLES3.functional.negative_api.shader.sampler_parameteriv * dEQP-GLES3.functional.negative_api.shader.sampler_parameterf * dEQP-GLES3.functional.negative_api.shader.sampler_parameterfv Reviewed-by: Matt Turner <[email protected]>
* st/mesa: don't die for ETC2 formats when no driver supportIlia Mirkin2015-02-191-0/+3
| | | | Signed-off-by: Ilia Mirkin <[email protected]>
* glsl/ir: Add builtin function support for doublesDave Airlie2015-02-191-0/+11
| | | | | | | v2: add d2b, more ir_constant stuff (Ilia) Signed-off-by: Dave Airlie <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* mesa: add double uniform support. (v5)Dave Airlie2015-02-194-32/+228
| | | | | | | | | | | | | | | | This adds support for the new uniform interfaces from ARB_gpu_shader_fp64. v2: support ARB_separate_shader_objects ProgramUniform*d* (Ian) don't allow boolean uniforms to be updated (issue 15) (Ian) v3: fix size_mul v4: Teach uniform update to take into account double precision (Topi) v5: add transpose for double case (Ilia) Signed-off-by: Dave Airlie <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* mesa: add ARB_gpu_shader_fp64 extension info (v2)Dave Airlie2015-02-192-0/+2
| | | | | | | | | | | This just adds the entries to extensions.c and mtypes.h v2: use core profile only (Ian) Signed-off-by: Dave Airlie <[email protected]> Reviewed-by: Ian Romanick <[email protected]> Reviewed-by: Matt Turner <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* glapi: add ARB_gpu_shader_fp64 (v2)Dave Airlie2015-02-193-35/+319
| | | | | | | | | | | | | | | Just add the xml file covering this extension, and dummy interface files in mesa, and fix up sanity tests. v2: Enable ProgramUniform*d* from ARB_separate_shader_objects (Ian) use 40 instead of 43 for dispatch_sanity.cpp (Chris) uncomment PU sanity tests. Signed-off-by: Dave Airlie <[email protected]> Reviewed-by: Ian Romanick <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* st/mesa: pass etc2 textures to driver if supportedIlia Mirkin2015-02-194-11/+40
| | | | | | | If the driver actually supports ETC2, don't decode it in software. Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* nir: Add a nir_shader_compiler_options struct pointed to by the shaders.Eric Anholt2015-02-181-0/+2
| | | | | | | | | This will be used to give the optimization passes a chance to customize behavior for the particular target device. v2: Rebase to master (no TGSI->NIR present) Reviewed-by: Kenneth Graunke <[email protected]> (v1)
* i965/simd8vs: Fix SIMD8 atomics (read-only)Jordan Justen2015-02-181-8/+16
| | | | | | | | | | | | | | | | An update for d9cd982d556be560af3bcbcdaf62b6b93eb934a5. A similar change was needed for CS to allow the piglit test tests/spec/arb_compute_shader/execution/simple-barrier-atomics.shader_test to pass. The previous change (d9cd982d) should fix cases that write atomics, such as atomicCounterIncrement, and this change will fix cases than only read atomics, such as atomicCounter. Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Ben Widawsky <[email protected]> Reviewed-by: Francisco Jerez <[email protected]>
* i915: For the love of all that is holy, stop saying "IGD"Adam Jackson2015-02-181-7/+7
| | | | | | | a001 and a011 are pineview chips. Say so. Reviewed-by: Matt Turner <[email protected]> Signed-off-by: Adam Jackson <[email protected]>
* st/mesa: add ARB_pipeline_statistics_query supportIlia Mirkin2015-02-182-4/+55
| | | | | Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* i965: implement ARB_pipeline_statistics_queryBen Widawsky2015-02-173-0/+106
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | NOTE: The implementation was initially one patch, this. All the history is kept here, even though all the core mesa changes were moved to the parent of this patch. This patch implements ARB_pipeline_statistics_query. This addition to GL does not add a new API. Instead, it adds new tokens to the existing query APIs. The work to hook up the new tokens is trivial due to it's similarity to the previous work done for the query APIs. I've implemented all the new tokens to some degree, but have stubbed out the untested ones at the entry point for Begin(). Doing this should allow the remainder of the code to be left in. The new tokens give GL clients a way to obtain stats about the GL pipeline. Generally, you get the number of things going in, invocations, and number of things coming out, primitives, of the various stages. There are two immediate uses for this, performance information, and debugging various types of misrendering. I doubt one can use these for debugging very complex applications, but for piglit tests, it should be quite useful. Tessellation shaders, and compute shaders are not addressed in this patch because there is no upstream implementation. I've implemented how I believe tessellation shader stats will work for Intel hardware (though there is a bit of ambiguity). Compute shaders are a bit more interesting though, and I don't yet know what we'll do there. For the lazy, here is a link to the relevant part of the spec: https://www.opengl.org/registry/specs/ARB/pipeline_statistics_query.txt Running the piglit tests http://lists.freedesktop.org/archives/piglit/2014-November/013321.html (http://cgit.freedesktop.org/~bwidawsk/piglit/log/?h=pipe_stats) yield the following results: > piglit-run.py -t stats tests/all.py output/pipeline_stats > [5/5] pass: 5 Running Test(s): 5 v2: - Don't allow pipeline_stats to be per stream (Ilia). This may (not sure) be needed for AMD_transform_feedback4, which we do not support. > If AMD_transform_feedback4 is supported then GEOMETRY_SHADER_PRIMITIVES_- > EMITTED_ARB counts primitives emitted to any of the vertex streams for > which STREAM_RASTERIZATION_AMD is enabled. - Remove comment from GL3.txt because it is only used for extensions that are part of required versions (Ilia) - Move the new tokens to a new XML doc instead of using the main GL4x.xml (Ilia) - Add a fallthrough comment (Ilia) - Only divide PS invocations by 4 on HSW+ (Ben) v3: - Add ARB_pipeline_statistics_query to relnotes.html - Add ARB_pipeline_statistics_query.xml to the Makefile.am, and master XML (Ilia) - Correct extension number (Ilia) - Add link to xml in the main GL API xml (Ilia) - remove special GS case from gen6_end_query (Ian) - Make lookup table static so gcc doesn't initialized it on every call (Ian) - Use if (_mesa_has_geometry_shaders(ctx)) instead of explicit checks (Ian) - Core mesa parts moved into a prep patch (Ilia) v4: - Change to 10.6 relnotes since we missed 10.5 window - Moved compute shader stuff into the switch statement (Jordan) - Jordan: Add compute shader support v5: - Fixed relnote style (Ilia) v6: - Rebased on master which beat me to adding the first relnotes - essentially this undoes v5 (which had a typo anyway) - Some code style fixes (Ken) - Remove some excess comments (Ken) - Unify tessellation failure style - unreachable (Ken) - Fix workaround comment for PS invocations (Ken) Signed-off-by: Ben Widawsky <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* mesa: Add support for the ARB_pipeline_statistics_query extensionBen Widawsky2015-02-174-0/+108
| | | | | | | | | | | | | | | | | | | | | | | | | This was originally part of a single patch which added the extension, and implemented it for i965 classic. For information about the evolution of the patch, please see the subsequent commit. One difference here as compared to the original mega patch is this does build support for the compute shader query. Since it cannot be tested on any platform, it will always return NULL for now. Jordan has already written a patch to address this, and when that patch lands, this logic can be modified. v2: Fix typo in subject (Brian Paul) Add checks for desktop gl (Ilia) Fail for any callers for now (Ilia) Update QueryCounterBits for new tokens (Ilia) Jordan: Use _mesa_has_compute_shaders Signed-off-by: Ben Widawsky <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]> v3: Rebased on patch which adds the proper information to unstub tessellation shaders. Reviewed-by: Kenneth Graunke <[email protected]>
* mesa: Add _mesa_has_compute_shadersJordan Justen2015-02-171-0/+11
| | | | | | | | | | v2 (Ben): Change GLboolean to bool as requested by Ian Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]> Reviewed-by: Ben Widawsky <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Signed-off-by: Ben Widawsky <[email protected]>
* mesa: Add ARB_tessellation_shader to extension table.Fabian Bieler2015-02-172-0/+2
| | | | Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Prefer Meta over the BLT for BlitFramebuffer.Kenneth Graunke2015-02-171-7/+7
| | | | | | | | | | | | | | | | | There's some debate about whether we should use Meta or BLORP, but either should run circles around the BLT engine. In particular, this means that Gen8+ will use the 3D engine for blits, like we do on Gen6-7. Improves performance in "copypixrate -blit -back" (from Mesa demos) by 232.037% +/- 3.15795% (n=10) on Broadwell GT3e. v2: Rebase on Laura's changes. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Matt Turner <[email protected]> Cc: "10.5" <[email protected]>
* i965/fs: Add algebraic optimizations for MAD.Matt Turner2015-02-171-0/+43
| | | | | | | | | total instructions in shared programs: 5764176 -> 5763808 (-0.01%) instructions in affected programs: 25121 -> 24753 (-1.46%) helped: 164 HURT: 2 Reviewed-by: Kenneth Graunke <[email protected]>
* i965/fs: Emit MAD instructions when possible.Matt Turner2015-02-172-8/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Previously we didn't emit MAD instructions since they cannot take immediate arguments, but with the opt_combine_constants() pass we can handle this properly. total instructions in shared programs: 5920017 -> 5733278 (-3.15%) instructions in affected programs: 3625153 -> 3438414 (-5.15%) helped: 22017 HURT: 870 GAINED: 91 LOST: 49 Without constant pooling, this patch is a complete loss: total instructions in shared programs: 5912589 -> 5987888 (1.27%) instructions in affected programs: 3190050 -> 3265349 (2.36%) helped: 1564 HURT: 17827 GAINED: 27 LOST: 101 And since the constant pooling patch by itself hurt a bunch of things, from before constant pooling to this patch the results are: total instructions in shared programs: 5895414 -> 5747946 (-2.50%) instructions in affected programs: 3617993 -> 3470525 (-4.08%) helped: 20478 HURT: 4469 GAINED: 54 LOST: 146 Reviewed-by: Kenneth Graunke <[email protected]>
* i965/fs: Allow immediates in MAD and LRP instructions.Matt Turner2015-02-172-3/+33
| | | | | | | | | | | | | | | And then the opt_combine_constants() pass will pull them out into registers. This will allow us to do some algebraic optimizations on MAD and LRP. total instructions in shared programs: 5946656 -> 5931320 (-0.26%) instructions in affected programs: 778247 -> 762911 (-1.97%) helped: 3780 HURT: 6 GAINED: 12 LOST: 12 Reviewed-by: Kenneth Graunke <[email protected]>
* i965/fs: Add pass to combine immediates.Matt Turner2015-02-174-0/+287
| | | | | | | | | | | | | total instructions in shared programs: 5885407 -> 5940958 (0.94%) instructions in affected programs: 3617311 -> 3672862 (1.54%) helped: 3 HURT: 23556 GAINED: 31 LOST: 165 ... but will allow us to always emit MAD instructions. Reviewed-by: Kenneth Graunke <[email protected]>
* i965/fs: Remove force_writemask_all assertion for execsize < 8.Matt Turner2015-02-171-1/+0
| | | | | | | This doesn't seem to be necessary. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=86974 Reviewed-by: Kenneth Graunke <[email protected]>
* i965/cfg: Add function to generate a dot file of the dominator tree.Matt Turner2015-02-172-0/+11
| | | | Reviewed-by: Kenneth Graunke <[email protected]>
* i965/cfg: Add function to generate a dot file of the CFG.Matt Turner2015-02-172-0/+15
| | | | Reviewed-by: Kenneth Graunke <[email protected]>
* i965/cfg: Calculate the immediate dominators.Matt Turner2015-02-172-4/+76
| | | | Reviewed-by: Kenneth Graunke <[email protected]>
* i965/cfg: Allow cfg::dump to be called without a visitor.Matt Turner2015-02-171-1/+2
| | | | | | | | | The fs_visitor's dump_instruction() implementation calls cfg_t() indirectly through calculate_live_intervals, so if you have an infinite loop in the CFG code, you can't call cfg::dump(fs_visitor *) to debug it. Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Allow exec_list sentinels as arguments to insert functions.Matt Turner2015-02-171-2/+4
| | | | | | | | | | | | | | | | | | To insert an instruction at the end of a basic block, we typically do something like inst = block->last_non_control_flow_inst(); inst->insert_after(block, new_inst); But blocks can consist of a single control flow instruction, so inst will actually be the exec_list's head sentinel. We shouldn't use it as if it were a regular instruction, but it is safe to insert something after it. This patch avoids assert-failing because an exec_list sentinel wasn't in the basic block's instruction list. Reviewed-by: Kenneth Graunke <[email protected]>
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