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* i965: Fix gl_TessLevelOuter[] for isolines.Kenneth Graunke2016-03-182-6/+22
* i965: Decode non-normalized coordinates bit in SAMPLER_STATE.Kenneth Graunke2016-03-181-2/+3
* i965: Account for TES in is_drawing_points().Kenneth Graunke2016-03-181-1/+8
* st/mesa: clean up st_translate_texture_target()Brian Paul2016-03-181-25/+44
* st/mesa: simplify drawpixels shader code with tgsi transform helper functionsBrian Paul2016-03-181-64/+18
* st/mesa: simplify bitmap shader code with tgsi transform helper functionsBrian Paul2016-03-181-37/+8
* mesa: remove remaining tabs in prog_parameter.cTimothy Arceri2016-03-181-8/+8
* mesa: inline _mesa_add_unnamed_constant()Timothy Arceri2016-03-182-24/+6
* mesa: simplify and inline _mesa_lookup_parameter_index()Timothy Arceri2016-03-183-41/+18
* mesa: make _mesa_lookup_parameter_constant staticTimothy Arceri2016-03-182-100/+94
* mesa: remove unused functionTimothy Arceri2016-03-181-6/+0
* st/mesa: honour sized internal formats in st_choose_format (v2)Nicolai Hähnle2016-03-171-21/+6
* nir: add a bit_size parameter to nir_ssa_dest_initConnor Abbott2016-03-172-7/+10
* nir: rename nir_const_value fields to include bitsize informationIago Toral Quiroga2016-03-176-63/+63
* nir: update opcode definitions for different bit sizesConnor Abbott2016-03-171-0/+18
* i965/nir: fix check to resolve booleans to work with sized nir_alu_typeSamuel Iglesias Gonsálvez2016-03-171-1/+1
* i965/nir: Lower nir compute shader shared variablesJordan Justen2016-03-173-0/+11
* i965: Skip execution size adjustment for instructions of width 4Iago Toral Quiroga2016-03-171-1/+13
* i965/vec4/gen6: fix exec_size for MOV with a width of 4 in generate_gs_ff_sync()Samuel Iglesias Gonsalvez2016-03-171-1/+3
* i965/vec4/gen6: fix exec_size for instructions with destination width of 4Samuel Iglesias Gonsalvez2016-03-171-0/+6
* i965/vec4/gen6: fix exec_size for instructions with width of 4 in generate_gs...Samuel Iglesias Gonsalvez2016-03-171-0/+3
* i965/gs/gen6: fix execsize for instructions with width of 4 in gen6_sol_progr...Samuel Iglesias Gonsalvez2016-03-171-1/+10
* i965: set correct execsize for MOVS with a width of 4 in brw_find_live_channelIago Toral Quiroga2016-03-171-0/+3
* i965/eu: set execution size for SEND message in brw_send_indirect_messageIago Toral Quiroga2016-03-171-0/+3
* i965/fs: Set exec size for gen7 pull const loadsIago Toral Quiroga2016-03-171-0/+1
* i965/eu: set correct execution size in brw_NOPIago Toral Quiroga2016-03-171-2/+3
* meta: Don't use integer handles for shaders or programs.Kenneth Graunke2016-03-167-147/+130
* mesa: Expose compile_shader() and link_program() beyond the file.Kenneth Graunke2016-03-162-10/+16
* mesa: Make link_program() take a gl_shader_program, not a GLuint.Kenneth Graunke2016-03-161-6/+4
* mesa: Make compile_shader() take a gl_shader, not a GLuint.Kenneth Graunke2016-03-161-9/+6
* meta: Use the _mesa_meta_compile_and_link_program helper more places.Kenneth Graunke2016-03-162-40/+8
* meta: Use ARB_explicit_attrib_location in the rest of the meta shaders.Kenneth Graunke2016-03-163-19/+17
* mesa: Ignore glPointSize when GL_POINT_SIZE_ARRAY_OES is enabledPlamena Manolova2016-03-151-0/+2
* st/mesa: set image access flags in st_bind_imagesNicolai Hähnle2016-03-141-0/+15
* st/glsl_to_tgsi: set FS_EARLY_DEPTH_STENCIL when requiredNicolai Hähnle2016-03-141-0/+3
* st/glsl_to_tgsi: set memory access type on image intrinsicsNicolai Hähnle2016-03-141-0/+7
* st/glsl_to_tgsi: provide Texture and Format information for image opsNicolai Hähnle2016-03-141-9/+15
* get: reconcile aliasing enums for MaxCombinedShaderOutputResourcesNicolai Hähnle2016-03-142-2/+11
* i965/fs: Restrict inequality that can only hold equal in saturate propagation.Francisco Jerez2016-03-141-1/+1
* i965/vec4: Consider removal of no-op MOVs as progress during register coalesce.Francisco Jerez2016-03-141-0/+1
* i965/fs: Add missing analysis invalidation in fixup_3src_null_dest().Francisco Jerez2016-03-141-0/+6
* i965/fs: Add missing analysis invalidation in opt_sampler_eot().Francisco Jerez2016-03-141-1/+4
* mesa: docs: Intel i965 hardware limits.Sarah Sharp2016-03-141-7/+48
* mesa: docs: i965: Use correct doxygen groupings syntaxSarah Sharp2016-03-141-2/+2
* i965: Remove useless IR self-destruct backend_shader method.Francisco Jerez2016-03-132-8/+0
* i965: Use foreach_in_list_reverse_safe() macro.Matt Turner2016-03-121-12/+2
* i965/chv: Display proper brandingBen Widawsky2016-03-113-5/+31
* i965/chv: Update lower min for CS threadsBen Widawsky2016-03-111-1/+1
* i965/chv: Check that compute threads are above thresholdBen Widawsky2016-03-112-0/+9
* i965/chv: Use kernel provided info for max_cs_threadsBen Widawsky2016-03-111-1/+8
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