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* dri: Remove driSwapControlExtensionKristian Høgsberg2011-11-023-21/+1
| | | | DRI1-only as well.
* dri: Drop driCopySubBufferExtensionKristian Høgsberg2011-11-023-21/+0
| | | | Another DRI1-only extension.
* dri: Drop driReadDrawableExtensionKristian Høgsberg2011-11-024-11/+0
| | | | All DRI2 drivers support setting a separate read drawable.
* dri: Drop driLegacyExtensionKristian Høgsberg2011-11-023-10/+0
| | | | There are no DRI1 drivers left.
* Build fix for -Werror=int-to-pointer-cast -Werror=pointer-to-int-castJeremy Huddleston2011-11-012-4/+4
| | | | Signed-off-by: Jeremy Huddleston <[email protected]>
* intel: fix potential segfault errorYuanhan Liu2011-11-021-2/+4
| | | | | Signed-off-by: Yuanhan Liu <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* swrast: Use MapRenderbuffer for glReadPixels(GL_DEPTH_COMPONENT) fast-paths.Eric Anholt2011-11-011-68/+63
| | | | | | | | This fixes issues with the code playing fast and loose with types of buffers, and as a bonus avoids the wrappers that were previously used to pull bits out of packed depth/stencil buffers. Reviewed-by: Brian Paul <[email protected]>
* mesa: Make unpack_uint_z_row return 32 bits of data.Eric Anholt2011-11-011-25/+10
| | | | | | | | | Some of the return values were u32, some were 24 bits, and z16 returned 16 bits. The caller would have to do all the work of interpreting the format all over again. However, there are no callers of this function at this point. Reviewed-by: Brian Paul <[email protected]>
* nouveau: Add implementation of MapRenderbuffer.Eric Anholt2011-11-011-0/+46
| | | | | | | | Perhaps the easiest implementation, nouveau can directly map buffers even if tiled, and uses separate surfaces for its texture renderbuffers so we don't have to worry about that offset. Reviewed-by: Brian Paul <[email protected]>
* radeon: Add implementation of MapRenderbuffer.Eric Anholt2011-11-012-0/+98
| | | | | | | | | | | Unlike intel, we do a blit to/from GTT memory in order to untile/retile the renderbuffer data, since we don't have fence registers for accessing it. (There is software tiling code in radeon_tile.c, but it's unused and doesn't support macro tiling) Reviewed-by: Brian Paul <[email protected]>
* intel: Use MapRenderbuffer in spans setup.Eric Anholt2011-11-011-23/+10
| | | | Reviewed-by: Brian Paul <[email protected]>
* intel: Add an implementation of MapRenderbuffer.Eric Anholt2011-11-014-1/+130
| | | | | | | | | v2: Add separate stencil S8 W-tile swizzling/deswizzling. Tested for the swizzling case with env INTEL_SEPARATE_STENCIL=1 INTEL_HIZ=1 ./bin/hiz-depth-stencil-test-fbo-d24-s8 v3: Apply Chad's fix for S8 window system buffers. Reviewed-by: Chad Versace <[email protected]>
* intel: Improve the debug info for renderbuffer allocation.Eric Anholt2011-11-011-4/+4
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* Add MapRenderbuffer implementations for software drivers.Eric Anholt2011-11-016-4/+127
| | | | | | | | | | Mesa core's is generic for things like osmesa. For swrast_dri.so, we have to do Y flipping. The front-buffer path isn't actually tested, though, because both before and after it fails with a BadMatch in XGetImage. Reviewed-by: Brian Paul <[email protected]>
* mesa: Add a driver hook for mapping renderbuffers.Eric Anholt2011-11-011-0/+9
| | | | Reviewed-by: Brian Paul <[email protected]>
* Revert "intel: Drop the immediate validation of the texture object in TFP."Eric Anholt2011-11-011-0/+5
| | | | | | | | | | | | | | | | | | This reverts commit abaebcee787eeb8a89bf7a82ed4d1532fcde5e39. The assertion I made was that "the zero-copy code in validation" would zero copy. Of course, I deleted that check back in January because the two sites that would trigger it (glTexImage() and this one) both immediately bound their mt to the object, making the other check pointless. Removes two extra blits in glx-tfp. Also fixed the Android home screen, which wasn't rendering because the extra copy broke the relationship between the texture and the eglimage. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=42152 Tested-by: Chad Versace <[email protected]> Tested-by: Eugeni Dodonov <[email protected]>
* mesa: make save_EndConditionalRender param list (void) to silence warningBrian Paul2011-11-011-1/+1
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* mesa: Fix memory leak in out-of-memory path.Vinson Lee2011-11-011-0/+1
| | | | Fixes Coverity resource leak defect.
* dri/nouveau: Enable NV_fog_distance on NV10 and NV20 hardwareNicholas Miell2011-11-014-9/+30
| | | | | | | Add support for NV_fog_distance to the NV10 and NV20 drivers. [ Francisco Jerez: Fix fog coord. signedness for GL_EYE_RADIAL_NV/GL_EYE_PLANE on nv20 ]
* st/mesa: Enable NV_fog_distance for Gallium driversNicholas Miell2011-11-011-0/+1
| | | | | The fixed-function generated vertex program is all that's needed for Gallium drivers.
* mesa: Add NV_fog_distance to the fixed-function vertex program generatorNicholas Miell2011-11-011-4/+39
| | | | | This is all that is needed to implement NV_fog_distance on programmable hardware.
* mesa: Add the basics for the NV_fog_distance extensionNicholas Miell2011-11-014-0/+22
| | | | No driver implements it yet.
* i965: Fix flat integral varyings.Paul Berry2011-10-312-3/+5
| | | | | | | | | | | | | | | | | Previously, the vertex and fragment shader back-ends assumed that all varyings were floats. In GLSL 1.30 this is no longer true--they can also be of integral types provided that they have an interpolation qualifier of "flat". This required two changes in each back-end: assigning the correct type to the register that holds the varying value during shader execution, and assigning the correct type to the register that ties the varying value to the rest of the graphics pipeline (the message register in the case of VS, and the payload register in the case of FS). Fixes piglit tests fs-int-interpolation and fs-uint-interpolation. Acked-by: Kenneth Graunke <[email protected]>
* i965/gen6+: Switch GLSL from ALT to IEEE floating point modePaul Berry2011-10-314-6/+26
| | | | | | | | | | | | | | | | | | | | | | | | | | | i965 graphics hardware has two floating point modes: ALT and IEEE. In ALT mode, floating-point operations never generate infinities or NaNs, and MOV instructions translate infinities and NaNs to finite values. In IEEE mode, infinities and NaNs behave as specified in the IEEE 754 spec. Previously, we used ALT mode for all vertex and fragment programs, whether they were GLSL programs or ARB programs. The GLSL spec is sufficiently vague about how infs and nans are to be handled that it was unclear whether this mode was compliant with the GLSL 1.30 spec or not, and it made it very difficult to test the isinf() and isnan() functions. This patch changes i965 GLSL programs to use IEEE floating-point mode, which is clearly compliant with GLSL 1.30's inf/nan requirements. In addition to making the Piglit isinf and isnan tests pass, this paves the way for future support of the ARB_shader_precision extension. Unfortunately we still have to use ALT floating-point mode when executing ARB programs, because those programs require 0^0 == 1, and i965 hardware generates 0^0 == NaN in IEEE mode. Fixes piglit tests "isinf-and-isnan fs_fbo", "isinf-and-isnan vs_fbo", and {fs,vs}-{isinf,isnan}-{vec2,vec3,vec4}.
* mesa: add note about immutable textures for _mesa_test_texobj_completeness()Brian Paul2011-10-311-0/+4
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* swrast: implement GL_ARB_texture_storageBrian Paul2011-10-314-0/+43
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* st/mesa: implement GL_ARB_texture_storageBrian Paul2011-10-312-0/+63
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* mesa: plug in dispatch functions for GL_ARB_texture_storageBrian Paul2011-10-311-0/+9
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* mesa: compile new texstore.c fileBrian Paul2011-10-312-0/+2
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* mesa: init extension entry for GL_ARB_texture_storageBrian Paul2011-10-311-0/+1
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* mesa: display list dispatch for GL_ARB_texture_storageBrian Paul2011-10-311-0/+9
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* mesa: new glTexImage error checks for GL_ARB_texture_storageBrian Paul2011-10-311-0/+34
| | | | | If the texture memory was allocated with glTexStorage1/2/3D() we can only change the image data with glTexSubImage calls.
* mesa: glGetTexParameter support for GL_ARB_texture_storageBrian Paul2011-10-311-0/+12
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* mesa: implement new functions for GL_ARB_texture_storageBrian Paul2011-10-312-0/+463
| | | | | This is the glTexStorage1D/2D/3D() functions. Basically do error checking then call the driver hook to actually allocate memory.
* glapi: regenerated API files for GL_ARB_texture_storageBrian Paul2011-10-313-5079/+5196
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* mesa: add new driver hook for AllocTextureStorage()Brian Paul2011-10-311-0/+9
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* mesa: add new fields for GL_ARB_texture_storageBrian Paul2011-10-311-0/+2
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* radeon/r200: drop remains of r300/r600 support along with old drm 1.x kernelDave Airlie2011-10-3015-553/+102
| | | | | | | | This drops all the old drmSupports* checks since KMS does them all, and it also drop R300_CLASS and R600_CLASS. Signed-off-by: Dave Airlie <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* intel: enable GL_OES_draw_textureChia-I Wu2011-10-301-0/+1
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* meta: add _mesa_meta_DrawTex()Chia-I Wu2011-10-303-0/+141
| | | | | | | | It is set to dd->DrawTex. Reviewed-by: Brian Paul <[email protected]> [olv: set dd->DrawTex in _mesa_init_driver_functions]
* i965: Remove the prepare() hook from state atoms.Eric Anholt2011-10-291-1/+0
| | | | | Reviewed-by: Kenneth Graunke <[email protected]> Acked-by: Paul Berry <[email protected]>
* i965: Remove the memcpy()ed atoms array now that everything is emit()-based.Eric Anholt2011-10-292-12/+9
| | | | | Reviewed-by: Kenneth Graunke <[email protected]> Acked-by: Paul Berry <[email protected]>
* i965: Merge brw_validate_state() and brw_upload_state() together.Eric Anholt2011-10-293-19/+5
| | | | | | | They were called back-to-back at this point. Reviewed-by: Kenneth Graunke <[email protected]> Acked-by: Paul Berry <[email protected]>
* i965: Remove state upload code for calling prepare() now that there are none.Eric Anholt2011-10-291-20/+3
| | | | | Reviewed-by: Kenneth Graunke <[email protected]> Acked-by: Paul Berry <[email protected]>
* i965: Remove some old texturing debug code.Eric Anholt2011-10-293-21/+0
| | | | | | | | | | It caught one possible bug I recall in my time working on the driver, and we haven't been setting it for non-fixed-function since the new FS backend came along. The bug it caught was likely a confusion about sampler mappings, which we have tests for these days. Reviewed-by: Kenneth Graunke <[email protected]> Acked-by: Paul Berry <[email protected]>
* i965: Finally, move the global fallbacks check to emit() time.Eric Anholt2011-10-291-1/+1
| | | | | | | | This was the last prepare() function, and it's the first state atom, so it must be ready to move. Reviewed-by: Kenneth Graunke <[email protected]> Acked-by: Paul Berry <[email protected]>
* i965: Move index buffer upload to emit() time.Eric Anholt2011-10-291-2/+2
| | | | | | | It's consumed by the brw_emit_index_buffer() code at emit() time. Reviewed-by: Kenneth Graunke <[email protected]> Acked-by: Paul Berry <[email protected]>
* i965: Do a hack job of merging VB prepare()/emit() together.Eric Anholt2011-10-291-1/+2
| | | | | | | | | I don't really want to touch this impenetrable code in this series, so just call the one function from the other, since no other atom cares about them. Reviewed-by: Kenneth Graunke <[email protected]> Acked-by: Paul Berry <[email protected]>
* i965: Move the WM input sizes calculation to emit() time.Eric Anholt2011-10-291-1/+1
| | | | | | | It's used for program compile. Reviewed-by: Kenneth Graunke <[email protected]> Acked-by: Paul Berry <[email protected]>
* i965: Move program compile to emit() time.Eric Anholt2011-10-295-9/+13
| | | | | | | Only 4 other prepare() functions are left, which don't rely on this. Reviewed-by: Kenneth Graunke <[email protected]> Acked-by: Paul Berry <[email protected]>
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