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* mesa: move _mesa_get_texstore_func() to texstore.cBrian Paul2009-09-263-75/+90
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* mesa: begin removing dependencies on gl_texture_format in texstore codeBrian Paul2009-09-261-97/+144
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* mesa: added formats.c to buildBrian Paul2009-09-262-0/+2
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* mesa: include formats.hBrian Paul2009-09-261-136/+1
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* mesa: initial check-in of new formats.[ch] filesBrian Paul2009-09-262-0/+1064
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* Merge branch 'asm-shader-rework-2'Ian Romanick2009-09-2510-2124/+3025
|\ | | | | | | | | Conflicts: src/mesa/shader/program_parse.tab.c
| * NV fp lexer: Add UP4B and UP4UB instructions that were previously missingIan Romanick2009-09-242-667/+686
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| * Merge branch 'master' into asm-shader-rework-2Ian Romanick2009-09-10173-8888/+13396
| |\ | | | | | | | | | | | | | | | | | | Conflicts: src/mesa/shader/lex.yy.c src/mesa/shader/program_parse.tab.c src/mesa/shader/program_parse.tab.h
| * | NV fp parser: Add support for condition codesIan Romanick2009-09-104-881/+1183
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Conditional write masks and the condition-code based KIL instruction are all supported. The specific behavior of KIL in the following shader may or may not match the behavior of other implementations: !!ARBfp1.0 TEMP GT; MOVC GT, fragment.texcoord[0]; KIL GT.x; END Should be it interpreted as 'KIL srcReg' or as 'KIL ccTest'? The current parser will interpret it as 'KIL srcReg'.
| * | ARB prog lexer: Add missing #include to silence compile warningIan Romanick2009-09-102-173/+175
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| * | ARB prog parser: Differentiate between used and unused names in the lexerIan Romanick2009-09-105-834/+851
| | | | | | | | | | | | | | | The lexer will return IDENTIFIER only when the name does not have an associated symbol. Otherwise USED_IDENTIFIER is returned.
| * | NV fp parser: Support instruction and TEMP / OUTPUT sizesIan Romanick2009-09-046-1506/+1463
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Adds support for declaring TEMP and OUTPUT variables as 'LONG' or 'SHORT' precision. The precision specifiers are parsed, but they are currently ignored. Some support for this may be added in the future, but neither Intel hardware nor, as far as I'm aware, Radeon hardware support multiple precisions. Also adds support for instruction precision ('X', 'H', and 'R') suffixes and instruction condition code output ('C') suffix. This results in a fairly major change to the lexer. Instructions are matched with all the possible suffix strings. The suffix string are then carved off by a context (i.e., which program mode and options are set) aware parser that converts the suffixes to bits in prog_instruction. This could have been handled in the same way _SAT was originally handled in the lexer, but it would have resulted in a very large lexer with lots of opportunity for cut-and-paste errors.
| * | ARB prog parser: Add new constructor for asm_instructionIan Romanick2009-09-043-334/+400
| | | | | | | | | | | | | | | The new constructor copies fields from the prog_instruction that the parser expects the lexer to set.
| * | NV fp parser: Add support for absolute value operator on instruction operandsIan Romanick2009-09-032-840/+942
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| * | Enable GL_NV_fragment_program_option for software renderingIan Romanick2009-09-032-0/+4
| | | | | | | | | | | | At this point the extension is not fully implemented.
| * | NV fp parser: Support new scalar constant behaviorIan Romanick2009-09-032-729/+770
| | | | | | | | | | | | | | | | | | ARBfp requires scalar constants have a '.x' suffix, but NVfp_option does not. This shows up with instructions that require a scalar parameter (e.g., COS).
| * | NV fp parser: Parse TXD instructionIan Romanick2009-09-012-842/+941
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| * | NV fp lexer: Add new opcodesIan Romanick2009-08-315-1191/+1455
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| * | NV fp: Parse 'OPTION NV_fragment_program' in ARB assembly shadersIan Romanick2009-08-312-0/+12
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| * | NV fp: Add tracking for NV_fragment_program_optionIan Romanick2009-08-312-0/+2
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* | | radeon: Fix newlines.Michal Krol2009-09-251-14/+14
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* | | Merge branch 'mesa_7_6_branch'Brian Paul2009-09-256-22/+13
|\ \ \ | | | | | | | | | | | | | | | | | | | | Conflicts: src/mesa/drivers/dri/intel/intel_clear.c
| * | | mesa: move declaration before codeVinson Lee2009-09-251-2/+3
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| * | | intel: Flush the batch when we're about to subdata into a VBO.mesa_7_6_rc1Eric Anholt2009-09-242-2/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This fixes the clears in openarena with the new metaops clear code, and the new piglit vbo-subdata-sync test. Bug #23857.
| * | | i965: Clean up some mess with the batch cache.Eric Anholt2009-09-243-18/+5
| | | | | | | | | | | | | | | | | | | | Its flagging of extra state that's already flagged by the vtbl new_batch when appropriate was confusing my tracking down of the OA clear bug.
* | | | mesa/main: Make FEATURE_convolve follow feature conventions.Chia-I Wu2009-09-245-86/+103
| | | | | | | | | | | | | | | | | | | | As shown in mfeatures.h, this allows users of convolve.h to work without knowing if the feature is available.
* | | | mesa/main: Make FEATURE_colortable follow feature conventions.Chia-I Wu2009-09-246-74/+64
| | | | | | | | | | | | | | | | | | | | As shown in mfeatures.h, this allows users of colortab.h to work without knowing if the feature is available.
* | | | mesa/main: Make FEATURE_pixel_transfer follow feature conventions.Chia-I Wu2009-09-244-56/+51
| | | | | | | | | | | | | | | | | | | | As shown in mfeatures.h, this allows users of pixel.h to work without knowing if the feature is available.
* | | | mesa/main: Add comments to mfeatures.h.Chia-I Wu2009-09-241-0/+32
| | | | | | | | | | | | | | | | The comments document the conventions that a feature may follow.
* | | | mesa: _mesa_meta_GenerateMipmap() now workingBrian Paul2009-09-241-33/+172
| | | | | | | | | | | | | | | | | | | | Handles GL_TEXTURE_1D, GL_TEXTURE_2D, GL_TEXTURE_CUBE_MAP. But GL_TEXTURE_3D and texture borders not supported yet.
* | | | mesa: remove: unused gl_vertex_program::TnlData fieldBrian Paul2009-09-242-8/+0
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* | | | Merge branch 'mesa_7_6_branch'Brian Paul2009-09-2412-28/+169
|\| | | | | | | | | | | | | | | | | | | | | | | Conflicts: src/mesa/vbo/vbo_exec_array.c
| * | | Merge branch 'mesa_7_5_branch' into mesa_7_6_branchBrian Paul2009-09-241-6/+1
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| | * | | mesa: remove glEnable(GL_DEPTH_BOUNDS_TEST_EXT) check/warningBrian Paul2009-09-241-5/+0
| | | | | | | | | | | | | | | | | | | | | | | | | At the time of the enable there may not be a Z buffer, but one may be attached to the FBO later.
| | * | | mesa: remove rgbMode check in enable_texture()Brian Paul2009-09-241-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If the currently bound FBO isn't yet validated it's possible for rgbMode to be zero so we'll lose the texture enable. This could fix some FBO rendering glitches, but I don't know of any specific instances.
| * | | | i965: Emit zero initialization for NV VP temporaries as required.Eric Anholt2009-09-245-0/+51
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is similar to what r300 does inside the driver, but I've added it as a generic option since it seems most hardware will want it. Fixes piglit nv-init-zero-reg.vpfp and nv-init-zero-addr.vpfp.
| * | | | i965: Remove assert about NV_vp now that it somewhat works.Eric Anholt2009-09-241-2/+0
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| * | | | i965: Load NV program matrices when required.Eric Anholt2009-09-241-0/+3
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| * | | | mesa: Initialize NV_vertex_program fields for the parameter lists and such.Eric Anholt2009-09-243-0/+55
| | | | | | | | | | | | | | | | | | | | This helps let drivers treat NV_vp like ARB_vp.
| * | | | intel: use default array/element buffers in intel_generate_mipmap()Brian Paul2009-09-241-0/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If there happened to be a bound VBO when intel_generate_mipmap() was called we blew up because of a bad vertex array pointer. Fixes regnumonline, bug 23859.
| * | | | mesa: replace assertion with no-op function assignmentBrian Paul2009-09-241-1/+12
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| * | | | mesa: added commentBrian Paul2009-09-241-0/+1
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| * | | | vbo: limit number of warnings to 10Brian Paul2009-09-241-18/+25
| | | | | | | | | | | | | | | | | | | | Otherwise some apps will emit tons of warnings.
* | | | | Merge branch 'mesa_7_6_branch'Pauli Nieminen2009-09-242-6/+7
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| * | | | radeon: Fix scissors for r600 KMS.Pauli Nieminen2009-09-242-6/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Radeon generic scissors code had problem that some of code was using exclusive and some inclusive bottom right corner. Only r600 driver is using exclusive coordinate so changed generic code to pass inclusive coordinate and r600 driver changes BR coordinate to be exclusive.
* | | | | Merge branch 'mesa_7_6_branch'Brian Paul2009-09-247-17/+38
|\| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Conflicts: src/mesa/drivers/dri/r600/r700_assembler.c src/mesa/drivers/dri/r600/r700_chip.c src/mesa/drivers/dri/r600/r700_render.c src/mesa/drivers/dri/r600/r700_vertprog.c src/mesa/drivers/dri/r600/r700_vertprog.h src/mesa/drivers/dri/radeon/radeon_span.c
| * | | | Merge branch 'mesa_7_5_branch' into mesa_7_6_branchBrian Paul2009-09-243-12/+18
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| | * | | swrast: add lod bias when texture samplingBrian Paul2009-09-231-2/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Mostly fixes progs/demos/lodbias when MESA_TEX_PROG=1. But the LOD still seems off by -1 or so. May be an issue with the params passed to _swrast_compute_lambda()
| | * | | mesa: don't bias LOD in shader interpreter; do it in swrastBrian Paul2009-09-231-6/+1
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| | * | | swrast: fix typo in partial derivatives parameter passingBrian Paul2009-09-231-1/+1
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