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* st/mesa: move frag depth up a level.Dave Airlie2011-12-102-19/+19
| | | | | | | This fixes the segfault, and seems to put this closer to where other properties are being set. Hopefully it still conforms. Signed-off-by: Dave Airlie <[email protected]>
* Revert "st/mesa: only resolve is number of samples is > 1"Dave Airlie2011-12-101-1/+1
| | | | | | This reverts commit 8c713626db33c40c18e24c880fe47d7948f4dcd7. Didn't mean to push this at all
* st/mesa: only resolve is number of samples is > 1Dave Airlie2011-12-101-1/+1
| | | | | | This fixes the firefox crash but I've no idea if its correct. Signed-off-by: Dave Airlie <[email protected]>
* mesa: add missing RG_INTEGER and some RED_INTEGER_EXT checks.Dave Airlie2011-12-104-0/+21
| | | | | | | | | | | This just adds the correct checks and asserts in the right places. This doesn't fix all the tests that I've sent to piglit, need to add int paths to go alongside the uint paths that don't go via float to fix it up properly. I'm not sure how much of that could be templated/shared will have a look once I write it the long way. Reviewed-by: Brian Paul <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* gallium: implement ARB_conservative_depthMarek Olšák2011-12-101-0/+19
| | | | This adds a new TGSI property to represent the GLSL layout qualifier in TGSI.
* mesa/st: Don't modify the context draw/read buffers.José Fonseca2011-12-091-64/+0
| | | | | | | | | It sets the wrong values (GL_XXX_LEFT instead of GL_XXX), and no other Mesa driver does this, given that Mesa sets the right draw/read buffers provided the Mesa visual has the doublebuffer flag filled correctly which is the case. Reviewed-by: Brian Paul <[email protected]>
* mesa,intel: use _mesa_image_offset() for PBOsnobled2011-12-082-15/+19
| | | | | | | | This avoids forming invalid pointers needlessly, which even if never dereferenced is undefined behavior. It also makes _mesa_validate_pbo_access() more comprehensible. Reviewed-by: Brian Paul <[email protected]>
* mesa: add _mesa_image_offset()nobled2011-12-082-17/+57
| | | | Reviewed-by: Brian Paul <[email protected]>
* mesa/image: assert on bad formatnobled2011-12-081-11/+9
| | | | | | | | | | | | | | | | | NULL as an error indicator is meaningless, since it will return NULL on success anyway if the caller passes in zero as the image's address and asks to calculate the offset of the first pixel. For example, _mesa_validate_pbo_access() does this. This also matches the code in the non-GL_BITMAP codepath, which already has an assert like this. v2: Per Brian Paul's review, remove the function call entirely and tighten the assert to only accept the two formats compatible with GL_BITMAP. They always have one component per pixel. Reviewed-by: Brian Paul <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* mesa/image: delete dead storenobled2011-12-081-7/+0
| | | | | | The return value here is a) always zero, b) never used. Reviewed-by: Brian Paul <[email protected]>
* glsl_to_tgsi: fix a bug in eliminate_dead_code_advanced()Bryan Cain2011-12-081-10/+8
| | | | | | | | | | | | | | | The bug, reported to me by Vadim Girlin on IRC, was causing overzealous elimination of code in parallel if statements such as the following: if (x) { r = false; } if (y) { r = true; } Before this commit, the assignment inside the first if block would be misdetected as dead code and removed.
* swrast: use malloc instead of MAX_WIDTH arrays in glCopyPixels, zoom codeBrian Paul2011-12-082-2/+18
| | | | | Reviewed-by: Jose Fonseca <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* mesa: use malloc instead of MAX_WIDTH array in glReadPixels()Brian Paul2011-12-081-9/+14
| | | | | Reviewed-by: Jose Fonseca <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* mesa: use malloc instead of MAX_WIDTH array in _mesa_convert_colors()Brian Paul2011-12-081-1/+7
| | | | | Reviewed-by: Jose Fonseca <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* mesa: add MAX_PIXEL_BYTES defineBrian Paul2011-12-082-0/+10
| | | | | | | | | In a few places we need to allocate space for some number of generic pixels. Use this new define instead of a magic number like 16 or 4 * sizeof(GLuint). Reviewed-by: Jose Fonseca <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* mesa: simplify _mesa_remove_renderbuffer()Brian Paul2011-12-081-10/+2
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* mesa: remove software-based renderbuffer code from core MesaBrian Paul2011-12-082-2039/+0
| | | | | | We're now using the functions that live in swrast. Reviewed-by: Eric Anholt <[email protected]>
* mesa/drivers: use new swrast renderbuffer functionsBrian Paul2011-12-0812-62/+74
| | | | Reviewed-by: Eric Anholt <[email protected]>
* mesa: build new s_renderbuffer.c fileBrian Paul2011-12-082-0/+2
| | | | Reviewed-by: Eric Anholt <[email protected]>
* swrast: remove core renderbuffer functions from s_renderbuffer.[ch]Brian Paul2011-12-082-267/+49
| | | | | | | We'll use the functions that live in main/ Plus, rename the remaining functions with "swrast_" prefix. Reviewed-by: Eric Anholt <[email protected]>
* swrast: add s_renderbuffer.[ch], copied from main/renderbuffer.[ch]Brian Paul2011-12-082-0/+2318
| | | | | | | Copying these files is the first step in moving the software buffer code from main/renderbuffer.c to swrast/s_renderbuffer.c Reviewed-by: Eric Anholt <[email protected]>
* mesa: remove unused functions in depthstencil.cBrian Paul2011-12-082-171/+0
| | | | Reviewed-by: Eric Anholt <[email protected]>
* mesa: make some renderbuffer functions staticBrian Paul2011-12-082-76/+48
| | | | | | | The functions to allocate software color, depth, accum, etc buffers aren't called from anywhere else. Reviewed-by: Eric Anholt <[email protected]>
* swrast: remove dead accum buffer context fieldsBrian Paul2011-12-082-10/+1
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* mesa: remove dead swrast and state tracker accum buffer codeBrian Paul2011-12-085-1049/+0
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* mesa: rewrite accum buffer supportBrian Paul2011-12-0810-15/+434
| | | | | | | | | | | | | Implemented in terms of renderbuffer mapping/unmapping and format packing/unpacking functions. The swrast and state tracker code for implementing accumulation are unused and will be removed in the next commit. v2: don't use memcpy() in _mesa_clear_accum_buffer() v3: don't allocate MAX_WIDTH arrays, be more careful with mapping flags Reviewed-by: Eric Anholt <[email protected]>
* mesa: new format_pack.c codeBrian Paul2011-12-084-0/+2596
| | | | | | This code packs colors, Z, stencil, etc. in the various mesa pixel formats. Will be used for things like glDrawPixels, glTexImage, glAccum, etc.
* mesa: remove the ctx->Driver.IsTextureResident() hookBrian Paul2011-12-084-30/+5
| | | | | | | No driver implemented this and we always returned "True" for residence queries. Reviewed-by: Ian Romanick <[email protected]>
* mesa: remove TextureMemCpy driver hookBrian Paul2011-12-084-69/+2
| | | | There's probably no reason to use a special version of memcpy() anymore.
* st/mesa: Use util_blit_pixels_writemask() for depth blits as well in ↵Henri Verbeet2011-12-081-81/+89
| | | | | | | | | st_copy_texsubimage(). This has no piglit regressions on r600g and softpipe. Signed-off-by: Henri Verbeet <[email protected]> Reviewed-by: Brian Paul <[email protected]>
* i965 gen6: Implement pass-through GS for transform feedback.Paul Berry2011-12-076-46/+208
| | | | | | | | | | | | | | | | | | | | | | In Gen6, transform feedback is accomplished by having the geometry shader send vertex data to the data port using "Streamed Vertex Buffer Write" messages, while simultaneously passing vertices through to the rest of the graphics pipeline (if rendering is enabled). This patch adds a geometry shader program that simply passes vertices through to the rest of the graphics pipeline. The rest of transform feedback functionality will be added in future patches. To make the new geometry shader easier to test, I've added an environment variable "INTEL_FORCE_GS". If this environment variable is enabled, then the pass-through geometry shader will always be used, regardless of whether transform feedback is in effect. On my Sandy Bridge laptop, I'm able to enable INTEL_FORCE_GS with no Piglit regressions. Reviewed-by: Kenneth Graunke <[email protected]> Acked-by: Eric Anholt <[email protected]>
* i965: Clean up misleading defines for DWORD 2 of URB_WRITE header.Paul Berry2011-12-075-24/+59
| | | | | | | | | | | | | R02_PRIM_END and R02_PRIM_START don't actually refer to bits in DWORD 2 of R0 (as the name, and comments in the code, would seem to indicate). Actually they refer to bits in DWORD 2 of the header for URB_WRITE messages. This patch renames the defines to reflect what they actually mean. It also addes a define URB_WRITE_PRIM_TYPE_SHIFT, which previously was just hardcoded in .c files. Reviewed-by: Kenneth Graunke <[email protected]>
* i965 gs: Clean up dodgy register re-use, at the cost of a few MOVs.Paul Berry2011-12-072-65/+111
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Prior to this patch, in the Gen4 and Gen5 GS, we used GRF 0 (called "R0" in the code) as a staging area to prepare the message header for the FF_SYNC and URB_WRITE messages. This cleverly avoided an unnecessary MOV operation (since the initial value of GRF 0 contains data that needs to be included in the message header), but it made the code confusing, since GRF 0 could no longer be relied upon to contain its initial value once the GS started preparing its first message. This patch avoids confusion by using a separate register ("header") as the staging area, at the cost of one MOV instruction. Worse yet, prior to this patch, the GS would completely overwrite the contents of GRF 0 with the writeback data it received from a completed FF_SYNC or URB_WRITE message. It did this because DWORD 0 of the writeback data contains the new URB handle, and that neds to be included in DWORD 0 of the next URB_WRITE message header. However, that caused the rest of the message header to be corrupted either with undefined data or zeros. Astonishingly, this did not produce any known failures (probably by dumb luck). However, it seems really dodgy--corrupting FFTID in particular seems likely to cause GPU hangs. This patch avoids the corruption by storing the writeback data in a temporary register and then copying just DWORD 0 to the header for the next message. This costs one extra MOV instruction per message sent, except for the final message. Also, this patch moves the logic for overriding DWORD 2 of the header (which contains PrimType, PrimStart, PrimEnd, and some other data that we don't care about yet). This logic is now in the function brw_gs_overwrite_header_dw2() rather than in brw_gs_emit_vue(). This saves one MOV instruction in brw_gs_quads() and brw_gs_quad_strip(), and paves the way for the Gen6 GS, which will need more complex logic to override DWORD 2 of the header. Finally, the function brw_gs_alloc_regs() contained a benign bug: it neglected to increment the register counter when allocating space for the "temp" register. This turned out not to have any effect because the temp register wasn't used on Gen4 and Gen5, the only hardware models (so far) to require a GS program. Now, all the registers allocated by brw_gs_alloc_regs() are actually used, and properly accounted for. Reviewed-by: Kenneth Graunke <[email protected]>
* i965 gen6: Allocate URB space for GSPaul Berry2011-12-073-12/+63
| | | | | | | | | | | | | | When the GS is not in use, the entire URB space is available for the VS. When the GS is in use, we split the URB space 50/50. The 50/50 split is probably not optimal--we'll probably want tune this for performance in a future patch. For example, in most situations, it's probably worth allocating more than 50% of the space to the VS, since VS space is used for vertex caching. But for now this is good enough. Based on previous work by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* i965: Set the maximum number of GS URB entries on Sandybridge.Kenneth Graunke2011-12-071-0/+2
| | | | | | | | | | | We never filled this in before because we didn't care. I'm skeptical these are correct; my sources indicate that both the VS and GS # of entries are 256 on both GT1 and GT2. I'm also loathe to change it and break stuff. Reviewed-by: Paul Berry <[email protected]>
* i965: Only convert if/else to conditional adds prior to Gen6.Paul Berry2011-12-071-2/+28
| | | | | | | | | | | | | | | | | | | | | | | | | Normally when outputting instructions in SPF (single program flow) mode, we convert IF and ELSE instructions to conditional ADD instructions applied to the IP register. On platforms prior to Gen6, flow control instructions cause an implied thread switch, so this is a significant savings. However, according to the SandyBridge PRM (Volume 4 part 2, p79): [Errata DevSNB{WA}] - When SPF is ON, IP may not be updated by non-flow control instructions. So we have to disable this optimization on Gen6. On later platforms, there is no significant benefit to converting flow control instructions to ADDs, so for the sake of consistency, this patch disables the optimization on later platforms too. The reason we never noticed this problem before is that so far we haven't needed to use SPF mode on Gen6. However, later patches in this series will introduce a Gen6 GS program which uses SPF mode. Reviewed-by: Kenneth Graunke <[email protected]>
* i965 gs: Remove unnecessary mapping of key->primitive.Paul Berry2011-12-072-16/+7
| | | | | | | | | | | | | Previously, GS generation code contained a lookup table that mapped primitive types POLYGON, TRISTRIP, and TRIFAN to TRILIST, mapped LINESTRIP to LINELIST, and left all other primitives unchanged. This was silly, because we never generate a GS program for those primitive types anyhow. This patch removes the unnecessary lookup table. Reviewed-by: Eric Anholt <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* mesa: Track changes to transform feedback state.Paul Berry2011-12-072-1/+9
| | | | | | | | | | | This patch adds a new bit to the ctx->NewState bitfield, _NEW_TRANSFORM_FEEDBACK, to track state changes that affect ctx->TransformFeedback. This bit can be used by driver back-ends to avoid expensive recomputations when transform feedback state has not been modified. Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* i965: Set Ivybridge's is_array SURFACE_STATE bit.Kenneth Graunke2011-12-071-1/+2
| | | | | | | | | | | Fixes piglit tests fbo-array, fbo-depth-array, fbo-generatemipmap-array, and array-texture, as well as the array variants of my new textureSize and texelFetch tests. Not a candidate for 7.11 because EXT_texture_array wasn't supported. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* i965: Return BRW_DEPTHBUFFER_D32_FLOAT as the null-depthbuffer format.Kenneth Graunke2011-12-071-0/+3
| | | | | | | | | | | Fixes many crashes on Ivybridge due to upload_sf_state calling brw_depthbuffer_format without an actual depth buffer. This was a recent regression on master. +3992 piglits on Ivybridge. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* intel: Update comment about how depth/stencil miptrees are handled.Eric Anholt2011-12-071-6/+18
| | | | | | | This evolved over several commits, and I also wanted to document some new information about how we handle formats. Reviewed-by: Chad Versace <[email protected]>
* intel: Rely on miptree mapping for all renderbuffer maps.Eric Anholt2011-12-072-202/+21
| | | | | | | Now that all RBs have miptrees, and miptree mapping covered these last two code paths, consistently use them. Reviewed-by: Chad Versace <[email protected]>
* intel: Add support for LLC-cached reads of X-tiled miptrees using a blit.Eric Anholt2011-12-072-0/+83
| | | | | | | This mimics the MapRenderbuffer code, and should improve the performance of glGetTexImage(). v2: Fix broken error handling.
* intel: Handle MapRenderbuffer of fake packed depth/stencil using miptree maps.Eric Anholt2011-12-071-138/+2
| | | | | This gets the same performance win as the miptree maps did, and removes a pile of code duplication.
* intel: Track miptrees for fake packed depth/stencil renderbuffers.Eric Anholt2011-12-071-0/+10
| | | | | | | | | | | | | Right now the fake packed d/s RBs are creating two sub-renderbuffers with their own storage, and the hardware setup and the mapping code have been explicitly referencing them. By setting miptrees on them, we'll be able to make our renderbuffer code for fake packed depth/stencil more consistent with all our other renderbuffers. The interesting new behavior here is that there is now a mt with a non-depthstencil format (X8Z24) that has a stencil_mt field associated. This looks like it should be safe, and we'll need to be able to do this for floating point depth/stencil as well.
* intel: Make the fake packed depth/stencil mappings use a cached temporary.Eric Anholt2011-12-072-121/+129
| | | | | | | | | | | | | | | | | | | | | | Before, we had an uncached read of S8 to untile, then a RMW (so uncached penalty) of the packed S8Z24 to store the value, then the consumer would uncached read that once per pixel. If data was written to the map, we would then have to uncached read the written data back out and do the scatter to the tiled S8 buffer (also uncached access penalties, since WC couldn't actually combine). So 3 or 5 uncached accesses per pixel in the ROI (and we we were ignoring the ROI, so it was the whole image). Now we get an uncached read of S8 to untile, and an uncached read of Z. The consumer gets to do cached accesses. Then if data was written, we do streaming Z writes (WC success), and scattered S8 tiling writes (uncached penalty). So 2 or 3 uncached accesses per pixel in the ROI. This should be a performance win, to the extent that anybody is doing software accesses of packed depth/stencil buffers. Reviewed-by: Chad Versace <[email protected]>
* intel: Make intel_region_map return void *.Eric Anholt2011-12-072-4/+4
| | | | | | | | We don't gripe about void * arithmetic for our driver, and this prevents silly casting when assigning the result of mapping to non-byte types. Reviewed-by: Chad Versace <[email protected]>
* intel: Move separate-stencil s8 mapping logic to intel_miptree_map.Eric Anholt2011-12-072-113/+112
| | | | | | | We're going to want to reuse this logic in mapping of fake packed miptrees wrapping separate depth/stencil miptrees. Reviewed-by: Chad Versace <[email protected]>
* intel: Move the gtt-particular texture mapping logic to a helper function.Eric Anholt2011-12-071-49/+71
| | | | | | | This code will be incrementally moving to a model like intel_fbo.c's renderbuffer mapping with helper functions, as I move that code here. Reviewed-by: Chad Versace <[email protected]>
* intel: Make mapping of texture slices track the region of interest.Eric Anholt2011-12-072-5/+51
| | | | | | | This will be used for things like packed depth/stencil temporaries and making LLC-cached temporary mappings using blits. Reviewed-by: Chad Versace <[email protected]>
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