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* i965/cfg: Add functions to get first and last non-CF instructions.Matt Turner2014-11-061-0/+74
| | | | Reviewed-by: Jason Ekstrand <[email protected]>
* glsl: Add infrastructure for "hidden" uniforms.Kenneth Graunke2014-11-062-2/+5
| | | | | | | | | | | | | | | In the compiler, we'd like to generate implicit uniforms for internal use. These should not be visible via the GL uniform introspection API. To support that, we add a new ir_variable::how_declared value of ir_var_hidden, and plumb that through to gl_uniform_storage. v2 (idr): Fix some memory management issues in move_hidden_uniforms_to_end. The comment block on the function has more details. Signed-off-by: Kenneth Graunke <[email protected]> Signed-off-by: Ian Romanick <[email protected]>
* mesa: Add SSE 4.1 optimisation for glDrawElements.Timothy Arceri2014-11-066-5/+152
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Makes use of SSE 4.1 to speed up compute of min and max elements. Callgrind cpu usage results from pts benchmarks: Openarena 0.8.8: 3.67% -> 1.03% UrbanTerror: 2.36% -> 0.81% V5: - actually make use of the optimisation in android (Emil Velikov) - set a better array size limit for using SSE and added TODO V4: - fixed bugs with incrementing pointer and updating counters V3: - Removed sse_minmax.c from Makefile.sources - handle the first few values without SSE until the pointer is aligned and use _mm_load_si128 rather than _mm_loadu_si128 - guard the call to the SSE code better at build time V2: - removed GL* types - use _mm_store_si128() rather than _mm_store_ps() - add runtime check for SSE - use aligned attribute for local mix/max - bunch of tidyups Reviewed-by: Juha-Pekka Heikkila <[email protected]> Reviewed-by: Matt Turner <[email protected]> Signed-off-by: Timothy Arceri <[email protected]>
* i965: Remove non-existent vertical strides from array.Matt Turner2014-11-061-1/+1
| | | | | | These never existed, as far as I can tell. Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Convert stride/width/execution size macros into enums.Matt Turner2014-11-061-28/+33
| | | | Reviewed-by: Kenneth Graunke <[email protected]>
* i965/fs: Remove force uncompressed stack.Matt Turner2014-11-063-27/+0
| | | | | | Last use was in shader_time. Reviewed-by: Jason Ekstrand <[email protected]>
* i965/fs: Use execution size of 1 for some shader_time operations.Matt Turner2014-11-061-1/+1
| | | | | | The ADDs depended on dispatch_width, which really isn't what we wanted. Reviewed-by: Jason Ekstrand <[email protected]>
* i965/fs: Use mov(4) instructions to read timestamp.Matt Turner2014-11-061-5/+4
| | | | We only want fields 0-2.
* Releasing a surfaceless EGL context doesn't release underlying DRI context.Alexandros Frantzis2014-11-061-2/+6
| | | | | | | | | | | | | | | | | | driUnbindContext() checks for valid drawables before calling the driver unbind function. In case of Surfaceless contexts, the drawables are always Null and we end up not releasing the underlying DRI context. Moving the call to the driver function before the drawable validity checks fixes things. Steps to trigger this bug are following: - create surfaceless context and make it current - make some other context current - {another thread} destroy surfaceless context - make another context current Signed-off-by: Alexandros Frantzis <[email protected]> Signed-off-by: Kalyan Kondapally <[email protected]> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=74563
* mesa: Silence unused parameter warning in check_context_limits in non-debug ↵Ian Romanick2014-11-051-0/+2
| | | | | | | | | | builds ../../src/mesa/main/context.c: In function 'check_context_limits': ../../src/mesa/main/context.c:733:41: warning: unused parameter 'ctx' [-Wunused-parameter] Signed-off-by: Ian Romanick <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Fix sampler state pointer adjustment for nonconst samplersChris Forbes2014-11-051-1/+1
| | | | | | | | | | | This started hitting an assertion recently. Only affects Haswell (Ivybridge doesn't support this meddling with the sampler state pointer, and ARB_gpu_shader5 is not enabled yet on Broadwell) 14 Piglits crash->pass. Signed-off-by: Chris Forbes <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Re-enable Z16 on Gen8+.Kenneth Graunke2014-11-041-0/+7
| | | | | | | | | | | | | Improves performance in GLBenchmark 2.7 TRex by 3.88889% +/- 0.336383% (n=80) at 1280x720 on Broadwell GT3. Together with the previous patch, it improves performance by 5.42738% +/- 0.541971% (n=10) at 1920x1080. Note that without the PMA stall fix, this would instead decrease performance by 22%. v2: Update comment (noticed by Kristian Høgsberg). Signed-off-by: Kenneth Graunke <[email protected]>
* i965: Implement the PMA stall fix.Kenneth Graunke2014-11-044-0/+180
| | | | | | | | | | | | | | | | | | | Certain non-promoted depth cases typically incur stalls. In very specific cases, we can enable a workaround which improves performance. Improves performance in GLBenchmark 2.7 TRex by 1.17762% +/- 0.448765% (n=75) at 1280x720 on Broadwell GT3. Haswell has this feature as well, but we can't currently write registers from userspace batches (and we'd incur additional software batch scanning overhead as well), so we haven't enabled it. Broadwell allows us to write CACHE_MODE_1. Backporters beware: the formula and flushing incantation differs between Haswell and Broadwell. v2: Move pma_stall_bits from brw->state to brw itself (requested by Kristian Høgsberg). Signed-off-by: Kenneth Graunke <[email protected]>
* i965: Add #defines for Broadwell HiZ workarounds in CACHE_MODE_1.Kenneth Graunke2014-11-041-0/+6
| | | | | | This patch adds macros needed for the HiZ PMA stall optimization. Signed-off-by: Kenneth Graunke <[email protected]>
* i965: Update compaction code to handle Skylake like Cherryview.Kenneth Graunke2014-11-031-4/+4
| | | | | | | | | Matt requested this in review feedback on the original patch, which I completely missed when pushing this series. Kristian also made this change, but I grabbed the wrong version of the patch. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* mesa: Don't call _mesa_ClipControl from glPopAttrib when unsupported.Kenneth Graunke2014-11-031-1/+2
| | | | | | | Otherwise, calling glPopAttrib on drivers that don't support ARB_clip_control gives you a GL error, which is surprising at best. Signed-off-by: Kenneth Graunke <[email protected]>
* i965: Disable fast color clears on Skylake for now.Kenneth Graunke2014-11-031-1/+1
| | | | | | | | We're not programming the clear values yet, so this won't work. This patch should be (effectively) reverted eventually. Signed-off-by: Kenneth Graunke <[email protected]>
* i965/skl: Use new MOCS for SKLKristian Høgsberg2014-11-036-17/+33
| | | | | | | | | | | | On Skylake, the MOCS bits are an index into a table of 63 different, configurable cache configurations. As for previous GENs, we only care about WB and WT, which are available in the documented default set. Define SKL_MOCS_WB and SKL_MOCS_WT to the indices for those configucations and use those for the Skylake MOCS values. Signed-off-by: Kristian Høgsberg <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Anuj Phogat <[email protected]>
* i965/skl: Implement workaround for VF Invalidate issueJordan Justen2014-11-031-0/+9
| | | | | | | Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Kristian Høgsberg <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Anuj Phogat <[email protected]>
* i965/skl: Update Viewport Z Clip Test Enable bits for Skylake.Kenneth Graunke2014-11-032-2/+10
| | | | | | | | | Skylake has separate controls for enabling the Z Clip Test for the near and far planes. For now, maintain the legacy behavior by setting both. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Kristian Høgsberg <[email protected]> Reviewed-by: Anuj Phogat <[email protected]>
* i965/skl: Emit extra zeros in 3DSTATE_DS on Skylake.Kenneth Graunke2014-11-031-10/+5
| | | | | | | | | Skylake's 3DSTATE_DS packet has a few more fields; we don't support domain shaders yet though. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Kristian Høgsberg <[email protected]> Reviewed-by: Anuj Phogat <[email protected]>
* i965/skl: Init instructions compaction tables for SKLKristian Høgsberg2014-11-031-0/+1
| | | | | | | They are the same as for BDW, so just add a case for SKL to the init switch. Signed-off-by: Kristian Høgsberg <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965/skl: Add fast clear resolve rect multipliers for SKLKristian Høgsberg2014-11-031-2/+5
| | | | | | | | SKL updates the resolve rectangle scaling factors again. Signed-off-by: Kristian Høgsberg <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Anuj Phogat <[email protected]>
* i965/skl: Always emit 3DSTATE_BINDING_TABLE_POINTERS_* on Skylake.Kenneth Graunke2014-11-031-1/+1
| | | | | | | | | | | On SKL, 3DSTATE_CONSTANT_* command is not committed until we give the corresponding 3DSTATE_BINDING_TABLE_POINTERS_* command. If we fail to do so, the constant buffers wont be read and push constants will be wrong. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Kristian Høgsberg <[email protected]> Reviewed-by: Anuj Phogat <[email protected]>
* i965/skl: Allocate 16 DWords for SURFACE_STATE on Skylake.Kenneth Graunke2014-11-031-1/+1
| | | | | | | | | Otherwise they overlap and horrible things happen. All the new DWords are for fast color clear values, which we don't do yet. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Kristian Høgsberg <[email protected]> Reviewed-by: Anuj Phogat <[email protected]>
* i965/skl: Refactor surface state allocation.Kenneth Graunke2014-11-031-10/+16
| | | | | | | | | | We will need to allocate more DWords on Skylake. v2: Don't mark brw_context parameter const. It's modified. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Kristian Høgsberg <[email protected]> Reviewed-by: Anuj Phogat <[email protected]>
* i965/skl: Emit extra zeros in STATE_BASE_ADDRESS on Skylake.Kenneth Graunke2014-11-031-2/+11
| | | | | | | | | Skylake introduces a new base address for a feature we don't yet expose. Setting these to 0 should be safe. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Kristian Høgsberg <[email protected]> Reviewed-by: Anuj Phogat <[email protected]>
* i965/skl: Update stencil reference handling for Skylake.Kenneth Graunke2014-11-033-6/+28
| | | | | | | | | Skylake uploads the stencil reference values in DW3 of the 3DSTATE_WM_DEPTH_STENCIL packet, rather than in COLOR_CALC_STATE. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Kristian Høgsberg <[email protected]> Reviewed-by: Anuj Phogat <[email protected]>
* i965/skl: Set mask bits in PIPELINE_SELECT on Skylake.Kenneth Graunke2014-11-031-1/+1
| | | | | | | | | | | Skylake has some extra bits in PIPELINE_SELECT, none of which are interesting for a 3D driver. In order to selectively change them, it also introduces new "mask bits" in 15:8. We care about the "Pipeline Selection" bits (1:0), so set the mask to 0x3. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Kristian Høgsberg <[email protected]> Reviewed-by: Anuj Phogat <[email protected]>
* i965/skl: Set max OpenGL version the same as gen7/8Jordan Justen2014-11-031-0/+1
| | | | | | | Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Kristian Høgsberg <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Anuj Phogat <[email protected]>
* i965/skl: Update 3DSTATE_SBE for Skylake.Damien Lespiau2014-11-032-2/+34
| | | | | | | | | | | | | This commands has seen the addition of 2 dwords that allow to specify which channels of which attributes need to be forwarded to the fragment shader. v2: Rebase forward a year (done by Ken). Signed-off-by: Damien Lespiau <[email protected]> Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Kristian Høgsberg <[email protected]> Reviewed-by: Anuj Phogat <[email protected]>
* i965/fs: Don't compute_to_mrf() on Gen >= 7.Matt Turner2014-11-031-0/+4
| | | | | | No differences in shader-db on Haswell (Gen 7.5). Reviewed-by: Kenneth Graunke <[email protected]>
* i965/chv: Increase VS and GS thread countsBen Widawsky2014-11-021-2/+2
| | | | | | | | AFAICT the number of threads is 80, not 70. I am not sure if Ken knows something I do not. Signed-off-by: Ben Widawsky <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* mesa: protect the debug state with a mutexChia-I Wu2014-10-302-47/+126
| | | | | | | | | | We are about to change mesa to spawn threads for deferred glCompileShader and glLinkProgram, and we need to make sure those threads can send compiler warnings/errors to the debug output safely. Signed-off-by: Chia-I Wu <[email protected]> Reviewed-by: Brian Paul <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* util: add _mesa_strtod and _mesa_strtofChia-I Wu2014-10-303-22/+1
| | | | | | | | | Both core mesa and glsl have their own wrappers for strtof_l. Merge and move them to util/. They are compiled with a C++ compiler so that we can make them thread-safe in a following commit. Signed-off-by: Chia-I Wu <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* mesa/gallium: Signal _NEW_TRANSFORM from glClipControl.Mathias Fröhlich2014-10-302-13/+6
| | | | | | | | | This removes the need for the gallium rasterizer state to listen to viewport changes. Thanks to Marek Olšák <[email protected]>. Reviewed-by: Marek Olšák <[email protected]> Signed-off-by: Mathias Froehlich <[email protected]>
* Revert "i965/compaction: Disable compaction on SNB temporarily."Matt Turner2014-10-291-6/+0
| | | | | | | | This reverts commit cabc93c5adc9ea62be901621eff5ce4cb9574791. Mark thinks the failures on the SNB GT2 in the lab are actually because of faulty hardware, not instruction compaction. The GT1 didn't see any problems after changes to the compaction code.
* i965/vec4: Perform CSE on MAD instructions with final arguments switched.Matt Turner2014-10-291-1/+5
| | | | Reviewed-by: Kenneth Graunke <[email protected]>
* i965/fs: Perform CSE on MAD instructions with final arguments switched.Matt Turner2014-10-291-1/+5
| | | | | | | | Multiplication is commutative. instructions in affected programs: 48314 -> 47954 (-0.75%) Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Rename brw_vec4_gs.[ch] to brw_gs.[ch].Kenneth Graunke2014-10-295-5/+4
| | | | | | | | | | | These source files support actual geometry shaders, so using "gs" for the name makes a lot of sense. We're going to be adding SIMD8 geometry shader support as well, at which point "vec4_gs" will be a misnomer. Signed-off-by: Kenneth Graunke <[email protected]> Acked-by: Matt Turner <[email protected]> Acked-by: Jason Ekstrand <[email protected]> Acked-by: Iago Toral Quiroga <[email protected]>
* i965: Rename brw_gs{,_emit}.[ch] to brw_ff_gs{,_emit}.[ch].Kenneth Graunke2014-10-295-5/+5
| | | | | | | | | | | | | | | | The brw_gs.[ch] and brw_gs_emit.c source files contain code for emulating fixed-function unit functionality (VF primitive decomposition or SOL) using the GS unit. They do not contain code to support proper geometry shaders. We've taken to calling that code "ff_gs" (see brw_ff_gs_prog_key, brw_ff_gs_prog_data, brw_context::ff_gs, brw_ff_gs_compile, brw_ff_gs_prog). So it makes sense to make the filenames match. Signed-off-by: Kenneth Graunke <[email protected]> Acked-by: Matt Turner <[email protected]> Acked-by: Jason Ekstrand <[email protected]> Acked-by: Iago Toral Quiroga <[email protected]>
* i965: Rename intel_bufferobj_* functions to match GL and DD hooks.Kenneth Graunke2014-10-291-65/+64
| | | | | | | | | | | | | | | | | | | | The GL functions and driver hooks use corresponding names---for example, glMapBufferRange and Driver.MapBufferRange. But our implementation was called "intel_bufferobj_map_range," which has the words "map" and "buffer" swapped, as well as randomly adding "obj." FlushMappedBufferRange was even trickier: it ordered the words 3, "obj", 1, 2, 4: intel_bufferobj_flush_mapped_range. Even though the old names were consistent, I always had trouble rearranging the jumble of words when searching for a function, and it took a few tries to eventually land there. The new names match the word order of GL and the driver hooks; FlushMappedBufferRange is simply brw_flush_mapped_buffer_range. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Kristian Høgsberg <[email protected]>
* mesa: Fix order of errors for glDrawTransformFeedbackStreamChris Forbes2014-10-291-5/+5
| | | | | | | | | | | | | | | | | | | The OpenGL 4.0 core profile specification, section 2.17.3 Transform Feedback Draw Operations says: "The error INVALID_VALUE is generated if <stream> is greater than or equal to the value of MAX_VERTEX_STREAMS. ... The error INVALID_OPERATION is generated if EndTransformFeedback has never been called while the object named by id was bound." Fixes the piglit test: ARB_transform_feedback3/arb_transform_feedback3-draw_using_invalid_stream_index (with the test itself fixed to eliminate an unrelated failure) Signed-off-by: Chris Forbes <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* st/mesa: use PIPE_BIND_DISPLAY_TARGET when checking for sRGB capabilityBrian Paul2014-10-281-1/+2
| | | | | | | When we're checking if the framebuffer is sRGB capable, call is_format_supported() with the PIPE_BIND_DISPLAY_TARGET flag. Reviewed-by: Charmaine Lee <[email protected]>
* Revert "st/mesa: set MaxUnrollIterations = 255"Marek Olšák2014-10-281-2/+1
| | | | | | | | | | | | | | | | | | This reverts commit 20836c81851e0df29a8ee9c86e5e5388738c840b. 255 is a huge number. If you have a loop with 255 iterations, unrolling it will exceed the SM3 instruction limit. Let's use the default again. The comment about a SM3 limit doesn't make sense. For SM3, we generally want 32 (default) or a lower number due to the SM3 instruction limit, which is 512 instructions. For SM4, we can try higher numbers if needed, but some shaders can end up being pretty huge and shader compilation can take more time. This fixes a shader compile failure on R500/SM3. Reported on IRC. Cc: 10.2 10.3 <[email protected]> Reviewed-by: Brian Paul <[email protected]>
* mesa: Add support for the GL_KHR_context_flush_control extensionNeil Roberts2014-10-284-2/+14
| | | | | | | | | | | | | | The GL side of this extension just provides an accessor via glGetIntegerv for the value of GL_CONTEXT_RELEASE_BEHAVIOR so it is trivial to implement. There is a constant on the context for the value of the enum which is initialised to GL_CONTEXT_RELEASE_BEHAVIOR_FLUSH. The extension is always enabled because it doesn't need any driver interaction to retrieve the value. If the value of the enum is anything but FLUSH then _mesa_make_current will now refrain from calling _mesa_flush. This should only affect drivers that explicitly change the enum to a non-default value. Reviewed-by: Ian Romanick <[email protected]>
* i965/fs: Don't set dependency hints on instructions with spilled destinationsJason Ekstrand2014-10-271-0/+8
| | | | Reviewed-by: Kenneth Graunke <[email protected]>
* i965/fs: Make scratch write instructions use the correct execution sizeJason Ekstrand2014-10-271-1/+1
| | | | Reviewed-by: Kristian Høgsberg <[email protected]>
* i965/fs: Use correct spill offsetsJason Ekstrand2014-10-271-6/+5
| | | | | | | | | | | | Different platforms require the offset to be in different units. However, the generator fixes all of this up for us and only requires an offset in bytes. Previously, we were getting this wrong all over the place. Some computed/used it correctly as bytes while others treated the offset as whole registers or computed it as bytes or bytes*2 in SIMD16 mode. This commit cleans all this up and makes us properly treat it as bytes everywhere. Reviewed-by: Kristian Høgsberg <[email protected]>
* i965: Use the spill destination for the message header on GEN >= 7Jason Ekstrand2014-10-271-6/+13
| | | | Reviewed-by: Kristian Høgsberg <[email protected]>
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