summaryrefslogtreecommitdiffstats
path: root/src/mesa
Commit message (Collapse)AuthorAgeFilesLines
* mesa: Initialize image units to default state on context creation.Francisco Jerez2015-05-043-0/+21
| | | | | | | This is the required initial image unit state according to "Table 23.45. Image State (state per image unit)" of the OpenGL 4.3 specification. Reviewed-by: Matt Turner <[email protected]>
* mesa: Implement image uniform queries.Francisco Jerez2015-05-041-1/+3
| | | | Reviewed-by: Matt Turner <[email protected]>
* mesa: Validate original image internal format rather than derived mesa format.Francisco Jerez2015-05-041-3/+3
| | | | | | | | | | | This matches what _mesa_BindImageTextures() does. The derived image format (gl_texture_image::TexFormat) isn't necessarily equivalent to the internal format of the texture image. If a forbidden internal format has been specified we need to mark the image unit as invalid as required by the spec, regardless of the derived format. Fixes the "invalid" ARB_shader_image_load_store piglit test. Reviewed-by: Matt Turner <[email protected]>
* mesa: Call _mesa_test_texobj_completeness() before using _MaxLevel in image ↵Francisco Jerez2015-05-041-3/+4
| | | | | | | | | | validation. gl_texture_object::_MaxLevel doesn't have any meaningful value until _mesa_test_texobj_completeness() has been run. Fixes the "level" ARB_shader_image_load_store piglit test. Reviewed-by: Matt Turner <[email protected]>
* mesa: Add support for binding a buffer texture to a shader image unit.Francisco Jerez2015-05-041-31/+42
| | | | Reviewed-by: Matt Turner <[email protected]>
* mesa: Add extern "C" guards to shaderimage.h to allow inclusion from C++ code.Francisco Jerez2015-05-041-0/+8
| | | | Reviewed-by: Matt Turner <[email protected]>
* mesa: Export shader image format to mesa format conversion function.Francisco Jerez2015-05-042-5/+12
| | | | | | | This function will be useful for back-ends to translate an image internal format as specified in GLSL code into a mesa format. Reviewed-by: Matt Turner <[email protected]>
* swrast: Fix rgba_draw_pixels with GL_COLOR_INDEXIago Toral Quiroga2015-05-041-3/+26
| | | | | | | | | | | | | | When we implemented the format conversion rewrite we forgot to handle GL_COLOR_INDEX here, which needs special handling. Fixes the following piglit test: bin/gl-1.0-drawpixels-color-index -auto -fbo Buzilla: https://bugs.freedesktop.org/show_bug.cgi?id=90213 Tested-by: Juha-Pekka Heikkila <[email protected]> Reviewed-by: Juha-Pekka Heikkila <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* i965: Add memory fence opcode.Francisco Jerez2015-05-046-0/+87
| | | | | Acked-by: Kenneth Graunke <[email protected]> Reviewed-by: Topi Pohjolainen <[email protected]>
* i965: Add typed surface access opcodes.Francisco Jerez2015-05-049-0/+261
| | | | | Acked-by: Kenneth Graunke <[email protected]> Reviewed-by: Topi Pohjolainen <[email protected]>
* i965: Add untyped surface write opcode.Francisco Jerez2015-05-049-0/+81
| | | | | Reviewed-by: Topi Pohjolainen <[email protected]> Acked-by: Kenneth Graunke <[email protected]>
* i965: Reorder sources of the untyped atomic opcode.Francisco Jerez2015-05-044-6/+6
| | | | | | | | | | | | This is consistent with the untyped surface read opcode. From now on all typed and untyped surface access opcodes will follow the same pattern: src[0] will be the message payload, src[1] will be the surface index and src[2] will be a control immediate (atomic operation for atomic opcodes and number of vector components for surface read and write opcodes). Reviewed-by: Topi Pohjolainen <[email protected]> Acked-by: Kenneth Graunke <[email protected]>
* i965: Pass the number of components as a source of the untyped surface read ↵Francisco Jerez2015-05-044-6/+10
| | | | | | | opcode. Reviewed-by: Topi Pohjolainen <[email protected]> Acked-by: Kenneth Graunke <[email protected]>
* i965/vec4: Add support for untyped surface message sends from GRF.Francisco Jerez2015-05-043-16/+14
| | | | | | | | | This doesn't actually enable untyped surface message sends from GRF yet, the upcoming atomic counter and image intrinsic lowering code will. Reviewed-by: Topi Pohjolainen <[email protected]> Acked-by: Kenneth Graunke <[email protected]>
* i965: Don't request untyped atomic writeback message if the destination is null.Francisco Jerez2015-05-042-2/+3
| | | | | Reviewed-by: Topi Pohjolainen <[email protected]> Acked-by: Kenneth Graunke <[email protected]>
* i965: Simplify generator code for untyped surface messages.Francisco Jerez2015-05-044-87/+18
| | | | | | | | | The generate_untyped_*() methods do nothing useful other than calling the corresponding function from brw_eu_emit.c. The calls to brw_mark_surface_used() will go away too in a future commit. Reviewed-by: Topi Pohjolainen <[email protected]> Acked-by: Kenneth Graunke <[email protected]>
* i965: Fix the untyped surface opcodes to deal with indirect surface access.Francisco Jerez2015-05-044-82/+99
| | | | | | | | | | | | Change brw_untyped_atomic() and brw_untyped_surface_read() to take the surface index as a register instead of a constant and to use brw_send_indirect_message() to emit the indirect variant of send with a dynamically calculated message descriptor. This will be required to support variable indexing of image arrays for ARB_shader_image_load_store. Acked-by: Kenneth Graunke <[email protected]> Reviewed-by: Topi Pohjolainen <[email protected]>
* i965: Upload atomic buffer state for compute shadersJordan Justen2015-05-024-1/+29
| | | | | Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965/cs: Emit MEDIA_STATE_FLUSH after WALKERJordan Justen2015-05-022-0/+6
| | | | | Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965/cs: Implement brw_emit_gpgpu_walkerJordan Justen2015-05-022-1/+51
| | | | | | | | | | | | | Tested on Ivybridge, Haswell and Broadwell. v2: * Use SET_FIELD. (Ken) * Use simd_size / 16 to support SIMD8/16/32. Ken suggested that we might be able to do it arithmetically rather than just supporting SIMD8 and SIMD16 with a conditional. Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965/state: Emit pipeline select when changing pipelinesJordan Justen2015-05-024-6/+36
| | | | | Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Implement DispatchCompute() back-endPaul Berry2015-05-024-0/+127
| | | | | | | brw_emit_gpgpu_walker will be implemented in a subsequent patch. Reviewed-by: Jordan Justen <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* main/cs: Implement front end code for glDispatchCompute().Paul Berry2015-05-021-1/+19
| | | | | Reviewed-by: Jordan Justen <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* mesa/cs: Add DispatchCompute() to driver function table.Paul Berry2015-05-021-0/+7
| | | | | Reviewed-by: Jordan Justen <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965/cs: Emit state base addressJordan Justen2015-05-022-1/+3
| | | | | Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965/fs: Add CS shader time supportJordan Justen2015-05-024-2/+33
| | | | | Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965/cs: Upload brw_cs_stateJordan Justen2015-05-024-0/+109
| | | | | | | | v3: * Add defines. Misc cleanup suggestions. (Ken) Signed-off-by: Jordan Justen <[email protected]> Acked-by: Kenneth Graunke <[email protected]>
* i965/cs: Support CS program precompileJordan Justen2015-05-024-0/+41
| | | | | Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Add brw_setup_tex_for_precompile. Use in VS, GS & FS.Jordan Justen2015-05-023-24/+24
| | | | | | Suggested-by: Kristian Høgsberg <[email protected]> Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965/cs: Emit compute shader code and upload programsJordan Justen2015-05-023-0/+212
| | | | | | | | | | | | v2: * Don't bother checking for 'gen > 5' (krh) * Populate sampler data in key (krh) v3: * Drop no8 support, and simplify code in several places (Ken) Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965/cs: Set invocation counts based on max_cs_threadsJordan Justen2015-05-021-0/+24
| | | | | | | | | | | | | | For ES, we set the max counts based on SIMD8, which is currently accurate. For desktop GL, we set the max counts based on SIMD16, which can fail in some cases where a SIMD16 program is not currently supported. Therefore, this value is not currently accurate, but will work fine in many cases, and lets us run more test cases. Eventually we want to always be able to generate a SIMD16 program. Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965/cs: Add max_cs_threadsJordan Justen2015-05-024-1/+14
| | | | | | | | Add values for gen7 & gen8. These are the number threads in a subslice. Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Remove comment about chv device numbers being preliminaryJordan Justen2015-05-021-3/+0
| | | | | Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965/fs: Support compute programs in fs_visitorJordan Justen2015-05-024-3/+93
| | | | | | | | | | v2: * Clean out some unneeded code copied from run_fs (krh) * Always use NIR * Split shader time out into a separate commit Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965/cache: Add support for CS in program state cacheJordan Justen2015-05-024-0/+54
| | | | | | Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Kristian Høgsberg <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965/cs: Add brw_cs_prog_data, brw_cs_prog_key and brw_context::cs.Paul Berry2015-05-022-0/+62
| | | | | | | | | | | | [email protected]: * Added brw_cs_prog_key structure * Added brw_cs_prog_data::dispatch_grf_start_reg_16 * Added brw_cs_prog_data::local_size * Added brw_cs_prog_data::simd_size Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Kristian Høgsberg <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965/cs: Add generator support for CS_OPCODE_CS_TERMINATEJordan Justen2015-05-022-0/+36
| | | | | | | | | | v2: * Don't rely on brw_eu* to generate the send instruction. We now generate the send here, and drop the "i965/cs: Add support for the SEND message that terminates a CS thread" brw_eu* patch. Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965/cs: Mark g0 as used by CS_OPCODE_CS_TERMINATEJordan Justen2015-05-021-0/+4
| | | | | Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965/fs: Add emit_cs_terminate to emit CS_OPCODE_CS_TERMINATEJordan Justen2015-05-022-0/+23
| | | | | | | | | | | | v2: * Do more work at the visitor level. g0 is loaded and sent to the generator now. v3: * Use Ken's comment explaining g0 usage Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965/cs: Add CS_OPCODE_CS_TERMINATEJordan Justen2015-05-022-0/+7
| | | | | Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965/cs: Add BRW_NEW_CS_PROG_DATA and BRW_CACHE_CS_PROGJordan Justen2015-05-023-0/+6
| | | | | | Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Kristian Høgsberg <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Add an INTEL_DEBUG=cs option.Paul Berry2015-05-022-2/+4
| | | | | | | | | At the moment it's not wired up to anything. Later patches will hook it up to the compute shader back-end. Reviewed-by: Jordan Justen <[email protected]> Reviewed-by: Kristian Høgsberg <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* mesa/cs: Add compute support to update_program().Paul Berry2015-05-021-0/+21
| | | | | | Reviewed-by: Jordan Justen <[email protected]> Reviewed-by: Kristian Høgsberg <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* mesa/cs: Update program.c for compute shaders.Paul Berry2015-05-021-0/+3
| | | | | | Reviewed-by: Jordan Justen <[email protected]> Reviewed-by: Kristian Høgsberg <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* mesa/cs: Add inline functions for dealing with compute shaders.Paul Berry2015-05-021-0/+22
| | | | | | Reviewed-by: Jordan Justen <[email protected]> Reviewed-by: Kristian Høgsberg <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965/cs: Add BRW_NEW_COMPUTE_PROGRAM state flag.Paul Berry2015-05-022-0/+9
| | | | | | | | | Also add code to brw_upload_state to set it when the compute program changes. Reviewed-by: Jordan Justen <[email protected]> Reviewed-by: Kristian Høgsberg <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965/fs: Strip trailing constant zeroes in sample messagesNeil Roberts2015-05-012-0/+50
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If a send message is emitted with a message length that is less than required for the message then the remaining parameters default to zero. We can take advantage of this to save a register when a shader passes constant zeroes as the final coordinates to the sample function. I think this might be useful for GLES applications that are using 2D textures to simulate 1D textures. On Skylake it will be useful for shaders that do texelFetch(tex,something,0) which I think is fairly common. This helps more on Skylake because in that case the order of the instruction operands are u,v,lod,r which is good for 2D textures whereas before they were u,lod,v,r which is only good for 1D textures. On Haswell: total instructions in shared programs: 8535730 -> 8533261 (-0.03%) instructions in affected programs: 236968 -> 234499 (-1.04%) helped: 1174 On Skylake: total instructions in shared programs: 10345646 -> 10341237 (-0.04%) instructions in affected programs: 293011 -> 288602 (-1.50%) helped: 1218 Reviewed-by: Matt Turner <[email protected]> v2: Applied suggestions by Kenneth Graunke: - Only apply on Gen5+ - Apply to all texture opcodes, not just TEX and TXF. Moved the optimisation into the loop as suggested by Matt Turner. Fix the array index when there is a header.
* i965/skl: Force the exec size to 8 when initing header for SIMD4x2Neil Roberts2015-05-012-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | On Gen9+ there needs to be a header when sampling using SIMD4x2. The header is set up by copying from the g0 register. Commit 07c571a39f tried to fix this mov instruction to always use an exec size of 8 because previously it was incorrectly using 4. It did this by casting the type of the destination register to vec8. This was done because there is code in brw_set_dest to guess the exec size based on the width of the dest register. However I misunderstood how this works because it is actually only used when the width is less than 8. That means the patch actually changed it to use the default exec size which on SIMD16 would be 16 and the MOV would clobber over the first register in the send message. This patch makes it additionally set the default exec size to 8. This is similar to how the message is set up in fs_generator::generate_tex. I think this wasn't picked up by any Piglit tests because we don't have any fragment shaders that hit this code path so nothing was using SIMD16. However the patch caused failures in deqp tests. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=90153 Reviewed-by: Matt Turner <[email protected]> Tested-by: Tapani Pälli <[email protected]>
* i965: Unhardcode a few more stage names and abbreviations.Kenneth Graunke2015-04-302-11/+5
| | | | | | | | | | | | | | | The stage_abbrev and stage_name fields in backend_visitor provide what we need without any additional effort. It also means we'll get the right names for compute shaders, SIMD8 geometry shaders, and both kinds of tessellation shaders. This does unfortunately change the capitalization of the stage abbreviation in the INTEL_DEBUG=optimizer output filenames. It doesn't seem worth adding code to handle, though. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Matt Turner <[email protected]> Reviewed-by: Anuj Phogat <[email protected]>
* mesa: add GL_OES_EGL_syncMarek Olšák2015-04-301-0/+1
| | | | | This is an empty extension whose presence means that EGL sync objects can be used with ES contexts.
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-27 22:41:18 +0000