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* i965: Add a pass to the FS to split virtual GRFs to float channels.Eric Anholt2010-10-142-2/+116
* i965: Update the live interval when coalescing regs.Eric Anholt2010-10-141-0/+4
* i965: Set class_sizes[] for the aligned reg pair class.Eric Anholt2010-10-141-0/+1
* Drop the "neutral" tnl moduleKristian Høgsberg2010-10-145-120/+9
* Revert "i965: fallback lineloop on sandybridge for now"Zhenyu Wang2010-10-141-7/+0
* i965: Fix GS hang on SandybridgeZhenyu Wang2010-10-144-14/+46
* i965: Add support for rescaling GL_TEXTURE_RECTANGLE coords to new FS.Eric Anholt2010-10-131-5/+40
* mesa: Clean up various 'unused parameter' warnings in shaderapiIan Romanick2010-10-131-6/+14
* mesa: Clean up two 'comparison between signed and unsigned' warningsIan Romanick2010-10-131-2/+2
* mesa: Refactor validation of shader targetsIan Romanick2010-10-131-10/+33
* mesa: Silence unused variable warningIan Romanick2010-10-131-0/+1
* x11: fix breakage from gl_config::visualType removalBrian Paul2010-10-133-5/+6
* Drop GLcontext typedef and use struct gl_context insteadKristian Høgsberg2010-10-13780-5680/+5677
* Drop GLframebuffer typedef and just use struct gl_framebufferKristian Høgsberg2010-10-1353-127/+126
* Rename GLvisual and __GLcontextModes to struct gl_configKristian Høgsberg2010-10-1389-178/+165
* gl: Remove unused GLcontextModes fieldsKristian Høgsberg2010-10-138-48/+7
* Get rid of GL/internal/glcore.hKristian Høgsberg2010-10-137-10/+131
* tdfx: Silence unused variable warning on non-debug builds.Vinson Lee2010-10-121-0/+1
* r300: Silence uninitialized variable warning.Vinson Lee2010-10-121-0/+1
* mesa: reformatting, comments, code movementBrian Paul2010-10-121-78/+99
* mesa: remove assertion w/ undeclared variable texelBytesBrian Paul2010-10-121-1/+0
* st/mesa: enable stencil shader export extension if supportedDave Airlie2010-10-131-0/+4
* glsl: add support for shader stencil exportDave Airlie2010-10-132-0/+2
* st/mesa: use shader stencil export to accelerate shader drawpixels.Dave Airlie2010-10-134-57/+158
* st/mesa: add option to choose a texture format that we won't render to.Dave Airlie2010-10-133-8/+22
* mesa: improve texstore for 8/24 formats and add texstore for S8.Dave Airlie2010-10-131-119/+144
* mesa: add support for FRAG_RESULT_STENCIL.Dave Airlie2010-10-131-2/+3
* i965: Don't rebase the index buffer to min 0 if any arrays are in VBOs.Eric Anholt2010-10-124-11/+15
* intel: Allow CopyTexSubImage to InternalFormat 3/4 textures, like RGB/RGBA.Eric Anholt2010-10-121-0/+2
* i965: Fix missing "break;" in i2b/f2b, and missing AND of CMP result.Eric Anholt2010-10-121-2/+3
* glsl: Fix incorrect assertionIan Romanick2010-10-121-1/+1
* mesa: Validate assembly shaders when GLSL shaders are usedIan Romanick2010-10-121-12/+40
* ir_to_mesa: assorted clean-ups, const qualifiers, new commentsBrian Paul2010-10-121-14/+45
* nouveau: Get larger push buffers.Francisco Jerez2010-10-122-2/+2
* dri/nouveau: Initialize tile_flags when allocating a render target.Francisco Jerez2010-10-122-6/+14
* i965: Always use the new FS backend on gen6.Eric Anholt2010-10-111-2/+7
* i965: Fix gen6 pixel_[xy] setup to avoid mixing int and float src operands.Eric Anholt2010-10-111-6/+15
* i965: Don't compute-to-MRF in gen6 VS math.Eric Anholt2010-10-111-7/+15
* i965: Expand uniform args to gen6 math to full registers to get hstride == 1.Eric Anholt2010-10-111-0/+25
* i965: Don't compute-to-MRF in gen6 math instructions.Eric Anholt2010-10-111-0/+16
* i965: Add a couple of checks for gen6 math instruction limits.Eric Anholt2010-10-111-0/+26
* i965: Don't consider gen6 math instructions to write to MRFs.Eric Anholt2010-10-111-17/+38
* intel_extensions: Add ability to set GLSL version via environmentChad Versace2010-10-111-1/+18
* r200: revalidate after radeon_update_renderbuffersDaniel Vetter2010-10-113-3/+10
* i965: Compute to MRF in the new FS backend.Eric Anholt2010-10-112-0/+124
* i965: Give the FB write and texture opcodes the info on base MRF, like math.Eric Anholt2010-10-112-38/+48
* i965: Give the math opcodes information on base mrf/mrf len.Eric Anholt2010-10-112-12/+57
* i965: Move FS backend structures to a header.Eric Anholt2010-10-115-363/+407
* i965: Reduce register interference checks for changed FS_OPCODE_DISCARD.Eric Anholt2010-10-111-5/+2
* i965: Split FS_OPCODE_DISCARD into two steps.Eric Anholt2010-10-111-9/+23
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