summaryrefslogtreecommitdiffstats
path: root/src/mesa
Commit message (Expand)AuthorAgeFilesLines
...
* | | intel: minor code clean-upsBrian Paul2009-09-141-11/+8
* | | intel: fix renderbuffer map/unmap regressionBrian Paul2009-09-141-14/+14
* | | intel: remove unneeded driver function assignmentsBrian Paul2009-09-141-5/+0
* | | mesa/st: remove dead commentKeith Whitwell2009-09-141-7/+0
* | | st/mesa: convert to new tgsi_ureg mechanism for shader emitKeith Whitwell2009-09-143-983/+625
* | | mesa: remove unused SATURATE_PLUS_MINUS_ONE flagKeith Whitwell2009-09-122-3/+0
* | | i965: Move OPCODE_DDX/DDY to brw_wm_emit.c and make it actually work.Eric Anholt2009-09-115-102/+126
* | | r600: fix texcoords from constantsAndre Maasikas2009-09-111-40/+52
* | | Revert "r600: support tex coords from constants"Alex Deucher2009-09-111-17/+45
* | | r600: support tex coords from constantsAlex Deucher2009-09-111-45/+17
* | | r600: enable caching of vertex programsAndre Maasikas2009-09-116-62/+110
* | | i965: Enable loops in the VS.Eric Anholt2009-09-101-15/+38
* | | mesa: nicer vertex setupBrian Paul2009-09-101-128/+138
* | | st/mesa: use st_context() helperBrian Paul2009-09-101-17/+17
* | | Merge branch 'mesa_7_6_branch'Brian Paul2009-09-106-52/+108
|\| |
| * | intel: disable intel_stencil_drawpixels() for nowBrian Paul2009-09-101-0/+16
| * | Fix merge failIan Romanick2009-09-101-13/+0
| * | mesa: need to set all stencil bits to 0 before setting the 1 bitsBrian Paul2009-09-101-0/+9
| * | Merge branch 'mesa_7_5_branch' into mesa_7_6_branchIan Romanick2009-09-102-1/+6
| |\|
| | * intel: add B43 chipset supportZhenyu Wang2009-09-102-1/+6
| * | i965: Fix relocation delta for WM surfaces.Eric Anholt2009-09-101-1/+1
| * | mesa: in texenvprogram code, only do saturation when really needed.Brian Paul2009-09-101-8/+53
| * | radeon: Change debugging code to use macros instead of inline functions.Pauli Nieminen2009-09-102-43/+27
| * | radeon: Add more verbose error message for failed command buffer.Pauli Nieminen2009-09-091-1/+3
* | | intel: Don't forget to map the depth read buffer in spans.Eric Anholt2009-09-101-22/+28
* | | r300: enable rb3d_discard_src_pixel_lte_threshold for more chips on dri2Alex Deucher2009-09-101-5/+1
* | | r300: add full support for two sided stencil on r5xx for dri2Alex Deucher2009-09-104-4/+46
* | | mesa: fix cut&paste typosMathias Frohlich2009-09-101-4/+4
* | | i965: Fix relocation delta for WM surfaces.Eric Anholt2009-09-091-1/+1
* | | i965: fix an overlooked merge conflictBrian Paul2009-09-091-13/+0
* | | r600: check if textures are actually enabled before submissionAlex Deucher2009-09-092-56/+64
* | | Merge branch 'mesa_7_6_branch'Brian Paul2009-09-096-2/+28
|\| |
| * | Merge branch 'mesa_7_5_branch' into mesa_7_6_branchBrian Paul2009-09-095-1/+24
| |\|
| | * mesa: bump version to 7.5.2Brian Paul2009-09-081-3/+3
| | * i965: fix incorrect test for vertex position attributeBrian Paul2009-09-083-1/+4
| | * i965: Fix warnings in intel_pixel_read.c.Eric Anholt2009-09-041-0/+4
| | * intel: Also get the DRI2 front buffer when doing front buffer reading.Eric Anholt2009-09-044-1/+29
| | * intel: Update Mesa state before span setup in glReadPixels.Eric Anholt2009-09-043-3/+13
| | * intel: Move intel_pixel_read.c to shared for use with i965.Eric Anholt2009-09-042-306/+307
| | * i965: Add missing state dependency of sf_unit on _NEW_BUFFERS.Eric Anholt2009-09-041-2/+4
| | * intel: Align cubemap texture height to its padding requirements.Eric Anholt2009-09-041-0/+10
| | * intel: Align untiled region height to 2 according to 965 docs.Eric Anholt2009-09-041-0/+7
| | * i965: Fix source depth reg setting for FSes reading and writing to depth.Eric Anholt2009-09-043-1/+5
| | * i965: Respect CondSwizzle in OPCODE_IF.Eric Anholt2009-09-041-1/+21
| | * i965: asst clean-ups, etc in brw_vs_emit()Brian Paul2009-09-041-11/+10
| | * i965: Emit conditional code updates as required for GLSL VS if statements.Eric Anholt2009-09-041-0/+13
| | * i965: Spell "conditional" correctly.Eric Anholt2009-09-043-15/+15
| | * i965: Fix RECT shadow sampling by not losing the other texcoords.Eric Anholt2009-09-041-1/+5
| | * i965: Assert that the offset in the VBO is below the VBO size.Eric Anholt2009-09-041-0/+14
| | * i965: Even if no VS inputs are set, still load some amount of URB as required.Eric Anholt2009-09-041-0/+11
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-27 21:12:08 +0000