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* i965/fs: Implement new ir_unop_u2i and ir_unop_i2u opcodes.Kenneth Graunke2011-06-292-0/+10
| | | | | | | | | | No MOV is necessary since signed/unsigned integers share the same bit-representation; it's simply a question of interpretation. In particular, the fs_reg::imm union shouldn't need updating. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Ian Romanick <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* ir_to_mesa: "Support" u2f, i2u, and u2i operations by doing nothing.Kenneth Graunke2011-06-291-1/+3
| | | | | | | | | Mesa IR actually stores all numbers as floating point, so this is totally a farce, but we may as well keep it going. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Ian Romanick <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* i965/gen7: Add missing ! to brw->gs.prog_active assertion.Kenneth Graunke2011-06-291-1/+1
| | | | | | | | | A typo in commit c173541d9769 accidentally removed the !. It's supposed to assert that there is _not_ an active GS program. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=38762 Signed-off-by: Kenneth Graunke <[email protected]>
* mesa: bump version to 7.12 (devel)Brian Paul2011-06-291-2/+2
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* st/mesa: s/tex_usage/bindings/ in st_format.hBrian Paul2011-06-291-1/+1
| | | | Just be consistent with the .c file.
* st/mesa: Use correct internal targetEmil Velikov2011-06-291-2/+2
| | | | | | | | | | | Commit 1a339b6c(st/mesa: prefer native texture formats when possible) introduced two new arguments to the st_choose_format() functions. This patch fixes the order and passes the correct internal_target rather than GL_NONE NOTE: This is a candidate for the 7.11 branch Signed-off-by: Emil Velikov <[email protected]> Signed-off-by: Brian Paul <[email protected]>
* st/mesa: fix overwriting gl_format with pipe_format since 9d380f48Andre Maasikas2011-06-291-2/+2
| | | | | | fixes assert later on in texcompress2/r600g Signed-off-by: Brian Paul <[email protected]>
* st-api: Rework how drawables are invalidated v3.Thomas Hellstrom2011-06-293-50/+73
| | | | | | | | | | | | | | | The api and the state tracker manager code as well as the state tracker code assumed that only a single context could be bound to a drawable. That is not a valid assumption, since multiple contexts can bind to the same drawable. Fix this by making it the state tracker's responsibility to update all contexts binding to a drawable Note that the state trackers themselves don't use atomic stamps on frame-buffers. Multiple context rendering to the same drawable should be protected by the application. Signed-off-by: Thomas Hellstrom <[email protected]>
* i965: Reissue PIPELINE_POINTERS and BINDING_TABLE_POINTERS on SBA change.Eric Anholt2011-06-286-12/+55
| | | | | This was a requirement we didn't run into until we started using STATE_BASE_ADDRESS for instruction data.
* i965/gen6: Fix scissors using invalid STATE_BASE_ADDRESS.Eric Anholt2011-06-281-2/+2
| | | | | | | | The scissor state was incorrectly in a .prepare function instead of .emit, so the packet would end up in the batch before the STATE_BASE_ADDRESS. It appears that this doesn't actually hurt, as the scissor address gets dereferenced according to the current SBA at draw time.
* i965: step message register allocationBen Widawsky2011-06-271-5/+5
| | | | | | | | The system routine requires m0 be reserved for saving off architectural state. Moved the allocation to start at 2 instead of 0. Signed-off-by: Ben Widawsky <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* Revert "Fix 24bpp software rendering"Brian Paul2011-06-253-89/+4
| | | | This reverts commit c0c0bb6cb140825f5bab3c40c0c9c0ec575fbc76.
* i965/gen5: Fix grf_used calculation for 16-wide.Eric Anholt2011-06-241-5/+4
| | | | | | | | | | If we happened to allocate a texture result (or other vector) to the highest hardware register slot, and we were in 16-wide, we would under-count the registers used and potentially wrap around to g0 if that allocation crossed a 16-register block boundary. Bad rendering and hangs ensued. Tested-by: Ian Romanick <[email protected]>
* i965: fix mask used to write to clip distance registers when gen>6Paul Berry2011-06-241-1/+1
| | | | | | | | | | | | | In gen6 and above, clip distances 0-3 are written to message register 3's xyzw components, and 4-7 to message register 4's xyzw components. Therefore when when writing the clip distances we need to examine the lower 2 bits of the clip distance index to see which component to write to. emit_vertex_write() was examining the lower 3 bits, causing clip distances 4-7 not to be written correctly. Fixes piglit test vs-clip-vertex-01.shader_test
* intel: Fix workaround for _mesa_update_framebufferChad Versace2011-06-241-3/+5
| | | | | | | | | | | In intel_draw_buffer, there exists a workaround to prevent _mesa_update_framebuffer from creating a swrast depth wrapper when using separate stencil. This commit fixes the workaround, which was incomplete for s8z24 texture renderbuffers. Fixes fbo-blit-d24s8 on gen5 with separate stencil manually enabled. Signed-off-by: Chad Versace <[email protected]>
* intel: Change framebuffer validation criteriaChad Versace2011-06-241-10/+3
| | | | | | | | Since all infrastructure is now in place to support packed depth/stencil renderbuffers when using separate stencil, there is no need for special cases when separate stencil is enabled. Signed-off-by: Chad Versace <[email protected]>
* intel: In intel_update_wrapper, support s8z24 textures when using separate ↵Chad Versace2011-06-241-6/+35
| | | | | | | | | | stencil Also, in order to coerce intel_update_tex_wrapper_regions() to allocate the hiz region, alter intel_update_tex_wrapper_regions() to examine the renderbuffer format instead of the texture image format. Signed-off-by: Chad Versace <[email protected]>
* intel: Factor region updates out of intel_update_wrapperChad Versace2011-06-241-0/+18
| | | | | | | | | | | ... and into new function intel_update_tex_wrapper_regions. This prevents code duplication in the next commit. Also add a note explaining that the hiz region is broken for mipmapped depth textures. Signed-off-by: Chad Versace <[email protected]>
* intel: During glTexImage, allocate renderbuffers for faking s8z24 texturesChad Versace2011-06-241-0/+62
| | | | | | | | | ... when using separate stencil. Define function intel_tex_image_x8z24_create_renderbuffers and call it in intelTexImage after the miptree has been created and filled with data. Signed-off-by: Chad Versace <[email protected]>
* intel: Declare some functions in intel_fbo.c as non-staticChad Versace2011-06-242-2/+14
| | | | | | | | | | ... because they will be needed by intel_tex_image_s8z24_create_renderbuffers. Redeclared functions are: intel_alloc_renderbuffer_storage intel_renderbuffer_set_draw_offsets Signed-off-by: Chad Versace <[email protected]>
* intel: Change signature of intel_create_wrapped_renderbufferChad Versace2011-06-242-22/+12
| | | | | | | | | | Redeclare as non-static because intel_tex_image_s8z24_create_renderbuffers will use it. Remove the 'wrapper' parameter, because there is no wrapper for intel_texture_image.depth_rb and stencil_rb. Signed-off-by: Chad Versace <[email protected]>
* intel: Perform gather on s8z24 texture images during glGetTexImageChad Versace2011-06-241-0/+8
| | | | Signed-off-by: Chad Versace <[email protected]>
* intel: Define functions intel_texture_s8z24_scatter/gatherChad Versace2011-06-241-0/+70
| | | | | | | ... which copy the stencil bits between intel_image->depth_rb and intel_image->stencil_rb. Signed-off-by: Chad Versace <[email protected]>
* intel: Add fields to intel_texture for faking s8z24 with separate stencilChad Versace2011-06-243-12/+40
| | | | | | | | Add the fields depth_rb and stencil_rb, and put hooks in place to release the renderbuffers in intelFreeTextureImageData and intelTexImage. Signed-off-by: Chad Versace <[email protected]>
* st/mesa: add PIPE_FORMAT_R8G8B8A8_UNORM as the first RGBA format.Stéphane Marchesin2011-06-241-1/+1
| | | | | | | Otherwise we can end up creating RGBA render targets (which are BGRA on the hardware), and then we bind them as RGBA textures (which are RGBA on the hardware). This generates software fallbacks every time we bind the frame as a texture.
* mesa: don't allocate memory in _mesa_unpack_depth_span if we don't need itMarek Olšák2011-06-241-7/+7
| | | | Reviewed-by: Brian Paul <[email protected]>
* mesa: fix a memory leak in _mesa_unpack_depth_spanMarek Olšák2011-06-241-0/+1
| | | | | | NOTE: This is a candidate for the 7.10 branch. Reviewed-by: Brian Paul <[email protected]>
* mesa: fix texstore of DEPTH24_STENCIL8 if srcFormat is STENCIL_INDEXMarek Olšák2011-06-241-3/+6
| | | | NOTE: This is a candidate for the 7.10 branch.
* mesa: remove unused function _mesa_new_depthstencil_renderbufferMarek Olšák2011-06-242-26/+0
| | | | Reviewed-by: Brian Paul <[email protected]>
* st/mesa: fix pipe_get_transfer() call in fallback_copy_texsubimage()Brian Paul2011-06-241-1/+2
| | | | | | | | | | | | | Commit 1a339b6c71ebab6e1a64f05b2e133022d3bbcd15 caused us to take a different path through the glCopyTexSubImage() code. The pipe_get_transfer() call neglected to pass the texture's level, face and slice info. So we were always transferring from the 0th mipmap level even when the source renderbuffer was a non-zero mipmap level in a texture. Fixes https://bugs.freedesktop.org/show_bug.cgi?id=38649 NOTE: This is a candidate for the 7.10 branch.
* i965: Make the brw_format_for_mesa_format table static const.Eric Anholt2011-06-241-1/+1
| | | | | | | | | Once again, assuming the compiler is clever works out so poorly. The generated code initialized the structure on the stack, then did a lookup into it. This was a performance regression from 70c6cd39bd9396b0d3f9e84df41fd8bef1f26cc4. Reviewed-by: Ian Romanick <[email protected]>
* i965: Don't bother telling swrast_setup about state updates until fallback.Eric Anholt2011-06-243-1/+4
| | | | Reviewed-by: Ian Romanick <[email protected]>
* i965: Don't bother telling tnl about state updates unless we fall back.Eric Anholt2011-06-244-2/+18
| | | | | | This was sucking up 1% of the CPU on 3DMMES. Reviewed-by: Ian Romanick <[email protected]>
* i965: Reuse existing program data when a new compiled program matches.Eric Anholt2011-06-242-20/+82
| | | | | | | | | | | | | | | | | | It's common in applications just before the advent of EXT_separate_shader_objects to have multiple linked shaders with the same VS or FS. While we aren't detecting those at the Mesa level, we can detect when our compiled output happens to match an existing compiled program. This patch was created after noting the incredible amount of compiled program data generated by Heroes of Newerth. It reduces the program data in use at the start menu (replayed by apitrace) from 828kb to 632kb, and reduces CACHE_NEW_WM_PROG state flagging by 3/4. It doesn't impact our rate of hardware state changes yet, because things depending on CACHE_NEW_WM_PROG also depend on BRW_NEW_FRAGMENT_PROGRAM which is still being flagged. Reviewed-by: Ian Romanick <[email protected]>
* st/mesa: fix all_varyings_in_vbos() regressionBrian Paul2011-06-241-1/+17
| | | | | Fixes regression from d631c19db47181129811080bfa772b210d762d4d. See http://bugs.freedesktop.org/show_bug.cgi?id=38626
* Fix 24bpp software renderingMarc Pignat2011-06-243-4/+89
| | | | | | | This patch add the support for 24bpp in the dri/swrast implementation. Signed-off-by: Marc Pignat <[email protected]> Signed-off-by: Brian Paul <[email protected]>
* dri/r200: properly spell current_atom.Stéphane Marchesin2011-06-231-1/+1
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* dri/r200: rename __atom to current_atom.Stéphane Marchesin2011-06-231-3/+3
| | | | __atom is defined by gcc when the atom compile optimizations are used.
* mesa: fix incorrect error stringBrian Paul2011-06-231-1/+1
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* st/mesa: fix format selection regressionBrian Paul2011-06-231-3/+7
| | | | | | | Note all gallium formats are supported by Mesa so disable them. Fixes regression from 1a339b6c71ebab6e1a64f05b2e133022d3bbcd15. See https://bugs.freedesktop.org/show_bug.cgi?id=38602
* vbo: Don't discount stride == 0 for testing all varyings in VBOs.Eric Anholt2011-06-231-2/+1
| | | | | | | | | | | | | | | | | In fixed function, stride == 0 (e.g. glColor4f() outside of the draw call) would get turned into uniform inputs, which is why it was ignored originally in this test. For shaders, drivers end up seeing a need to upload stride == 0 data, and get confused by needing to upload when vbo_all_varyings_in_vbos() returned true. In the 965 driver case, it wouldn't bother to compute the min/max index, and uploaded nothing if the min/max wasn't known. We've talked about removing the ff stride=0-into-uniforms code, so this check shouldn't be missed once that's gone. Fixes ARB_vertex_buffer_object/mixed-immediate-and-vbo Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=37934 Reviewed-by: Brian Paul <[email protected]>
* vbo: Don't bother checking for stride == 0 for "any varying in a VBO".Eric Anholt2011-06-231-2/+1
| | | | | | | We would still want to consider that data as being in a VBO even if we managed to produce this case, which as far as I know we can't. Reviewed-by: Brian Paul <[email protected]>
* i965/gen6: Add a couple more packets to the nonpipelined workaround list.Eric Anholt2011-06-231-0/+6
| | | | | | | All the packets chosen before came from grepping the pdf for nonpipelined, and these two came from grepping for non.pipelined. We could stand a review by looking at all packets emitted and identifying what kind they are.
* intel: Implement DRIimageExtension::dupImageBenjamin Franzke2011-06-231-1/+26
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* st/mesa: use a helper for st_framebuffer creationChia-I Wu2011-06-231-18/+29
| | | | | | In st_api_make_current, we would like to reuse the exising st_framebuffer if possible. Use a helper function to make the code clearer.
* st/mesa: prefer native texture formats when possible.Stéphane Marchesin2011-06-224-8/+101
| | | | | | If possible, we want to match the hardware format to what the app uses. By doing so, we avoid the need for pixel conversions and therefore greatly speed up texture uploads.
* r600c: add missing bank tiling case for evergreenAlex Deucher2011-06-221-0/+3
| | | | Signed-off-by: Alex Deucher <[email protected]>
* mesa: comments and 80-column wrappingBrian Paul2011-06-221-6/+21
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* mesa: update comments in update_program_enables()Brian Paul2011-06-221-1/+4
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* mesa: update/fix comments in update_program()Brian Paul2011-06-221-17/+16
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