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* mesa: remove gl_dlist_node::next pointer to reduce dlist memory useBrian Paul2013-12-041-8/+10
| | | | | | | Now, sizeof(gl_dlist_node)==4 even on 64-bit systems. This can halve the memory used by some display lists on 64-bit systems. Reviewed-by: Ian Romanick <[email protected]>
* mesa: begin reducing memory used by display listsBrian Paul2013-12-041-172/+252
| | | | | | | | | | | | | | | | | This is a first step in reducing memory used by display lists on 64-bit systems. On 64-bit systems, the gl_dlist_node union type is 8 bytes because of the 'data' and 'next' fields. This causes every display list node/token to occupy 8 bytes instead of 4 as originally designed. This basically doubles the memory used by some display lists on 64-bit systems. The fix is to remove the 64-bit 'data' and 'next' pointer fields from the union and instead store them as a pair of 32-bit values. Easily done with a few helper functions. The next patch will take care of the 'next' field. Reviewed-by: Ian Romanick <[email protected]>
* mesa: modified _mesa_align_free() to accept NULL pointerSiavash Eliasi2013-12-047-32/+26
| | | | | | | | | | | So that it acts like ordinary free(). This lets us remove a bunch of if statements where the function is called. v2: - Avoiding compile error on MSVC and possible warnings on other compilers. - Added comment regards passing NULL pointer being safe. Reviewed-by: Brian Paul <[email protected]>
* mesa: don't leak performance monitors on context destroyIlia Mirkin2013-12-043-0/+23
| | | | | | Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Cc: "10.0" <[email protected]>
* i965: Fix BRW_BATCH_STRUCT to specify RENDER_RING, not UNKNOWN_RING.Kenneth Graunke2013-12-031-2/+2
| | | | | | | | | | | | | | | | I missed this in the boolean -> enum conversion. C cheerfully casts false -> 0 -> UNKNOWN_RING. On Gen4-5, this causes the render ring prelude hook to get called in the middle of the batch, which is crazy. BRW_BATCH_STRUCT is not used on Gen6+. Fixes regressions since 395a32717df494353703f3581edcd3ba380f16d6 ("i965: Introduce an UNKNOWN_RING state."). Fixes "fips -v glxgears" on Ironlake. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* Revert "i965: Move brw_emit_query_begin() to the render ring prelude."Kenneth Graunke2013-12-032-7/+3
| | | | | | | | | | | | This reverts commit a4bf7f6b6e612626c4e4fc21507ac213a7ba4b00. It breaks occlusion queries on Gen4-5. Doing this right will likely require larger changes, which should be done at a future date. Some Piglit tests still passed due to other bugs; fixing those revealed this problem. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* i965: Fix OACONTROL assertion failures on Ironlake.Kenneth Graunke2013-12-031-4/+8
| | | | | | | | | | | | | | | I guarded half of the callers to start/stop_oa_counters with generation checks, but missed the other half (which were added later). OACONTROL doesn't exist on Ironlake, so we better not write it. Also, there's no need---Ironlake's performance counters are always running. This patch moves the generation checks into start/stop_oa_counters, rather than requiring the caller to do them. Fixes assertion failures in Piglit's AMD_performance_monitor/measure. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* mesa: resolve typo DTXn/DXTnEmil Velikov2013-12-031-1/+1
| | | | | Reviewed-by: Kenneth Graunke <[email protected]> Signed-off-by: Emil Velikov <[email protected]>
* i965: Add extra-alignment for non-msrt fast color clear for all hw (v2)Chad Versace2013-12-031-24/+11
| | | | | | | | | | | | | | | | | | | | | | The BSpec states that the aligment for the non-msrt clear rectangle must be doubled; the BSpec does not restricit the workaround to specific hardware. Commit 9a1a67b applied the workaround to Haswell GT3. Commit 8b659ce expanded the workaround to all Haswell variants. This commit expands it to all hardware. No Piglit regressions on Ivybridge 0x0166. No fixes either. I know no Ivybridge nor Baytrail bug related to this workaround. However, the BSpec says the extra alignment is required, so let's do it. v2: Apply to all hardware, not just gen7. CC: "9.2, 10.0" <[email protected]> CC: Anuj Phogat <[email protected]> Reviewed-by: Paul Berry <[email protected]> Signed-off-by: Chad Versace <[email protected]>
* st/mesa: implement layered framebuffer clear for the clear_with_quad fallbackMarek Olšák2013-12-032-16/+43
| | | | Same approach as in u_blitter.
* gallium: add support for AMD_vertex_shader_layerMarek Olšák2013-12-032-0/+11
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* st/mesa: add support for layered framebuffers and consolidate codeMarek Olšák2013-12-036-93/+99
| | | | | | | | | This is a subset of geometry shaders. It's all about setting first_layer and last_layer correctly. Also some code between st_render_texture and update_framebuffer_state is consolidated. It doesn't use rtt_level and derives the level from dimensions instead as the code in st_atom_framebuffer.c did.
* mesa: expose AMD_vertex_shader_layer in the core profile onlyMarek Olšák2013-12-031-1/+1
| | | | | | | It needs glFramebufferTexture, which isn't available in the compatibility profile. Reviewed-by: Ian Romanick <[email protected]>
* i965: Skip the register write check on Broadwell.Kenneth Graunke2013-12-021-1/+5
| | | | | | | | | MI_STORE_REGISTER_MEM has to take a 48-bit address, so the existing code doesn't work. But supposedly Broadwell has a register whitelist and just works out of the box anyway, so there's no need to check. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* i965: Fix texture border color on Broadwell.Kenneth Graunke2013-12-021-1/+11
| | | | | | | | | | | | The Gen7 sampler state code still works. Increasing the alignment to 64 bytes makes bit 5 zero, which is good because it's now reserved. Since we don't use the new filter bits, we can leave those as zero too, which means we don't need to update the code to update the pointer. (We probably should anyway, for clarity, but alas, another day.) Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* i965: Don't use MACH for integer multiplies on Gen8+.Kenneth Graunke2013-12-022-2/+2
| | | | | | | | | | | The documentation is really hard to follow, but apparently a 32-bit x 32-bit multiply just works without the MACH macro. The macro apparently is only necessary to get the full 64-bit value. Fixes Piglit tests [vf]s-op-mult-int-int.shader_test. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* i965: Fix texture swizzling on Broadwell.Kenneth Graunke2013-12-021-1/+1
| | | | | | | | Like Haswell, we do this in SURFACE_STATE rather than shader workarounds. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* i965: Set vertical alignment unit to 4 on Broadwell.Kenneth Graunke2013-12-021-0/+6
| | | | | | | | | | | | Broadwell doesn't support a surface vertical alignment of 2. It only supports VALIGN_4, VALIGN_8, or VALIGN_16. I chose 4 since it's the least wasteful. v2: Replace my comment with a better one from Eric. Move Broadwell checks earlier so it's more obvious that "return 2" won't be hit. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* i965/vs: Always store pull constant offsets in GRFs on Gen8.Kenneth Graunke2013-12-021-1/+15
| | | | | | | | | | | | We need to SEND from a GRF, and we can only obtain those prior to register allocation. This allows us to do pull constant loads without the MRF hack. v2: Reword comments (suggested by Paul). Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Paul Berry <[email protected]>
* i965/vs: Don't copy propagate into SEND-from-GRF messages.Kenneth Graunke2013-12-021-0/+3
| | | | | | | | SEND can't deal with swizzles, source modifiers, and so on. This should avoid problems with VS pull constant loads on Broadwell. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* i965/hsw: Apply non-msrt fast color clear w/a to all HSW GTsChad Versace2013-12-021-6/+12
| | | | | | | | | | | | | | | | | | | | | | Pre-patch, the workaround was applied to only HSW GT3. However, the workaround also fixes render corruption on the HSW GT1 Chromebook, codenamed Falco. Also, update the BSpec quote that discusses the workaround to reflect the latest BSpec. The BSpec states that the workaround is required for Ivybridge and Baytrail as well as Haswell. But, we apply the workaround to only Haswell because (a) we suspect that is the only hardware where it is actually required and (b) we haven't yet validated the workaround for the other hardware. CC: "9.2, 10.0" <[email protected]> CC: Anuj Phogat <[email protected]> OTC-Tracker: CHRMOS-812 Reviewed-by: Paul Berry <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Signed-off-by: Chad Versace <[email protected]>
* glsl: Simplify the built-in function linking code.Kenneth Graunke2013-12-012-4/+2
| | | | | | | | | | | | | | | | | | Previously, we stored an array of up to 16 additional shaders to link, as well as a count of how many each shader actually needed. Since the built-in functions rewrite, all the built-ins are stored in a single shader. So all we need is a boolean indicating whether a shader needs to link against built-ins or not. During linking, we can avoid creating the temporary array if none of the shaders being linked need built-ins. Otherwise, it's simply a copy of the array that has one additional element. This is much simpler. This patch saves approximately 128 bytes of memory per gl_shader object. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* i965/gen6: Fix multisample resolve blits for luminance/intensity 32F formats.Paul Berry2013-11-291-0/+15
| | | | | | | | | | | | | | | | | | | | | | | | | On gen6, multisamble resolve blits use the SAMPLE message to blend together the 4 samples for each texel. For some reason, SAMPLE doesn't blend together the proper samples when the source format is L32_FLOAT or I32_FLOAT, resulting in blocky artifacts. To work around this problem, sample from the source surface using R32_FLOAT. This shouldn't affect rendering correctness, because when doing these resolve blits, the destination format is R32_FLOAT, so the channel replication done by L32_FLOAT and I32_FLOAT is unnecessary. Fixes piglit tests on Sandy Bridge: - spec/ARB_texture_float/multisample-formats 2 GL_ARB_texture_float - spec/ARB_texture_float/multisample-formats 4 GL_ARB_texture_float No piglit regressions on Sandy Bridge. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=70601 Cc: Kenneth Graunke <[email protected]> Cc: [email protected] Reviewed-by: Kenneth Graunke <[email protected]>
* mesa: fix mem leak of glPixelMap data in display listBrian Paul2013-11-291-13/+16
| | | | | | And simplify save_PixelMapfv() by using the memdup() function. Reviewed-by: Ian Romanick <[email protected]>
* mesa: added memory-related comment in save_error()Brian Paul2013-11-291-0/+4
| | | | Reviewed-by: Ian Romanick <[email protected]>
* mesa: fix flags assignment in save_WaitSync()Brian Paul2013-11-291-1/+1
| | | | | | | | The flags value is a bitfield so use the union's 'bf' field, not 'e' (enum) field. There's no actual change in behavior here since both fields of the union are the same size. Reviewed-by: Ian Romanick <[email protected]>
* mesa: remove old colortable, histogram, etc. code from dlist.cBrian Paul2013-11-291-551/+0
| | | | | | | Trying to compile any of these functions into a display list now just generates a GL_INVALID_OPERATION error. Reviewed-by: Ian Romanick <[email protected]>
* mesa: have old convolution functions generate GL_INVALID_OPERATIONBrian Paul2013-11-291-12/+12
| | | | Reviewed-by: Ian Romanick <[email protected]>
* mesa: have old glColorTable functions generate GL_INVALID_OPERATIONBrian Paul2013-11-291-10/+10
| | | | | | As is done for the old histogram functions. Reviewed-by: Ian Romanick <[email protected]>
* i965: Properly reject __DRI_CTX_FLAG_ROBUST_BUFFER_ACCESS when ↵Ian Romanick2013-11-273-4/+18
| | | | | | | | | | | | | | | | | | | __DRI2_ROBUSTNESS is not enabled Only allow __DRI_CTX_FLAG_ROBUST_BUFFER_ACCESS in brwCreateContext if intelInitScreen2 also enabled __DRI2_ROBUSTNESS (thereby enabling GLX_ARB_create_context). This fixes a regression in the piglit test "glx/GLX_ARB_create_context/invalid flag" v2: Remove commented debug code. Noticed by Jordan. Signed-off-by: Ian Romanick <[email protected]> Reported-by: Paul Berry <[email protected]> Reviewed-by: Jordan Justen <[email protected]> Reviewed-by: Matt Turner <[email protected]> Cc: "10.0" <[email protected]>
* Revert "drop old INTEL_DEBUG names for `perf` (fall) and `fs` (wm)"Matt Turner2013-11-271-0/+2
| | | | | | | This reverts commit 195994fe4cd851f4aed7fe32697f94c4188a96c8. It wasn't sent to the list, Ken didn't review it, and it breaks shader-db.
* i965: Always reserve binding table space for at least one render target.Kenneth Graunke2013-11-271-1/+4
| | | | | | | | | | | | | | | | | | | | | In brw_update_renderbuffer_surfaces(), if there are no color draw buffers, we always set up a null render target at surface index 0 so we have something to use with the FB write marking the end of thread. However, when we recently began computing surface indexes dynamically, we failed to reserve space for it. This meant that the first texture would be assigned surface index 0, and our closing FB write would clobber the texture. Fixes Piglit's EXT_packed_depth_stencil/fbo-blit-d24s8 test on Gen4-5, which regressed as of commit 4e5306453da6a1c076309e543ec92d999e02f67a ("i965/fs: Dynamically set up the WM binding table offsets.") Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=70605 Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Chris Forbes <[email protected]> Tested-by: lu hua <[email protected]> Cc: "10.0" [email protected]
* i965/fs: Fix misleading comment.Francisco Jerez2013-11-261-1/+1
| | | | Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Bump number of supported atomic counter buffers.Francisco Jerez2013-11-261-1/+1
| | | | | | | Now that we have dynamic binding tables there's no good reason anymore to expose so few atomic counter buffers. Increase it to 16. Reviewed-by: Kenneth Graunke <[email protected]>
* i965/gs: Set GS prog_data to NULL if there is no GS program.Paul Berry2013-11-261-0/+7
| | | | | | | | | | | | | The previous commit fixes a bug wherein we would incorrectly refer to stale geometry shader prog_data when no geometry shader was active. This patch reduces the likelihood of that sort of bug occurring in the future by setting prog_data to NULL whenever there is no GS program. Cc: [email protected] Reviewed-by: Eric Anholt <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965/gs: Properly skip GS binding table upload when no GS active.Paul Berry2013-11-261-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | Previously, in brw_gs_upload_binding_table(), we checked whether brw->gs.prog_data was NULL in order to determine whether a geometry shader was active. This didn't work: brw->gs.prog_data starts off as NULL, but it is set to non-NULL when a geometry shader program is built, and then never set to NULL again. As a result, if we called brw_gs_upload_binding_table() while there was no geometry shader active, but a geometry shader had previously been active, it would refer to a stale (and possibly freed) prog_data structure. This patch fixes the problem by modifying brw_gs_upload_binding_table() to use the proper technique to determine whether a geometry shader is active: by checking whether brw->geometry_program is NULL. This fixes the crash reported in comment 2 of bug 71870 (the incorrect rendering remains, however). Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=71870 Cc: [email protected] Reviewed-by: Chris Forbes <[email protected]> Reviewed-by: Eric Anholt <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* dri: Allow __DRI_CTX_FLAG_ROBUST_BUFFER_ACCESS in driCreateContextAttribsIan Romanick2013-11-261-2/+4
| | | | | | | | Signed-off-by: Ian Romanick <[email protected]> Reported-by: Zhenyu Wang <[email protected]> Reviewed-by: Matt Turner <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Cc: "10.0" <[email protected]>
* i965: Only enable __DRI2_ROBUSTNESS if kernel support is availableIan Romanick2013-11-262-16/+23
| | | | | | | | | | | | | | | | | Rather than always advertising the extension but failing to create a context with reset notifiction, just don't advertise it. I don't know why it didn't occur to me to do it this way in the first place. NOTE: Kristian requested that I provide a follow-up for master that dynamically generates the list of DRI extensions instead of selected between two hardcoded lists. Signed-off-by: Ian Romanick <[email protected]> Suggested-by: Kristian Høgsberg <[email protected]> Reviewed-by: Matt Turner <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Kristian Høgsberg <[email protected]> Cc: "10.0" <[email protected]>
* Revert "i965: Make the driver compile until a proper libdrm can be released."Ian Romanick2013-11-262-10/+5
| | | | | | | | | libdrm 2.4.48 has been released. This reverts commit bd4596efac2b783b789392a222da909efcd0fd3b. Reviewed-by: Matt Turner <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Use __attribute__((flatten)) on fast tiled teximage code.Kenneth Graunke2013-11-251-2/+8
| | | | | | | | | | | | | | | | | | | The fast tiled texture upload code does not compile with GCC 4.8's -Og optimization flag. memcpy() has the always_inline attribute set. This poses a problem, since {x,y}tile_copy_faster calls it indirectly via {x,y}tile_copy, and {x,y}tile_copy normally aren't inlined at -Og. Using __attribute__((flatten)) tells GCC to inline every function call inside the function, which I believe was the author's intent. Fix suggested by Alexander Monakov. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Matt Turner <[email protected]> Reviewed-by: Chad Versace <[email protected]> Cc: [email protected]
* i965: Enable ARB_draw_indirect (and ARB_multi_draw_indirect) on Gen7+Chris Forbes2013-11-251-0/+1
| | | | | | | | | | | .. and mark them off on the extensions list as done. V2: Enable only if pipelined register writes work. V3: Also update relnotes Signed-off-by: Chris Forbes <[email protected]> Reviewed-by: Ian Romanick <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* vbo: map indirect buffer and extract params if doing sw primitive restartChris Forbes2013-11-251-0/+33
| | | | | | | | | V2: Check for mapping failure (thanks Brian) V3: - Change error on mapping failure to OUT_OF_MEMORY (Brian) - Unconst; remove casting away of const. Signed-off-by: Chris Forbes <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* mesa: pass indirect buffer to sw primitive restartChris Forbes2013-11-254-4/+6
| | | | | Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* i965: pass indirect buffer to primitive restart checkChris Forbes2013-11-253-6/+9
| | | | | | Signed-off-by: Chris Forbes <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* i965: implement indirect drawing for Gen7Chris Forbes2013-11-251-2/+55
| | | | | | | | | | | | | | | | | | | | Just prior to emitting the 3DPRIMITIVE command, we load each of the indirect registers. The values loaded are either from offsets into the current indirect BO, or constant zero if the parameter is not used for this draw. Enabling use of the indirect registers is done by turning on a bit in the first dword of the 3DPRIMITIVE command itself. V3: - Deduplicate the common part of both indexed and nonindexed indirect setup. - Just refer to the indirect bo out of the context directly. V4: - Fix bo reference to specify the range we care about. Signed-off-by: Chris Forbes <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* i965: Add new defines for indirect drawsChris Forbes2013-11-252-0/+9
| | | | | | | | | - MMIO registers for draw parameters - New bit in 3DPRIMITIVE command to enable indirection Signed-off-by: Chris Forbes <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* vbo: Flesh out implementation of indirect drawsChris Forbes2013-11-251-0/+218
| | | | | | | | | Based on part of Patch 2 of Christoph Bumiller's ARB_draw_indirect series. Signed-off-by: Chris Forbes <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* mesa: add indirect_offset, is_indirect to _mesa_primChris Forbes2013-11-254-1/+12
| | | | | | | | | V3: Add missing cases V4: Add indirect_offset here too Signed-off-by: Chris Forbes <[email protected]> Reviewed-by: Paul Berry <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* mesa: Add validation helpers for new indirect drawsChris Forbes2013-11-252-0/+218
| | | | | | | | | | | | | | | | | Based on part of Patch 2 of Christoph Bumiller's ARB_draw_indirect series. V3: - Disallow primcount==0 for DrawMulti*Indirect. The spec is unclear on this, but it's silly. We might go back on this later if it turns out to be a problem. - Make it clear that the caller has dealt with stride==0 V4: - Allow primcount==0 again. Signed-off-by: Chris Forbes <[email protected]> Reviewed-by: Paul Berry <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* mesa: Add binding point for indirect bufferChris Forbes2013-11-254-0/+22
| | | | | | | | Based on part of Patch 2 of Christoph Bumiller's ARB_draw_indirect series. Signed-off-by: Chris Forbes <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
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