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* intel: Make intel_region_map return void *.Eric Anholt2011-12-072-4/+4
| | | | | | | | We don't gripe about void * arithmetic for our driver, and this prevents silly casting when assigning the result of mapping to non-byte types. Reviewed-by: Chad Versace <[email protected]>
* intel: Move separate-stencil s8 mapping logic to intel_miptree_map.Eric Anholt2011-12-072-113/+112
| | | | | | | We're going to want to reuse this logic in mapping of fake packed miptrees wrapping separate depth/stencil miptrees. Reviewed-by: Chad Versace <[email protected]>
* intel: Move the gtt-particular texture mapping logic to a helper function.Eric Anholt2011-12-071-49/+71
| | | | | | | This code will be incrementally moving to a model like intel_fbo.c's renderbuffer mapping with helper functions, as I move that code here. Reviewed-by: Chad Versace <[email protected]>
* intel: Make mapping of texture slices track the region of interest.Eric Anholt2011-12-072-5/+51
| | | | | | | This will be used for things like packed depth/stencil temporaries and making LLC-cached temporary mappings using blits. Reviewed-by: Chad Versace <[email protected]>
* intel: Move the teximage mapping logic to a miptree level/slice mapping.Eric Anholt2011-12-073-48/+109
| | | | | | | This will let us share teximage mapping logic with renderbuffer mapping, which has an intel_mipmap_tree but not a gl_texture_image. Reviewed-by: Chad Versace <[email protected]>
* intel: Only prefer separate stencil when we can do HiZ.Eric Anholt2011-12-072-4/+14
| | | | | | | | | | | | This required is_hiz_depth_format to start returning true on S8_Z24 as well, since that's the format we have here. The two previous callers are only calling it on non-depthstencil formats. This avoids us needing to have HiZ working on a new Z format immediately upon exposing the format (particularly painful for Z32_FLOAT_X24S8, which means all the fake packed depth/stencil paths). Reviewed-by: Chad Versace <[email protected]>
* i965: Set SURFACE_STATE vertical alignment bit on Ivybridge.Kenneth Graunke2011-12-061-0/+7
| | | | | | | | | | | | See intel_vertical_texture_alignment_unit() in intel_tex_layout.c; certain surface types require setting this to VALIGN_4. Analogous to commit dd0e46c4102976b7d317104ecd1bb565ac34613a on Gen6. Fixes piglit test fbo-generatemipmap-formats with the GL_ARB_depth_texture and GL_EXT_packed_depth_stencil arguments. Signed-off-by: Kenneth Graunke <[email protected]>
* radeon: add original r100 to the always tiled depth list.Dave Airlie2011-12-061-1/+1
| | | | | | According to Alex, he thinks r100 is also covered. Signed-off-by: Dave Airlie <[email protected]>
* osmesa: remove unused bpc variableFabio Pedretti2011-12-061-8/+0
| | | | Signed-off-by: Brian Paul <[email protected]>
* radeon/r200: add RV200 detiling + add an always tiled flagDave Airlie2011-12-063-37/+72
| | | | | | passes readpix sanity on the M7. Signed-off-by: Dave Airlie <[email protected]>
* r200: add Z16 depth detiling.Dave Airlie2011-12-061-0/+105
| | | | | | This passes readPixSanity with z16 visuals. Signed-off-by: Dave Airlie <[email protected]>
* r200: handle Z24 depth buffers correctlyDave Airlie2011-12-061-2/+2
| | | | | | The same detiling pattern applies to X8_Z24 as well. Signed-off-by: Dave Airlie <[email protected]>
* r200: fix cb microtile setupDave Airlie2011-12-061-0/+3
| | | | | | We shouldn't see this in buffers from the DDX but just in case. Signed-off-by: Dave Airlie <[email protected]>
* r200: enable tiling flags on blitter setup.Dave Airlie2011-12-061-0/+10
| | | | | | The r200 blitter also didn't set the correct tiling flags. Signed-off-by: Dave Airlie <[email protected]>
* swrast: Add depth cube map support.Anuj Phogat2011-12-051-4/+14
| | | | | Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Brian Paul <[email protected]>
* mesa: Allow glTexImage2D with a depth component cube map.Anuj Phogat2011-12-051-2/+5
| | | | | | Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* i965: Fix incorrect comment about single program flow on Ironlake.Kenneth Graunke2011-12-051-1/+1
| | | | | | | | The code forces single program flow to be enabled on Ironlake, or equivalently, disables multiple program flow. The comment was reversed. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* radeon/r200: drop old span depth/stencil code.Dave Airlie2011-12-051-317/+0
| | | | | | This is no longer used with the new renderbuffer code. Signed-off-by: Dave Airlie <[email protected]>
* radeon/r200: add draw/stencil buffer detilingDave Airlie2011-12-052-0/+111
| | | | | | | This moves the detiling to the fbo mapping, r200 depth is always tiled, and we can't detile it with the blitter. Signed-off-by: Dave Airlie <[email protected]>
* radeon: fix warningsDave Airlie2011-12-051-2/+2
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* radeon: use mesa renderbuffer accessors for depth for now.Dave Airlie2011-12-051-4/+5
| | | | Signed-off-by: Dave Airlie <[email protected]>
* radeon: add some tiling support for r100.Dave Airlie2011-12-052-0/+13
| | | | | | | | This sets up the tiling flags on the blitter. Fixes some piglit tests with tiling enabled. Signed-off-by: Dave Airlie <[email protected]>
* radeon: texture/renderbuffer overhaul.Dave Airlie2011-12-0513-599/+385
| | | | | | | | | | | | | | | This could have been split up better, but the driver is just broken now, so bisecting the brokenness is going to be painful no matter what. This adds renderbuffer mapping/unmapping along with texture image allocation. It drops all the old texture upload paths, some of which could possible be reimplemented with the blitter later. It also redoes the span code paths to use its own set of image mapping handlers, along with removing the tiling decode paths for the color buffers, since we now hope to use the blitter for this. Signed-off-by: Dave Airlie <[email protected]>
* radeon: set texture bits to always emit.Dave Airlie2011-12-051-3/+3
| | | | | | | I think there is a missing state update or flush somewhere, and every so often PP_CNTL goes to the kernel with a texture enabled but no texture. Signed-off-by: Dave Airlie <[email protected]>
* radeon: update flush according to glXMakeCurrent man pageDave Airlie2011-12-051-2/+15
| | | | | | This also copies code from intel driver to do this. Signed-off-by: Dave Airlie <[email protected]>
* radeon: drop border checkDave Airlie2011-12-051-5/+0
| | | | | | now that we strip borders off earlier. Signed-off-by: Dave Airlie <[email protected]>
* radeon: add a bit more debugging to the blit debug code.Dave Airlie2011-12-051-4/+4
| | | | | | For debugging blits it helps if we printed out the offsets as well. Signed-off-by: Dave Airlie <[email protected]>
* mesa: Reject glDrawPixels(integer format).Eric Anholt2011-12-041-0/+18
| | | | | | | When folding GL_EXT_texture_integer into the core, a new (and very sensible) restriction was added. Reviewed-by: Brian Paul <[email protected]>
* mesa: Use VERT_{ATTRIB,BIT}* for ARB input validation.Mathias Fröhlich2011-12-032-4/+4
| | | | | | | | | | | | | For validating ARB program inputs replace hard coded bitfield and attribute number with the appropriate VERT_{ATTRIB,BIT}* variant. This should fix: https://bugs.freedesktop.org/show_bug.cgi?id=43407 Signed-off-by: Mathias Froehlich <[email protected]> Reviewed-by: Jose Fonseca <[email protected]>
* i965: Fix emit of a MOV with bad destination channel on gen6 math in FPs.Stuart Abercrombie2011-12-021-5/+5
| | | | | | | | | Previously a zero writemask would result in dst_chan == -1, meaning an unnecessary MOV with the destination register dictated by undefined memory contents would be emitted before returning. This caused intermittent GPU hangs, e.g. with glean/texCombine. Reviewed-by: Eric Anholt <[email protected]>
* mesa: Fix assertions for block size handling in glCompressedTexSubImage2D.Eric Anholt2011-12-021-2/+2
| | | | | | | | | | | Anything of less than (bw, bh) size is possible when you consider rectangular textures, and this code is (now) safe for those. Even for power-of-two textures, width could be 4 for FXT1 while not being aligned to block size. Fixes piglit compressedteximage GL_COMPRESSED_RGB_FXT1_3DFX Reviewed-by: Brian Paul <[email protected]>
* mesa: Fix glCompressedTexSubImage (and non-Sub) for height == 2 or 1.Eric Anholt2011-12-021-1/+1
| | | | | | | | | | Generally this code works with width and height aligned to compressed blocks, but at the 2x2 and 1x1 levels of a square texture (or height < bh in general), we were skipping uploading our single row of blocks. Fixes piglit compressedteximage GL_COMPRESSED_RGBA_S3TC_DXT5_EXT. Reviewed-by: Brian Paul <[email protected]>
* mesa: Fix glCompressedTexImage when dstRowStride != srcRowStride.Eric Anholt2011-12-021-28/+9
| | | | | | | | | | | | | | | | | | | | | | Since the MapTextureImage changes on Intel, nwn had corruption in the scrollbar at the load game menu, and corrupted ground textures in the starting zone. Heroes of Newerth's intro screen was also thoroughly garbled. A new piglit test "compressedteximage" was created to regression test this. The issue was this code now seeing dstRowStride aligned to hardware requirements instead of a temporary buffer that gets uploaded to hardware later. The existing code was just trying to memcpy srcRowStride * height / bh, while the glCompressedTexSubImage2D() storage code nearby did the correct walking by blockheight rows at a time. Just reuse the subimage upload instead of duplicating that logic. v2: Update comment at the top of the function (suggestion by Joel Forsberg) Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=41451 Reviewed-by: Kenneth Graunke <[email protected]> (v1)
* mesa: add casts to fix unpack_SIGNED_GR1616()Brian Paul2011-12-021-2/+2
| | | | We were passing unsigned values to the macro before.
* mesa: remove unreachable code in _mesa_unpack_color_span_ubyte()Brian Paul2011-12-021-64/+0
| | | | | | | | We checked if srcType == GL_UNSIGNED_BYTE earlier so there was no way to reach this code. This was left-over code from the GLchan removal work. Reviewed-by: José Fonseca <[email protected]>
* vbo: remove unreachable _mesa_error() callBrian Paul2011-12-021-3/+0
| | | | | | | If mode is not GL_POINT/LINE/FILL we'll have already reported the error earlier in the function and returned so we can never get here. Reviewed-by: José Fonseca <[email protected]>
* mesa: move _mesa_error() call in compressedteximage()Brian Paul2011-12-021-7/+2
| | | | | | | | We shouldn't call _mesa_error() if the target is a proxy texture. Errors are handled later in the function. Fixes a Coverity warning. Reviewed-by: José Fonseca <[email protected]>
* mesa: fix potential mem leak in generate_mipmap_compressed()Brian Paul2011-12-021-0/+1
| | | | | | Fixes a coverity warning. Reviewed-by: Vinson Lee <[email protected]>
* mesa: fix some minor texstore commentsBrian Paul2011-12-021-3/+3
| | | | For the texsubimage commands, we're not mapping the whole image/region.
* mesa: rename MESA_FORMAT_RG88_REV to MESA_FORMAT_RG88Brian Paul2011-12-027-19/+19
| | | | R is in the high byte, G in the low byte.
* mesa: rename MESA_FORMAT_RG88 to MESA_FORMAT_GR88Brian Paul2011-12-0212-30/+30
| | | | | To better reflect the component ordering and be consistent with other format names.
* mesa: fix unpacking of RG88_REV texelsBrian Paul2011-12-022-5/+5
| | | | R should be in the high byte and G in the low byte for this format.
* i965: Make gen6_resolve_implied_move a no-op for MRF sources.Kenneth Graunke2011-12-021-0/+3
| | | | | | | | | | Attempting to move an MRF to a MRF is not only pointless, it will fail because MRFs are read-only, resulting in garbage in your register. If we already set up a MRF source, there's nothing to resolve anyway. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* mesa: Renumber the tnl attributes to match VERT_ATTRIB*.Mathias Fröhlich2011-12-021-29/+29
| | | | | | | | | | | | | Also renumber the tnl modules vertex attributes to match the renumbered VERT_ATTRIB_* values. This should fix https://bugs.freedesktop.org/show_bug.cgi?id=43353 Signed-off-by: Mathias Froehlich <[email protected]> Tested-by: Vinson Lee <[email protected]> Reviewed-by: Brian Paul <[email protected]>
* mesa: Extend BITSET64_*_RANGE to work on arbitrary ranges.Mathias Fröhlich2011-12-021-3/+18
| | | | | | | | | | The BITSET64_{TEST,SET,CLEAR}_RANGE macros only work on ranges wither in the lower 32 or in the upper 32 bits of the bitset. This change extends these macros to work on arbitrary ranges possibly crossing the bitset word boundary. Signed-off-by: Mathias Froehlich <[email protected]> Reviewed-by: Brian Paul <[email protected]>
* st/mesa: add support for GL_OES_compressed_ETC1_RGB8_textureChia-I Wu2011-12-022-0/+20
| | | | | | | Have st/mesa recognize MESA_FORMAT_ETC1_RGB8 then we are good to advertise the extension. Reviewed-by: Brian Paul <[email protected]>
* mesa: add support for GL_OES_compressed_ETC1_RGB8_textureChia-I Wu2011-12-0213-0/+130
| | | | | | | | | | | Add support for GL_OES_compressed_ETC1_RGB8_texture to core mesa. There is no driver support yet. Unlike desktop GL compressed texture formats, GLES compressed texture formats usually can only be used with glCompressedTexImage2D. All other gl*Tex*Image* functions are updated to check for that. Reviewed-by: Brian Paul <[email protected]>
* mesa: add ETC1 decoding routinesChia-I Wu2011-12-025-0/+249
| | | | | | | The format is defined by GL_OES_compressed_ETC1_RGB8_texture. These routines will be used in the following commit. Reviewed-by: Brian Paul <[email protected]>
* glapi: regenerate files for GL_OES_compressed_ETC1_RGB8_textureChia-I Wu2011-12-021-3035/+3038
| | | | Reviewed-by: Brian Paul <[email protected]>
* swrast: Fix signed/unsigned problems with negative strides.Mathias Fröhlich2011-12-011-2/+2
| | | | | | | | | | In swrast_map_renderbuffer negative strides lead to render buffer map pointers that are off by 2^32. Make sure that intermediate negative values are not converted to an unsigned. Signed-off-by: Mathias Froehlich <[email protected]> Reviewed-by: Brian Paul <[email protected]>
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