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* mesa: implement depth unpacking for GL_FLOAT_32_UNSIGNED_INT_24_8_REVMarek Olšák2011-07-101-2/+25
| | | | Reviewed-by: Kenneth Graunke <[email protected]>
* mesa: implement stencil unpacking for GL_FLOAT_32_UNSIGNED_INT_24_8_REVMarek Olšák2011-07-101-3/+32
| | | | Reviewed-by: Kenneth Graunke <[email protected]>
* mesa: implement texfetch functions for depth_buffer_floatMarek Olšák2011-07-102-8/+31
| | | | Reviewed-by: Kenneth Graunke <[email protected]>
* mesa: initial ARB_depth_buffer_float supportMarek Olšák2011-07-109-6/+125
| | | | | | | Using GL_NONE as DataType of Z32_FLOAT_X24S8, not sure what I should put there. The spec says the type is n/a. Reviewed-by: Kenneth Graunke <[email protected]>
* intel: Recognize all depth formats in get_teximage_readbuffer.Kenneth Graunke2011-07-091-8/+4
| | | | | | | | | | | | | | | | | | | The existing code was missing GL_DEPTH_COMPONENT32, resulting in it wrongly returning the color buffer instead of the depth buffer. Fixes an issue in PlaneShift 0.5.7 when casting spells. The game calls CopyTexSubImage2D on buffers with a GL_DEPTH_COMPONENT32 internal format, which (prior to this patch) resulted in an attempt to copy ARGB8888 to X8_Z24. Instead of adding the missing enumeration directly, convert the code to use _mesa_is_depth_format() and _mesa_is_depthstencil_format() as these should catch any newly added depth formats in the future. NOTE: This is a candidate for the 7.10 and 7.11 branches. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* i965/gen4: Fix GPU hangs since the program streaming change.Eric Anholt2011-07-091-1/+1
| | | | | | | | | | This was tricky. We were doing a use-before-initialize of grf_reg_count, but the value usually got overwritten anyway -- when we didn't have to do a relocation (typical), or on gen5 when we didn't have relocations at all. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=38771 Reviewed-by: Kenneth Graunke <[email protected]>
* i965/gen7: Remove gratuitous dirty flags from WM and PS state.Kenneth Graunke2011-07-081-8/+3
| | | | | | | | | | | | | | | | Commit b46dc45ceef3deb17ba2b0b4300eeb93e9cf7833 claimed that NEW_POLYGONSTIPPLE is gratuitous, but somehow just changed comments and whitespace instead of actually removing the flag. While we're at it, 3DSTATE_PS doesn't appear to need NEW_LINE or NEW_POLYGON either (those are in 3DSTATE_WM). Also, 3DSTATE_WM doesn't appear to need BRW_NEW_NR_WM_SURFACES or BRW_NEW_CURBE_OFFSETS either (those are in 3DSTATE_PS). NOTE: This is a candidate for the 7.11 branch. Reviewed-by: Eric Anholt <[email protected]> Signed-off-by: Kenneth Graunke <[email protected]>
* st/mesa: handle float formats in st_format_datatypeMarek Olšák2011-07-081-2/+14
| | | | | | NOTE: This is a candidate for the 7.11 branch. Reviewed-by: Brian Paul <[email protected]>
* st/mesa: use the first non-VOID channel in st_format_datatypeMarek Olšák2011-07-081-3/+16
| | | | | | | | Otherwise PIPE_FORMAT_X8B8G8R8_UNORM and friends would fail. NOTE: This is a candidate for the 7.10 and 7.11 branches. Reviewed-by: Brian Paul <[email protected]>
* mesa/st: Fix piglit read-front with new drawable invalidation v2Thomas Hellstrom2011-07-081-0/+9
| | | | | | | | | | | | | When the state tracker adds a front buffer, nothing triggers a validate drawable call, since the state tracker manager is never notified. Force a validate drawable call by invalidating the framebuffer's stamp, so that the window system's renderbuffer (if any) is picked up. This fixes bug 38988 https://bugs.freedesktop.org/show_bug.cgi?id=38988 Signed-off-by: Thomas Hellstrom <[email protected]>
* intel: add null src pointer check in intel_region_reference()Brian Paul2011-07-071-1/+2
| | | | | | | | Fixes segfault when running cubemap demo on i945. This happened when intel_region_reference() was called in i915_set_draw_region() with depth_region=NULL. Reviewed-by: Eric Anholt <[email protected]>
* intel: Fix use of freed buffer if glBitmap is called after a swap.Eric Anholt2011-07-071-3/+4
| | | | | | | | Regions looked up from the framebuffer are invalid after intel_prepare_render(). Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=30266 Tested-by: Thomas Jones <[email protected]>
* intel: Remove dead comment about software clears -- it's handled just above.Eric Anholt2011-07-071-1/+0
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* i915: Fix leak of ViewportMatrix data on context destroy.John2011-07-071-0/+2
| | | | Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=30217
* intel: Remove gratuitous context checks in intel_delete_renderbuffer().Eric Anholt2011-07-071-14/+5
| | | | | | | | | Even if we don't have a current context, if we're freeing the rb we should free its region (and BO). The renderbuffer unreference checks appear to be just cargo-cult from the region unreference code. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=30217 Reviewed-by: Chad Versace <[email protected]>
* intel: Remove now trivial intel_renderbuffer_set_{hiz_,}region().Eric Anholt2011-07-073-57/+19
| | | | | | | | | As a result of this cleanup, a bug in intel_process_dri2_buffer_no_separate_stencil() became quite apparent. We were associating the NULL pointer after an unreference with the STENCIL attachment -- clarify the logic and attach the right region. Reviewed-by: Chad Versace <[email protected]>
* intel: Rely on intel_region_reference()'s support of *dst != NULL.Eric Anholt2011-07-074-18/+0
| | | | Reviewed-by: Chad Versace <[email protected]>
* intel: Allow intel_region_reference() with *dst != NULL.Eric Anholt2011-07-071-4/+6
| | | | | | | This should help us avoid leaking regions in region reference code by making the API more predictable. Reviewed-by: Chad Versace <[email protected]>
* intel: Mark MESA_FORMAT_X8_Z24 as always supported.Eric Anholt2011-07-071-1/+1
| | | | | | | | | | This prevents developer surprise at seeing a GL_DEPTH_COMPONENT texture have stencil bits, and avoids the metaops path accidentally copying stencil bits around in glCopyTexImage(GL_DEPTH_COMPONENT) (and being broken because swrast's glReadPixels(GL_UNSIGNED_INT_24_8) is broken). Acked-by: Chad Versace <[email protected]>
* i965: Remove unused structures for command packets.Kenneth Graunke2011-07-071-433/+0
| | | | | | | | | We simply emit these using OUT_BATCH and bitshifting, as it results in better compiled code than packed structures. Since our documentation is public, it's not terribly useful to keep these around for reference. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* i965: Convert system instruction pointer to OUT_BATCH style.Kenneth Graunke2011-07-072-14/+5
| | | | | | | | Also rename it from CMD_STATE_INSN_POINTER to CMD_STATE_SIP to match the documentation. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* i965: Convert PIPELINE_SELECT to OUT_BATCH style.Kenneth Graunke2011-07-071-10/+4
| | | | | Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* i965: Emit 3DSTATE_VF_STATISTICS in OUT_BATCH style.Kenneth Graunke2011-07-072-18/+4
| | | | | | | | This is a little different from most because it's a single DWord; there's no length field. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* i965: Convert 3DSTATE_GLOBAL_DEPTH_OFFSET_CLAMP to OUT_BATCH style.Kenneth Graunke2011-07-072-19/+5
| | | | | Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* mesa: Fix the BindSampler unit limit.Henri Verbeet2011-07-071-1/+1
| | | | | | | | | | | I'm not sure about this one. The current code actually follows the spec, but considering the spec is supposed to be written against GL 3.2 I'd say the spec is broken. I filled out a spec feedback form over a month ago, but either the form is broken, or nobody cares. Signed-off-by: Henri Verbeet <[email protected]> Reviewed-by: Brian Paul <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* mesa: Fix a couple of TexEnv unit limits.Henri Verbeet2011-07-071-3/+3
| | | | | | | | NOTE: This is a candidate for the 7.11 branch. Signed-off-by: Henri Verbeet <[email protected]> Reviewed-by: Brian Paul <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* mesa: Use the Elements macro for the sampler index assert in ↵Henri Verbeet2011-07-071-1/+1
| | | | | | | | | | | | validate_samplers(). This is probably nicer if the array size ever changes. NOTE: This is a candidate for the 7.11 branch. Signed-off-by: Henri Verbeet <[email protected]> Reviewed-by: Brian Paul <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* mesa: Allow sampling from units >= MAX_TEXTURE_UNITS in shaders.Henri Verbeet2011-07-073-4/+4
| | | | | | | | | | | | The total number of units used by a shader is limited to MAX_TEXTURE_UNITS, but the actual indices are only limited by MAX_COMBINED_TEXTURE_IMAGE_UNITS, since they're shared between vertex and fragment shaders. NOTE: This is a candidate for the 7.11 branch. Signed-off-by: Henri Verbeet <[email protected]> Reviewed-by: Brian Paul <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* mesa: Check the texture against all units in unbind_texobj_from_texunits().Henri Verbeet2011-07-071-1/+1
| | | | | | | | NOTE: This is a candidate for the 7.11 branch. Signed-off-by: Henri Verbeet <[email protected]> Reviewed-by: Brian Paul <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* ir_to_mesa: Allocate temporary instructions on the visitor's ralloc contextIan Romanick2011-07-061-16/+12
| | | | | | | | | | | | And don't delete them. Let ralloc clean them up. Deleting the temporary IR leaves dangling references in the prog_instruction. That results in a bad dereference when printing the IR with MESA_GLSL=dump. NOTE: This is a candidate for the 7.10 and 7.11 branches. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=38584 Reviewed-by: Eric Anholt <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* mesa: fix texstore addressing bugs for depth/stencil formatsBrian Paul2011-07-061-12/+9
| | | | | | | | | | Using GLuint pointers worked when the pixel size was four bytes or the row stride was a multiple of four but was otherwise broken. Fixes failures found with the piglit fbo-stencil test. This helps to fix https://bugs.freedesktop.org/show_bug.cgi?id=38729 NOTE: This is a candidate for the 7.11 branch.
* mesa: Don't error on glFeedbackBuffer(size = 0, buffer = NULL)Eric Anholt2011-07-061-1/+1
| | | | | | | | | | | The existing error result doesn't appear in the GL 2.1 or 3.2 compatibility specs, and triggers an unexpected GL error in Intel's oglconform when it tries to reset the feedback state after usage so that the "diff the state at error time vs. context init time" code doesn't generate spurious diffs. The unexpected GL error then translates into testcase failure. Brian wants the safety check on buffer = NULL, though, so that people can't as easily set up a broken buffer.
* mesa: Don't skip glGetProgramLocalParam4dvARB if there was already an error.Eric Anholt2011-07-061-64/+53
| | | | | | | Like the previous commit, but fixes ARB_vertex_program/getlocal4d-with-error. v2: Move the success case line into the conditional, use ASSIGN_4V more.
* mesa: Don't skip glGetProgramEnvParam4dvARB if there was already an error.Eric Anholt2011-07-061-66/+46
| | | | | | | | | | Fixes a bug caught by oglconform, and now piglit ARB_vertex_program/getenv4d-with-error. The wrapping of an existing GL function made it so that we couldn't distinguish an error in looking up our arguments from an existing error. Instead, make a helper function to choose the param, and use it from multiple callers. v2: Move the success case line into the conditional, use COPY_4V more.
* i965/fs: Fix message register allocation in FB writes.Kenneth Graunke2011-07-061-5/+6
| | | | | | | | | Commit 6750226e6d915742ebf96bae2cfcdd287b85db35 bumped the base MRF to m2 instead of m0, but failed to adjust inst->mlen, which was being set to the highest MRF. Subtracting the base MRF solves the issue. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Ben Widawsky <[email protected]>
* i965/fs: Implement new ir_unop_u2i and ir_unop_i2u opcodes.Kenneth Graunke2011-06-292-0/+10
| | | | | | | | | | No MOV is necessary since signed/unsigned integers share the same bit-representation; it's simply a question of interpretation. In particular, the fs_reg::imm union shouldn't need updating. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Ian Romanick <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* ir_to_mesa: "Support" u2f, i2u, and u2i operations by doing nothing.Kenneth Graunke2011-06-291-1/+3
| | | | | | | | | Mesa IR actually stores all numbers as floating point, so this is totally a farce, but we may as well keep it going. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Ian Romanick <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* i965/gen7: Add missing ! to brw->gs.prog_active assertion.Kenneth Graunke2011-06-291-1/+1
| | | | | | | | | A typo in commit c173541d9769 accidentally removed the !. It's supposed to assert that there is _not_ an active GS program. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=38762 Signed-off-by: Kenneth Graunke <[email protected]>
* mesa: bump version to 7.12 (devel)Brian Paul2011-06-291-2/+2
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* st/mesa: s/tex_usage/bindings/ in st_format.hBrian Paul2011-06-291-1/+1
| | | | Just be consistent with the .c file.
* st/mesa: Use correct internal targetEmil Velikov2011-06-291-2/+2
| | | | | | | | | | | Commit 1a339b6c(st/mesa: prefer native texture formats when possible) introduced two new arguments to the st_choose_format() functions. This patch fixes the order and passes the correct internal_target rather than GL_NONE NOTE: This is a candidate for the 7.11 branch Signed-off-by: Emil Velikov <[email protected]> Signed-off-by: Brian Paul <[email protected]>
* st/mesa: fix overwriting gl_format with pipe_format since 9d380f48Andre Maasikas2011-06-291-2/+2
| | | | | | fixes assert later on in texcompress2/r600g Signed-off-by: Brian Paul <[email protected]>
* st-api: Rework how drawables are invalidated v3.Thomas Hellstrom2011-06-293-50/+73
| | | | | | | | | | | | | | | The api and the state tracker manager code as well as the state tracker code assumed that only a single context could be bound to a drawable. That is not a valid assumption, since multiple contexts can bind to the same drawable. Fix this by making it the state tracker's responsibility to update all contexts binding to a drawable Note that the state trackers themselves don't use atomic stamps on frame-buffers. Multiple context rendering to the same drawable should be protected by the application. Signed-off-by: Thomas Hellstrom <[email protected]>
* i965: Reissue PIPELINE_POINTERS and BINDING_TABLE_POINTERS on SBA change.Eric Anholt2011-06-286-12/+55
| | | | | This was a requirement we didn't run into until we started using STATE_BASE_ADDRESS for instruction data.
* i965/gen6: Fix scissors using invalid STATE_BASE_ADDRESS.Eric Anholt2011-06-281-2/+2
| | | | | | | | The scissor state was incorrectly in a .prepare function instead of .emit, so the packet would end up in the batch before the STATE_BASE_ADDRESS. It appears that this doesn't actually hurt, as the scissor address gets dereferenced according to the current SBA at draw time.
* i965: step message register allocationBen Widawsky2011-06-271-5/+5
| | | | | | | | The system routine requires m0 be reserved for saving off architectural state. Moved the allocation to start at 2 instead of 0. Signed-off-by: Ben Widawsky <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* Revert "Fix 24bpp software rendering"Brian Paul2011-06-253-89/+4
| | | | This reverts commit c0c0bb6cb140825f5bab3c40c0c9c0ec575fbc76.
* i965/gen5: Fix grf_used calculation for 16-wide.Eric Anholt2011-06-241-5/+4
| | | | | | | | | | If we happened to allocate a texture result (or other vector) to the highest hardware register slot, and we were in 16-wide, we would under-count the registers used and potentially wrap around to g0 if that allocation crossed a 16-register block boundary. Bad rendering and hangs ensued. Tested-by: Ian Romanick <[email protected]>
* i965: fix mask used to write to clip distance registers when gen>6Paul Berry2011-06-241-1/+1
| | | | | | | | | | | | | In gen6 and above, clip distances 0-3 are written to message register 3's xyzw components, and 4-7 to message register 4's xyzw components. Therefore when when writing the clip distances we need to examine the lower 2 bits of the clip distance index to see which component to write to. emit_vertex_write() was examining the lower 3 bits, causing clip distances 4-7 not to be written correctly. Fixes piglit test vs-clip-vertex-01.shader_test
* intel: Fix workaround for _mesa_update_framebufferChad Versace2011-06-241-3/+5
| | | | | | | | | | | In intel_draw_buffer, there exists a workaround to prevent _mesa_update_framebuffer from creating a swrast depth wrapper when using separate stencil. This commit fixes the workaround, which was incomplete for s8z24 texture renderbuffers. Fixes fbo-blit-d24s8 on gen5 with separate stencil manually enabled. Signed-off-by: Chad Versace <[email protected]>
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