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* Merge branch 'master' of git+ssh://[email protected]/git/mesa/mesajoukj2007-11-30145-11467/+10552
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| * i965: if source depth to render target is set,Xiang, Haihao2007-11-301-0/+14
| | | | | | | | it should be handled in fb_write.
| * i965: use uncompressed instruction to ensure onlyXiang, Haihao2007-11-301-0/+1
| | | | | | | | | | Pixel Mask Copy is modified as the pixel shader thread turns off pixels based on kill instructions.
| * [i915] Make INTEL_DEBUG=bufmgr actually do things for bufmgr_fake.Eric Anholt2007-11-293-6/+17
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| * New ctx->Driver.Map/UnmapTexture() functions for accessing textures from ↵Brian2007-11-294-1/+56
| | | | | | | | t_vb_program.c
| * cleanups, commentsBrian2007-11-291-27/+28
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| * Move _mesa_load_tracked_matrices() from TNL module to prog_statevars.cBrian2007-11-294-102/+101
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| * r200: Fix texture format regression on big endian systems.Michel Dänzer2007-11-281-3/+6
| | | | | | | | | | | | | | See https://bugs.freedesktop.org/show_bug.cgi?id=13324 . Also use tx_table_be for VALID_FORMAT, in case r200SetTexImages ever gets called for MESA_FORMAT_RGB888.
| * i965: update RefCount when using Vertex/Fragment program.Xiang, Haihao2007-11-281-0/+2
| | | | | | | | It makes quake4-demo works well on 965.
| * use DEFAULT_SOFTWARE_DEPTH_BITSDelle2007-11-271-9/+11
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| * set fp->UsesKill when emitting OPCODE_KILBrian2007-11-271-2/+8
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| * improve 24-bit Z to 32-bit Z conversionBrian2007-11-271-2/+3
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| * i965: The jump instruction count is addedXiang, Haihao2007-11-271-1/+1
| | | | | | | | | | | | to IP pre-increment, and should point to the first instruction after the do instruction of the do-while block of code
| * i915: Catch cases where not all state is emitted for a new batchbuffer.Keith Whitwell2007-11-266-1/+56
| | | | | | | | This could lead to incorrect rendering or even lockups.
| * i915: Some additional blit fixes and assertions.Michel Dänzer2007-11-261-8/+24
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| * intel: Fix relative symlinks.Michel Dänzer2007-11-252-2/+2
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| * Consolidate texture fetch code and use partial derivatives when possible.Brian2007-11-233-75/+79
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| * Fix parsing of gl_FrontLightModelProduct.sceneColor, don't segfault on ↵Brian2007-11-232-5/+15
| | | | | | | | variable array indexes.
| * need to check border width in sample_linear_2d() - fixes failed assertion in ↵Brian2007-11-231-1/+2
| | | | | | | | texwrap.c test
| * Consolidate point size computation, clamping in get_size().Brian2007-11-221-36/+35
| | | | | | | | | | Also, apply user-defined clamp limits to point size even when not using attentuation or program-computed size.
| * fix z buffer read/write issue with rv100-like chips and old ddxRoland Scheidegger2007-11-221-1/+5
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| * [965] Replace 965 texture format code with common code.Eric Anholt2007-11-208-187/+8
| | | | | | | | | | The only functional difference should be that 965 now gets the optimization where textures default to 16bpp when the screen is 16bpp.
| * [965] Remove dead exec vfmt code which was replaced by generic vbo code.Eric Anholt2007-11-201-530/+0
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| * clamp lambda to Min/MaxLodBrian2007-11-201-3/+6
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| * [965] Add INTEL_DEBUG=fall debugging output.Eric Anholt2007-11-191-5/+17
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| * [965] Convert DBG macro to use FILE_DEBUG_FLAG like i915.Eric Anholt2007-11-1912-16/+31
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| * fix some texture format assertions, etcBrian2007-11-191-23/+11
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| * fix out-of-bounds array index (ix=-1)Brian2007-11-191-2/+3
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| * [intel] Add 965 support to shared intel_blit.cEric Anholt2007-11-1612-75/+119
| | | | | | | | | | This requires that regions grow a marker of whether they are tiled or not, because fence (surface) registers are ignored by the 965 2D engine.
| * [i915] Pass static region names in so debugging says more than "static region".Eric Anholt2007-11-163-12/+17
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| * [intel] Move additional code to be shared from intel_context.h to intel/.Eric Anholt2007-11-164-59/+87
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| * [intel] Move intel_tex.h into place, forgotten in the previous commit.Eric Anholt2007-11-161-0/+0
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| * [965] Add batchbuffer decode for several more packets.Eric Anholt2007-11-161-3/+127
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| * [intel] Fix typos in intel_chipset.h macros.Eric Anholt2007-11-161-6/+6
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| * [i915] Add INTEL_DEBUG=sync debug flag to wait for fences after making them.Eric Anholt2007-11-163-0/+8
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| * [i915] Reenable batchbuffer debug under INTEL_DEBUG=bat.Eric Anholt2007-11-161-4/+4
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| * [intel] Add some doxygen notes on what the bufmgr_fake block members mean.Eric Anholt2007-11-161-2/+11
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| * [intel] Add a simple relocation cache to the fake buffer manager.Eric Anholt2007-11-161-35/+91
| | | | | | | | | | This is required for 965 performance, as it avoids a lot of repeated data uploads of the state caches due to surface offsets in them.
| * [intel] Assert against 0-sized buffers in dri_bufmgr_fake.c.Eric Anholt2007-11-161-0/+4
| | | | | | | | They shouldn't be created, and this often helps catch stupid issues.
| * [intel] Add support for multiple levels of relocation in bufmgr_fake.Eric Anholt2007-11-162-73/+163
| | | | | | | | | | This is required for 965 support, which has relocations in other places than just the batchbuffer.
| * [i915] Push locking in intelClearWithTris down inside meta_draw_poly.Eric Anholt2007-11-162-85/+72
| | | | | | | | | | | | | | | | | | The lock coverage and checks for cliprects were unneeded since the batchbuffer will have INTEL_BATCH_CLIPRECTS anyway. It appeared to be a leftover from intelClearWithBlit. This makes the locking requirements of i915 meta_draw_quad match i965 meta_draw_quad.
| * fix bogus assumption if ddx has set up surface reg for z bufferRoland Scheidegger2007-11-151-2/+1
| | | | | | | | | | | | | | | | this is wrong since even if ddx has not set up a surface reg to cover the z buffer we should pretend it has on those rv100 chips since they presumably do not do z buffer tiling if not using hyperz, so we can use linear addressing just the same. Doesn't seem to fix #13080, but it's wrong anyway and the bug almost certainly broke newer non-tcl chips.
| * fix position invariant vertex programs for sw-tnlRoland Scheidegger2007-11-151-52/+151
| | | | | | | | | | | | do the same math as for fixed function pipe, including user clip planes. (mostly resurrected from the dead t_vb_arbprogram.c code)
| * i965: correct the opcode of XY_SETUP_BLT_CMD. fix bug #12730Xiang, Haihao2007-11-121-1/+1
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| * [i915] Remove old frontbuffer rotation hack.Eric Anholt2007-11-0911-564/+8
| | | | | | | | | | | | This was replaced in previous releases of xserver/dri/libGL by reporting the damage to the frontbuffer so that the server and driver could handle it appropriately.
| * [intel] By default, output batchbuffer decode to stderr like other debug info.Eric Anholt2007-11-091-1/+1
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| * [intel] Initialize a depth buffer if the visual has depth 24 but no stencil.Eric Anholt2007-11-091-15/+28
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| * [intel] Move over files that will be shared with 965-fbo work.Eric Anholt2007-11-0945-8055/+8072
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| * check for texture and renderbuffer in check_end_texture_render()Brian2007-11-091-2/+1
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| * code clean-ups, reformattingBenno Schulenberg2007-11-091-11/+8
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