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* mesa: wrap comments, code to 78 columns in multisample.cBrian Paul2013-06-191-6/+11
| | | | Reviewed-by: Jose Fonseca <[email protected]>
* mesa: remove unused BITSET64 macrosBrian Paul2013-06-191-61/+0
| | | | Reviewed-by: Jose Fonseca <[email protected]>
* gen7: fix GPU hang on WebGL texture-size testJordan Justen2013-06-181-1/+1
| | | | | | | | | | | | | | | | | | When rendering to a texture with BaseLevel set, the miptree may be laid out such that BaseLevel is in level 0 of the miptree (to avoid wasting memory on unused levels between 0 and BaseLevel-1). In that case, we have to shift our render target's level down to the appropriate level of the smaller miptree. The WebGL test in combination with a meta code relating to glGenerateMipmap also triggered a similar failure scenario. This GPU hang regression was introduced by c754f7a8. Bugzilla: http://bugs.freedesktop.org/show_bug.cgi?id=65324 Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Eric Anholt <[email protected]> Reviewed-by: Paul Berry <[email protected]>
* intel: Remove unused IS_POWER_OF_TWO() macro.Eric Anholt2013-06-181-2/+0
| | | | | | The is_power_of_two() inline function has been used instead. Reviewed-by: Matt Turner <[email protected]>
* gallium: add condition parameter to render_conditionRoland Scheidegger2013-06-181-3/+3
| | | | | | | | | | | | | For conditional rendering this makes it possible to skip rendering if either the predicate is true or false, as supported by d3d10 (in fact previously it was sort of implied skip rendering if predicate is false for occlusion predicate, and true for so_overflow predicate). There's no cap bit for this as presumably all drivers could do it trivially (but this patch does not implement it for the drivers using true hw predicates, nvxx, r600, radeonsi, no change is expected for OpenGL functionality). Reviewed-by: Jose Fonseca <[email protected]>
* intel: Allow blorp CopyTexSubImage to nonzero destination slices.Eric Anholt2013-06-173-14/+9
| | | | | Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Paul Berry <[email protected]>
* intel: Allow blit CopyTexSubImage to nonzero destination slices.Eric Anholt2013-06-171-14/+9
| | | | | Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Paul Berry <[email protected]>
* intel: Directly implement blit glBlitFramebuffer instead of awkward reuse.Eric Anholt2013-06-173-70/+72
| | | | | | | | | | This gets us support for blitting to attachment types other than textures. v2: fix up comments from review by Kenneth. Reviewed-by: Kenneth Graunke <[email protected]> Acked-by: Paul Berry <[email protected]>
* intel: Move XRGB->ARGB blit logic into intel_miptree_blit().Eric Anholt2013-06-174-100/+63
| | | | | | | | Now any caller (such as glCopyPixels()) can benefit from it, and it only changes the correct subset of the destination instead of a whole teximage. Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Paul Berry <[email protected]>
* intel: Fix Y tiling support for glCopyTexSubImage's alpha override.Eric Anholt2013-06-171-4/+4
| | | | | | | | | | | Apparently we don't have any piglit tests for this, because it would have assertion failed in a debug build, or just rendered wrong in a non-debug build if the destination wasn't covering whole tiles. v2: Use the new macros. Reviewed-by: Paul Berry <[email protected]> (v1) Reviewed-by: Kenneth Graunke <[email protected]> (v1)
* intel: Make batch macros for doing BCS_SWCTRL setup.Eric Anholt2013-06-171-37/+47
| | | | | | | | | | | | | We're going to add more BCS_SWCTRL setup instances soon, and you have to be careful to have the set and restore atomic with the rendering that's done, so that our state doesn't leak out to other rendering processes. v2: Rewrite the patch to have batch begin/advance macros so that magic numbers don't get sprinkled around (and so you don't mix up your do-I-need-to-reset vs what-do-I-reset-to logic, which I nearly did in the next patch when first writing it) Acked-by: Kenneth Graunke <[email protected]>
* mesa: Hide weirdness of 1D_ARRAY textures from Driver.CopyTexSubImage().Eric Anholt2013-06-177-52/+67
| | | | | | | | | | | | | | | | | Intel had brokenness here, and I'd like to continue moving Mesa toward hiding 1D_ARRAY's ridiculousness inside of the core, like we did with MapTextureImage. Fixes copyteximage 1D_ARRAY on intel. There's still an impedance mismatch in meta when falling back to read and texsubimage, since texsubimage expects coordinates into 1D_ARRAY as (width, slice, 0) instead of (width, 0, slice). v2: Fix offset of scanline reads from the source. (Thanks Brian!), replace dd.h comment with Paul's text and replace early exit with an assert. Reviewed-by: Brian Paul <[email protected]> (v1) Reviewed-by: Kenneth Graunke <[email protected]> (v1) Reviewed-by: Paul Berry <[email protected]> (v1)
* mesa: Fix ieee fp on AlphaSven Joachim2013-06-171-1/+1
| | | | | | | | | | | Commit 1f82bf12ed inadvertently broke it, checking for __IEEE_FLOAT on all Alpha machines instead of only on VMS as before. NOTE: This is a candidate for the 9.1 branch. Reviewed-by: Matt Turner <[email protected]> Reviewed-by: Andreas Boll <[email protected]> Signed-off-by: Sven Joachim <[email protected]>
* i965: Assume flexible hardware primitive restart exists in the future.Kenneth Graunke2013-06-141-1/+1
| | | | | | Primitive restart with an arbitrary cut index was first supported as of Haswell. It's very doubtful that they'd take that away in future hardware, so we may as well alter the check now.
* i965: Shrink Gen5 VUE map layout to be the same as Gen4.Chris Forbes2013-06-166-40/+7
| | | | | | | | | | | | | | | | | | | The PRM suggests a larger layout, mostly to support having gl_ClipDistance[] somewhere predictable for the fixed-function clipper -- but it didn't actually arrive in Gen5. Just use the same layout for both Gen4 and Gen5. No Piglit regressions. Improves performance in CS:S Video Stress Test by ~3%. V2: - Remove now-useless function for determining the SF URB read offset - Remove now-unused BRW_VARYING_SLOT_POS_DUPLICATE Signed-off-by: Chris Forbes <[email protected]> Reviewed-by: Paul Berry <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Implement 16-wide math on G45 and Ironlake.Kenneth Graunke2013-06-162-0/+28
| | | | | | | | [chrisf:] Improves performance in CS:S video stress test by about 2%. No piglit regressions on Ironlake. Reviewed-by: Chris Forbes <[email protected]>
* mesa: Add infrastructure for ARB_shading_language_420pack.Todd Previte2013-06-142-0/+2
| | | | | | | | v2 [mattst88] - Split infrastructure into separate patch. - Add preprocessor #define. Reviewed-by: Kenneth Graunke <[email protected]>
* st/mesa: fix temp texture bindings in st_CopyPixels()Chia-I Wu2013-06-141-17/+13
| | | | | | | | The temporary texture should have either PIPE_BIND_RENDER_TARGET or PIPE_BIND_DEPTH_STENCIL set in addition to PIPE_BIND_SAMPLER_VIEW. Signed-off-by: Chia-I Wu <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* mesa: Fix bug in unclamped float to ubyte conversion.Manfred Ernst2013-06-121-2/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | Problem: The IEEE float optimized version of UNCLAMPED_FLOAT_TO_UBYTE in macros.h computed incorrect results for inputs in the range 0x3f7f0000 (=0.99609375) to 0x3f7f7f80 (=0.99803924560546875) inclusive. 0x3f7f7f80 is the IEEE float value that results in 254.5 when multiplied by 255. With rounding mode "round to closest even integer", this is the largest float in the range 0.0-1.0 that is converted to 254 by the generic implementation of UNCLAMPED_FLOAT_TO_UBYTE. The IEEE float optimized version incorrectly defined the cut-off for mapping to 255 as 0x3f7f0000 (=255.0/256.0). The same bug was present in the function float_to_ubyte in u_math.h. Fix: The proposed fix replaces the incorrect cut-off value by 0x3f800000, which is the IEEE float representation of 1.0f. 0x3f7f7f81 (or any value in between) would also work, but 1.0f is probably cleaner. The patch does not regress piglit on llvmpipe and on i965 on sandy bridge. Tested-by Stéphane Marchesin <[email protected]> Reviewed-by Stéphane Marchesin <[email protected]> Reviewed-by: Brian Paul <[email protected]>
* st/mesa: make generic CopyPixels path work with MSAA visualsMarek Olšák2013-06-131-92/+70
| | | | | | | | | | | | | | We have to use pipe->blit, not resource_copy_region, so that the read buffer is resolved if it's multisampled. I also removed the CPU-based copying, which just did format conversion (obsoleted by the blit). Also, the layer/slice/face of the read buffer is taken into account (this was ignored). Last but not least, the format choosing is improved to take float and integer read buffers into account. Reviewed-by: Brian Paul <[email protected]>
* st/mesa: don't use blit_copy_pixels if an occlusion query is activeMarek Olšák2013-06-131-1/+2
| | | | | | | CopyPixels, just as DrawPixels, should count the samples that passed depth test. Reviewed-by: Brian Paul <[email protected]>
* st/mesa: rework blit_copy_pixels to use pipe->blitMarek Olšák2013-06-131-35/+79
| | | | | | | | | | | | | | | There were 2 issues with it: - resource_copy_region doesn't allow different sample counts of both src and dst, which can occur if we blit between a window and a FBO, and the window has an MSAA colorbuffer and the FBO doesn't. (this was the main motivation for using pipe->blit) - blitting from or to a non-zero layer/slice/face was broken, because rtt_face and rtt_slice were ignored. blit_copy_pixels is now used even if the formats and orientation of framebuffers don't match. Reviewed-by: Brian Paul <[email protected]>
* gallium/util: make WRITES_ALL_CBUFS optional in the passthrough fragment shaderMarek Olšák2013-06-132-2/+4
| | | | Reviewed-by: Brian Paul <[email protected]>
* mesa: fix OES_EGL_image_external being partially allowed in the core profileMarek Olšák2013-06-134-6/+8
| | | | Reviewed-by: Chad Versace <[email protected]>
* glsl: Add gl_shader_program::UniformLocationBaseScaleIan Romanick2013-06-123-3/+21
| | | | | | | | | | | | | | | | This is used by _mesa_uniform_merge_location_offset and _mesa_uniform_split_location_offset to determine how the base and offset are packed. Previously, this value was hard coded as (1U<<16) in those functions via the shift and mask contained therein. The value is still (1U<<16), but it can be changed in the future. The next patch dynamically generates this value. NOTE: This is a candidate for stable release branches. Signed-off-by: Ian Romanick <[email protected]> Reviewed-by: Brian Paul <[email protected]> Reviewed-and-tested-by: Chad Versace <[email protected]>
* glsl: Add a gl_shader_program parameter to ↵Ian Romanick2013-06-124-5/+7
| | | | | | | | | | | | _mesa_uniform_{merge,split}_location_offset This will be used in the next commit. NOTE: This is a candidate for stable release branches. Signed-off-by: Ian Romanick <[email protected]> Reviewed-by: Brian Paul <[email protected]> Reviewed-and-tested-by: Chad Versace <[email protected]>
* i965/gen7: Enable support for fast color clears.Paul Berry2013-06-121-0/+20
| | | | | | | | | | | This patch adds code to place mcs_state into INTEL_MCS_STATE_RESOLVED for miptrees that are capable of supporting fast color clears. This will have no effect on buffers that don't undergo a fast color clear; however, for buffers that do undergo a fast color clear, an MCS miptree will be allocated (at the time of the first fast clear), and will be used thereafter. Reviewed-by: Eric Anholt <[email protected]>
* i965/gen7+: Disable fast color clears on shared regions.Paul Berry2013-06-124-0/+42
| | | | | | | | | | | | | | | | | | | | | | | | In certain circumstances the memory region underlying a miptree is shared with other miptrees, or with other code outside Mesa's control. This happens, for instance, when an extension like GL_OES_EGL_image or GLX_EXT_texture_from_pixmap extension is used to associate a miptree with an image existing outside of Mesa. When this happens, we need to disable fast color clears on the miptree in question, since there's no good synchronization mechanism to ensure that deferred clear writes get performed by the time the buffer is examined from the other miptree, or from outside of Mesa. Fortunately, this should not be a performance hit for most applications, since most applications that use these extensions use them for importing textures into Mesa, rather than for exporting rendered images out of Mesa. So most of the time the miptrees involved will never experience a clear. v2: Rework based on the fact that we have decided not to use an accessor function to protect access to the region. Reviewed-by: Eric Anholt <[email protected]>
* i965/gen7+: Resolve color buffers when necessary.Paul Berry2013-06-127-3/+37
| | | | | | | | | | | | | | | | Resolve color buffers that have been fast-color cleared: 1. before texturing from the buffer (brw_predraw_resolve_buffers()) 2. before using the buffer as the source in a blorp blit (brw_blorp_blit_miptrees()) 3. before mapping the buffer's miptree (intel_miptree_map_raw(), intel_texsubimage_tiled_memcpy()) 4. before accessing the buffer using the hardware blitter (intel_miptree_blit(), do_blit_bitmap()) v2: Rework based on the fact that we have decided not to use an accessor function to protect access to the region. Reviewed-by: Eric Anholt <[email protected]>
* i965/gen7+: Ensure that front/back buffers are fast-clear resolved.Paul Berry2013-06-123-12/+15
| | | | | | | | | | | | We already had code in intel_downsample_for_dri2_flush() for downsampling front and back buffers when multisampling was in use. This patch extends that function to perform fast color clear resolves when necessary. To account for the additional functionality, the function is renamed to simply intel_resolve_for_dri2_flush(). Reviewed-by: Eric Anholt <[email protected]>
* i965/blorp: Write blorp code to do render target resolves.Paul Berry2013-06-126-0/+96
| | | | | | | | | | | | | | | | | | | This patch implements the "render target resolve" blorp operation. This will be needed when a buffer that has experienced a fast color clear is later used for a purpose other than as a render target (texturing, glReadPixels, or swapped to the screen). It resolves any remaining deferred clear operation that was not taken care of during normal rendering. Fortunately not much work is necessary; all we need to do is scale down the size of the rectangle primitive being emitted, run the fragment shader with the "Render Target Resolve Enable" bit set, and ensure that the fragment shader writes to the render target using the "replicated color" message. We already have a fragment shader that does that (the shader that we use for fast color clears), so for simplicity we re-use it. Reviewed-by: Eric Anholt <[email protected]>
* i965/blorp: Expand clear class hierarchy to prepare for RT resolves.Paul Berry2013-06-122-25/+35
| | | | | | | | | | | | | | The fragment shaders that to do color clears will be re-used to perform so-called "render target resolves" (the resolves associated with fast color clears). To prepare for that, this patch expands the class hierarchy for blorp params by adding brw_blorp_const_color_params (which will be used for all blorp operations where the fragment shader outputs a constant color). Some other data structures and functions were also renamed to use "const_color" nomenclature where appropriate. Reviewed-by: Eric Anholt <[email protected]>
* i965/gen7+: Implement fast color clear operation in BLORP.Paul Berry2013-06-129-14/+240
| | | | | | | | | | | | | | | | | | Since we defer allocation of the MCS miptree until the time of the fast clear operation, this patch also implements creation of the MCS miptree. In addition, this patch adds the field intel_mipmap_tree::fast_clear_color_value, which holds the most recent fast color clear value, if any. We use it to set the SURFACE_STATE's clear color for render targets. v2: Flag BRW_NEW_SURFACES when allocating the MCS miptree. Generate a perf_debug message if clearing to a color that isn't compatible with fast color clear. Fix "control reaches end of non-void function" build warning. Reviewed-by: Eric Anholt <[email protected]>
* i965/gen7+: Create helper functions for single-sample MCS buffers.Paul Berry2013-06-122-0/+128
| | | | Reviewed-by: Eric Anholt <[email protected]>
* i965/gen7+: Set up MCS in SURFACE_STATE whenever MCS is present.Paul Berry2013-06-123-5/+7
| | | | | | | | | | | | | | | On Gen7+, MCS buffers are used both for compressed multisampled color buffers and for "fast clear" of single-sampled color buffers. Previous to this patch series, we didn't support fast clear, so we only used MCS with multisampled bolor buffers. As a first step to implementing fast clears, this patch modifies the code that sets up SURFACE_STATE so that it configures the MCS buffer whenever it is present, regardless of whether we are multisampling or not. Reviewed-by: Eric Anholt <[email protected]>
* i965/gen7+: Create an enum for keeping track of fast color clear state.Paul Berry2013-06-126-0/+104
| | | | | | | | | | | | | This patch includes code to update the fast color clear state appropriately when rendering occurs. The state will also need to be updated when a fast clear or a resolve operation is performed; those state updates will be added when the fast clear and resolve operations are added. v2: Create a new function, intel_miptree_used_for_rendering() to handle updating the fast color clear state when rendering occurs. Reviewed-by: Eric Anholt <[email protected]>
* intel: Conditionally compile mcs-related code for i965 only.Paul Berry2013-06-122-1/+9
| | | | | | | | | This patch ifdefs out intel_mipmap_tree::mcs_mt when building the i915 (pre-Gen4) driver (MCS buffers aren't supported until Gen7, so there is no need for this field in the i915 driver). This should make it a bit easier to implement fast color clears without undue risk to i915. Reviewed-by: Eric Anholt <[email protected]>
* intel: Keep region name in intel_miptree_create_for_dri2_buffer().Paul Berry2013-06-121-0/+1
| | | | | | | | | | | | | | | | | | | | | | When processing a buffer received from the X server, intel_process_dri2_buffer() examines intel_region::name to determine whether it's received a brand new buffer, or the same buffer it received from the X server the last time it made a request. However, this didn't work properly, because in the call to intel_miptree_create_for_dri2_buffer(), we create a fresh intel_region object to represent the buffer, and this was causing us to forget the buffer's previous name. This patch fixes things by copying over the region name when creating the fresh intel_region object. At the moment, this is just a minor performance optimization. However, when fast color clears are added, it will be necessary to ensure that the fast color clear state for a buffer doesn't get discarded the next time we receive that buffer from the X server. Reviewed-by: Eric Anholt <[email protected]>
* i965: Emit the depth/stencil state pointer directly, not via atoms.Kenneth Graunke2013-06-117-80/+18
| | | | | | | | | | | | | | | | | | | | | See two commits ago for the rationale. This allows us to delete the whole gen7_cc_state.c file. This does move these commands before the depth stall flushes from brw_emit_depthbuffer, which may be a problem. The documentation for 3DSTATE_DEPTH_BUFFER mentions that depth stall flushes are required before changing any depth/stencil buffer state, but explicitly lists 3DSTATE_DEPTH_BUFFER, 3DSTATE_HIER_DEPTH_BUFFER, 3DSTATE_STENCIL_BUFFER, and 3DSTATE_CLEAR_PARAMS. It does not mention this particular packet (_3DSTATE_DEPTH_STENCIL_STATE_POINTERS). No observed Piglit regressions on Sandybridge or Ivybridge. Together with the last two commits, this makes a cairo-gl benchmark faster by 0.324552% +/- 0.258355% on Ivybridge. No statistically significant change on Sandybridge. (Thanks to Eric for the numbers.) Signed-off-by: Kenneth Graunke <[email protected]>
* i965: Emit the CC state pointer directly rather than via atoms.Kenneth Graunke2013-06-115-30/+18
| | | | | | See the previous commit for the rationale. Signed-off-by: Kenneth Graunke <[email protected]>
* i965: Emit the BLEND_STATE pointer directly rather than via atoms.Kenneth Graunke2013-06-115-30/+18
| | | | | | | | | | | | | | | | | | | | | | | | Previously, we would: 1. Emit the new indirect state. 2. Flag CACHE_NEW_BLEND_STATE. 3. Rely on later state atoms to notice CACHE_NEW_BLEND_STATE and emit a pointer to the new indirect state. This is rather cumbersome: it requires two state atoms instead of one, and there's a strict ordering dependency in the list. Plus, the code gets spread across two functions (or even files in the case of Gen7+). Gen7+ has a packet to update just the blend state pointer, so it makes a lot of sense to simply emit that right away. Gen6 has a combined packet which updates blending, the color calculator, and depth/stencil state; however, each can still be modified independently. This drops the Gen6 micro-optimization where we tried to only emit one packet that changed all three states. State updates are pretty cheap. CACHE_NEW_BLEND_STATE is no longer necessary, so drop it. Signed-off-by: Kenneth Graunke <[email protected]>
* Revert "i965: Disable unused pipeline stages once at startup on Gen7+."Kenneth Graunke2013-06-113-6/+13
| | | | | | | | | | This reverts commit 6c966ccf07bcaf64fba1a9b699440c30dc96e732. Apparently causes GPU hangs. Conflicts: src/mesa/drivers/dri/i965/brw_state.h src/mesa/drivers/dri/i965/brw_state_upload.c
* swrast: add texfetch code for some XBGR formatsBrian Paul2013-06-112-9/+46
| | | | | | | | | | Fixes piglit texture-packed-formats regression. We need to implement more XBGR formats here eventually, but many are UINT/SINT formats which swrast doesn't handle yet anyway (integer textures). Bugzilla https://bugs.freedesktop.org/show_bug.cgi?id=64935 Reviewed-by: Jose Fonseca <[email protected]>
* mesa: add missing texture strings in tex_target_name()Brian Paul2013-06-101-0/+5
| | | | And add a static assert for the future.
* mesa: Add a _mesa_problem to document a piglit failure on i965.Eric Anholt2013-06-101-0/+6
| | | | | | | | | Having figured out what was going on with piglit fbo-depth copypixels GL_DEPTH_COMPONENT32F (falling all the way back to swrast on CopyPixels to a float depth buffer), I'm not inclined to fix the problem currently but it seems worth saving someone else the debug time. Reviewed-by: Matt Turner <[email protected]>
* i965/vs: Avoid the MUL/MACH/MOV sequence for small integer multiplies.Eric Anholt2013-06-101-13/+37
| | | | | | | | | | | | | | | We do a lot of multiplies by 3 or 4 for skinning shaders, and we can avoid the sequence if we just move them into the right argument of the MUL. On pre-IVB, this means reliably putting a constant in a position where it can't be constant folded, but that's still better than MUL/MACH/MOV. Improves GLB 2.7 trex performance by 0.788648% +/- 0.23865% (n=29/30) v2: Fix test for pre-sandybridge. Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Matt Turner <[email protected]> (v1)
* i965/vs: Allow copy propagation into MUL/MACH.Eric Anholt2013-06-101-2/+4
| | | | | | | | | | | This is a trivial port of 1d6ead38042cc0d1e667d8ff55937c1e32d108b1 from the FS. No significant performance difference on trex (misplaced the data, but it was about n=20). Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* i965/vs: Use the MAD instruction when possible.Eric Anholt2013-06-104-0/+43
| | | | | | | | | | | | | | This is different from how we do it in the FS - we are using MAD even when some of the args are constants, because with the relatively unrestrained ability to schedule a MOV to prepare a temporary with that data, we can get lower latency for the sequence of instructions. No significant performance difference on GLB2.7 trex (n=33/34), though it doesn't have that many MADs. I noticed MAD opportunities while reading the code for the DOTA2 bug. Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* intel: Reserve less batchbuffer space.Kenneth Graunke2013-06-101-4/+3
| | | | | | | | | | | | | | | Now that Gen6+ relies on hardware contexts, we don't need to record an occlusion query value at the end of each batch. That means we no longer need to reserve space for the absurd number of PIPE_CONTROLs required to do that on Sandybridge. See commit 4e087de51ad0e7ba4a7199d3664e1d096f8dc510, which bumped this up to 60 bytes. This is not quite a revert, as it uses 24 bytes instead of 16, and saves the comments. As far as I can tell, the old value of 16 bytes was just wrong, so we shouldn't go back to that. Reviewed-by: Eric Anholt <[email protected]> Signed-off-by: Kenneth Graunke <[email protected]>
* i965: Allocate push constant L3 space once at startup on Gen7+.Kenneth Graunke2013-06-104-12/+4
| | | | | | | | | | | We always allocate the maximum amount of space and never change it, so it makes sense to do it once. Programming it on startup also lets us skip re-programming it from BLORP. This removes a tiny amount of overhead from our drawing loop. Reviewed-by: Eric Anholt <[email protected]> Signed-off-by: Kenneth Graunke <[email protected]>
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