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* mesa/st: split updating vertex and fragment shader stages.Dave Airlie2011-05-183-8/+12
| | | | | | | this seems like a logical thing to do and sets the correct st flags for vertex textures. Signed-off-by: Dave Airlie <[email protected]>
* st/mesa: only memset sampler when about to use it.Dave Airlie2011-05-181-3/+2
| | | | | | | | | | | This function was taking a lot more CPU than required due to it memsetting a bunch of memory that didn't require it from what I can see. We should only memset here when we are about to fill out the sampler, otherwise we end up doing a bunch of memsets for everytime this function is called, basically setting 0 memory to 0. Signed-off-by: Dave Airlie <[email protected]>
* i965: Instead of fallback on missing region, just bind a null renderbuffer.Eric Anholt2011-05-172-12/+4
| | | | | | | | | | | | | | The change for GPU hanging in 13bab58f04c1ec6d0d52760eab490a0997d9abe2 fell back even when rb == NULL, which is wrong for GLES2 and caused segfaulting in GLES2 conformance. For the GPU hang case (where the broken 2D driver failed to allocate a BO for the window system renderbuffer), it also would assertion fail/segfault immediately after the fallback setup when the renderbuffer map failed. Fixes GLES2 conformance packed_depth_stencil. Signed-off-by: Eric Anholt <[email protected]> Signed-off-by: Kenneth Graunke <[email protected]>
* i965: Updated fixed-point sizes in Ivybridge SAMPLER_STATE.Kenneth Graunke2011-05-171-3/+3
| | | | | | | | | Texture LOD Bias is now S4.8 instead of S4.6; Min LOD, and Max LOD are now U4.8 instead of U4.6. Fixes piglit test tex-miplevel-selection. Signed-off-by: Kenneth Graunke <[email protected]>
* i965: Ivybridge uses the Gen4 SAMPLER_BORDER_COLOR_STATE.Kenneth Graunke2011-05-171-1/+4
| | | | | | Volume 5c 1.13.7 lists it as [PreDevILK] and [DevIVB+]. Signed-off-by: Kenneth Graunke <[email protected]>
* intel: Recognize new Ivybridge PCI IDs.Kenneth Graunke2011-05-172-2/+22
| | | | | Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* i965: Disable register spilling on Ivybridge for now.Kenneth Graunke2011-05-171-0/+2
| | | | | | | | The data port messages for this are rather different. For now, fail to compile rather than hanging the GPU. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* i965: Fix RNDZ and RNDE on Sandybridge and Ivybridge.Kenneth Graunke2011-05-171-3/+8
| | | | | | | | | | | | | | On gen4/5, the RNDZ and RNDE instructions return floor(x), but set special "round increment bits" in the flag register; a predicated ADD (+1) fixes the result. The documentation still lists '.r' as existing, and says that the predicated add is necessary, but it apparently lies. According to the simulator, BRW_CONDITIONAL_R (7) is not a valid conditional modifier and the RNDZ and RNDE instructions simply produce the correct value. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* i965: Fix data port reads on Ivybridge.Kenneth Graunke2011-05-171-2/+12
| | | | | | | These also need to use gen7_dp. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* i965: Avoid register coalescing away MATH workarounds on Ivybridge.Kenneth Graunke2011-05-171-1/+1
| | | | | | | | The MATH instruction cannot handle source modifiers, even on Gen7. So, apply this workaround for Sandybridge on Ivybridge as well. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* i965: Make the CONT instruction point to the WHILE instruction.Kenneth Graunke2011-05-171-5/+2
| | | | | | | | | | | | This fixes piglit test glsl-fs-loop-continue.shader_test on Ivybridge. According to the documentation, the CONT instruction's UIP field should point to the WHILE instruction on both Sandybridge and Ivybridge. The previous code made UIP point to the implicit DO instruction, which seems incorrect. I'm not sure how it could have worked on Sandybridge. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* i965: Add support for loops on Ivybridge.Kenneth Graunke2011-05-171-3/+18
| | | | | Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* i965: Add support for IF/ELSE/ENDIF control flow on Ivybridge.Kenneth Graunke2011-05-173-8/+40
| | | | | | | | | | Ivybridge's IF instruction doesn't support conditional modifiers. It also introduces UIP, which must point to the ENDIF instruction. ELSE and ENDIF remain the same except that JIP moves from dst to src1. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* i965: Add support for Ivybridge texturing messages.Kenneth Graunke2011-05-172-3/+66
| | | | | | | | | Ivybridge puts the shadow comparator first, then lod/bias, and finally the coordinate---unlike previous generations which always reserved four slots for the coordinate at the beginning. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* i965: Fix sampler message descriptor on Ivybridge.Kenneth Graunke2011-05-172-1/+23
| | | | | Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* i965: Fix SAMPLER_STATE on Ivybridge.Kenneth Graunke2011-05-175-2/+250
| | | | | | | Most of this code copied from brw_wm_sampler_state.c. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* i965: Mark some brw_wm_sampler_state.c helper functions as non-static.Kenneth Graunke2011-05-172-2/+9
| | | | | Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* i965: Update SURFACE_STATE for Ivybridge.Kenneth Graunke2011-05-175-4/+503
| | | | | | | | I'm still not happy with the amount of code duplication here, but it will have to do for now. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* i965: Mark a few more brw_wm_surface_state functions as non-static.Kenneth Graunke2011-05-172-5/+14
| | | | | | | I need to reuse them. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* i965: Change brw_format_for_mesa_format to a non-static function.Kenneth Graunke2011-05-172-55/+63
| | | | | | | This will make it easier to share between files. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* i965: Set Address Modify Enable in VERTEX_BUFFER on Ivybridge.Kenneth Graunke2011-05-172-0/+4
| | | | | | | | Otherwise, Ivybridge seems to ignore the newly supplied data, giving us rubbish for vertices. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* i965: Enable channel masks in Ivybridge's URB_WRITE_HWORD header.Kenneth Graunke2011-05-171-0/+8
| | | | | | | | This shouldn't be done using MRFs, but until I have a proper solution for dealing with MRFs, this allows my hack to keep working. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* i965: Fix the URB write message descriptor on Ivybridge.Kenneth Graunke2011-05-172-2/+29
| | | | | | | The message header is still incorrect, but this is a start. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* i965: Fix render target writes on Ivybridge.Kenneth Graunke2011-05-172-1/+29
| | | | | | | Ivybridge shifts the data port messages by one bit. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* i965: Mad hacks to avoid using MRFs on Ivybridge.Kenneth Graunke2011-05-171-1/+19
| | | | | | | | | | | | | | | | | Ivybridge's SEND instruction uses GRFs instead of MRFs. Unfortunately, a lot of our code explicitly uses MRFs, and rewriting it would take a fair bit of effort. In the meantime, use a hack: - Change brw_set_dest, brw_set_src0, and brw_set_src1 to implicitly convert any MRFs into the top 16 GRFs. - Enable gen6_resolve_implied_move on Ivybridge: Moving g0 to m0 actually moves it to g111 thanks to the previous hack. It remains to officially reserve these registers so the allocator doesn't try to reuse them. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* i965: Emit 3DPRIMITIVE Ivybridge-style.Kenneth Graunke2011-05-172-1/+62
| | | | | Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* i965: Don't use the GS for breaking down quads on Ivybridge.Kenneth Graunke2011-05-172-3/+3
| | | | | Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* i965: Emit extra 0's in 3DSTATE_MULTISAMPLE on Ivybridge.Kenneth Graunke2011-05-171-2/+5
| | | | | Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* i965: Add depth buffer support on Ivybridge.Kenneth Graunke2011-05-176-5/+140
| | | | | | | | This also disables the HiZ and separate stencil buffers. We still need to implement stencil. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* i965: Upload sampler state pointers on Ivybridge.Kenneth Graunke2011-05-174-1/+11
| | | | | | | | Since we currently only support sampling in the fragment shader, we only bother to emit the PS variant. In the future we'll need to emit others. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* i965: Disable binding table pointers for unused pipeline stages.Kenneth Graunke2011-05-172-0/+17
| | | | | | | This may not be necessary, but it seems like a good idea. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* i965: Upload binding table pointers on Ivybridge.Kenneth Graunke2011-05-174-2/+16
| | | | | | | Ivybridge uses per-stage commands to update binding table pointers. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* i965: Split BRW_NEW_BINDING_TABLE dirty bit into one per stage.Kenneth Graunke2011-05-175-15/+27
| | | | | | | | | Ivybridge can update each stage's binding table pointer independently, so we want separate dirty bits. Previous generations can simply subscribe to all three dirty bits and emit as usual. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* i965: Explicitly disable unused pipeline stages on Ivybridge.Kenneth Graunke2011-05-175-1/+141
| | | | | | | This may not be strictly necessary, but seems wise. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* i965: Initial Ivybridge VS state.Kenneth Graunke2011-05-174-1/+96
| | | | | | | | | Copied from gen6_vs_state.c; reuses create_vs_constant_bo from there. The 3DSTATE_VS command is identical but 3DSTATE_CONSTANT_VS is not. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* i965: Initial Ivybridge Viewport state setup.Kenneth Graunke2011-05-176-4/+137
| | | | | | | | | | | SF and CLIP viewport state has been combined into SF_CLIP_VIEWPORT; SF_CLIP and CC state pointers can now be uploaded independently. Some portions of the hardware documentation refer to separate upload commands for SF and CLIP; these are outdated and incorrect. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* i965: Initial Ivybridge Clip state setup.Kenneth Graunke2011-05-175-1/+125
| | | | | | | | | | | Copied from gen6_clip_state.c. This enables early culling and sets the necessary fields. Otherwise, it is entirely the same, so I doubt this patch is strictly necessary for a functional driver. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* i965: Initial Ivybridge CC state setup.Kenneth Graunke2011-05-175-1/+98
| | | | | | | | | The state itself still seems to be the same; the only change is that each part (CC, BLEND, DEPTH_STENCIL) can now be uploaded independently. Thus, we still rely on the code in gen6_cc.c to set up the state. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* i965: Initial Ivybridge WM/PS state setup.Kenneth Graunke2011-05-175-3/+322
| | | | | | | | | | Copied from gen6_wm_state.c. The main change from Sandybridge seems to be that 3DSTATE_WM was split into two separate state packet commands: 3DSTATE_WM and 3DSTATE_PS. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* i965: Initial Ivybridge SF/SBE state setup.Kenneth Graunke2011-05-175-2/+291
| | | | | | | | | | | | Copied from gen6_sf_state.c. The main change from Sandybridge seems to be that 3DSTATE_SF was split into two separate state packet commands: 3DSTATE_SF and 3DSTATE_SBE ("setup backend"). The bit-offsets are even the same - only the DWords numbers have shuffled around a bit. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* i965: Make gen6_sf_state.c's get_attr_override non-static.Kenneth Graunke2011-05-172-1/+5
| | | | | Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* i965: Initial Ivybridge URB space partitioning, including push constants.Kenneth Graunke2011-05-178-4/+162
| | | | | | | | | Currently this always reserves 16kB for push constants, regardless of how much space is needed, and partitions it evenly betwen the VS and FS. This is probably not ideal, but is straightforward. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* i965: Set maximum number of threads for Ivybridge.Kenneth Graunke2011-05-171-1/+11
| | | | | Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* i965: Split out tracked state atoms for Ivybridge.Kenneth Graunke2011-05-171-1/+70
| | | | | | | | Currently, gen7_atoms is a verbatim copy of gen6_atoms; future commits will update it to contain gen7-specific state. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* intel: Initial IS_GEN7 plumbing.Kenneth Graunke2011-05-173-3/+17
| | | | | | | | | Currently, IS_GEN7, IS_IVYBRIDGE, IS_IVB_GT1, and IS_IVB_GT2 all return false. This allows me to write the code for them before actually adding the PCI IDs and thus enabling the hardware. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* i965: Rename max_vs_handles to max_vs_entries for consistency.Kenneth Graunke2011-05-173-6/+6
| | | | | | | | | | | The documentation uses the term "vertex URB entries", the code talks about "entry size", and so on. Also, handles are just "pointers" to entries (actually small integers). Also rename max_gs_handles to max_gs_entries. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* i965: Convert BRW_NEW_* dirty bits to use an enum.Kenneth Graunke2011-05-171-21/+45
| | | | | | | | This will make it much easier to add new dirty bits. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]> Reviewed-by: Chad Versace <[email protected]>
* i965: Rework IF/ELSE jump target back-patching.Kenneth Graunke2011-05-171-114/+144
| | | | | | | | | | | | | | | | | | | | | | | | | The primary motivation for this is to better support Ivybridge control flow. Ivybridge IF instructions need to point to the first instruction of the ELSE block -and- the ENDIF instruction; the existing code only supported back-patching one instruction ago. A second goal is to simplify and centralize the back-patching, hopefully clarifying the code somewhat. Previously, brw_ELSE back-patched the IF instruction, and brw_ENDIF back-patched the previous instruction (IF or ELSE). With this patch, brw_ENDIF is responsible for patching both the IF and (optional) ELSE. To support this, the control flow stack (if_stack) maintains pointers to both the IF and ELSE instructions. Unfortunately, in single program flow (SPF) mode, both were emitted as ADD instructions, and thus indistinguishable. To remedy this, this patch simply emits IF and ELSE, rather than ADDs; brw_ENDIF will convert them to ADDs (the SPF version of back-patching). Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* i965: Move IF stack handling into the EU abstraction layer/brw_compile.Kenneth Graunke2011-05-1710-132/+122
| | | | | | | | This hides the IF stack and back-patching of IF/ELSE instructions from each of the code generators, greatly simplifying the interface. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* i965: Get a ralloc context into brw_compile.Kenneth Graunke2011-05-178-22/+44
| | | | | | | | | | | | This would be so much easier if we were using C++; we could simply use constructors and destructors. Instead, we have to update all the callers. While we're at it, ralloc various brw_wm_compile fields rather than explicitly calloc/free'ing them. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
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