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* i965/gen8+: Remove redundant zeroing of surface stateBen Widawsky2015-11-031-12/+0
* i965/skl: Add GT4 PCI IDsBen Widawsky2015-11-031-1/+5
* mesa: Add spec citations for DispatchCompute*Jordan Justen2015-11-021-5/+29
* mesa: Update DispatchComputeIndirect errors for indirect parameterJordan Justen2015-11-021-6/+5
* i965/fs: Clean up FBH code.Matt Turner2015-11-021-4/+3
* i965/vec4: Clean up FBH code.Matt Turner2015-11-021-13/+5
* i965: Replace default case with list of enum values.Matt Turner2015-11-025-26/+29
* i965/vec4: Don't disable channels in any/all comparisons.Matt Turner2015-11-021-42/+10
* mesa: fix uniforms calculation in glGetProgramivTapani Pälli2015-11-021-2/+12
* mesa: fix program resource queries for atomic counter buffersTapani Pälli2015-11-021-2/+26
* mesa: expose support for OES/EXT_draw_elements_base_vertex to OpenGL ESRyan Houdek2015-11-012-3/+12
* nouveau: set MaxDrawBuffers to the same value as MaxColorAttachmentsIlia Mirkin2015-11-011-1/+1
* mesa/sso: Add compute shader supportJordan Justen2015-11-012-1/+12
* mesa/sso: Add MESA_VERBOSE=api trace supportJordan Justen2015-11-011-0/+33
* i965: Setup pull constant state for compute programsJordan Justen2015-11-014-1/+35
* main/get: Add MAX_COMBINED_COMPUTE_UNIFORM_COMPONENTSJordan Justen2015-11-011-0/+1
* i965/sched: don't calculate live intervals for post-RA schedulingConnor Abbott2015-10-311-1/+2
* i965: Do legacy userclipping in OpenGL ES 1.x contexts.Ian Romanick2015-10-301-1/+2
* i965: enable ARB_shader_clock on gen7+Emil Velikov2015-10-301-0/+1
* i965: Implement nir_intrinsic_shader_clockEmil Velikov2015-10-302-0/+19
* i965/fs: move the fs_reg::smear() from get_timestamp() to the callersEmil Velikov2015-10-301-12/+17
* mesa: add infra for ARB_shader_clockEmil Velikov2015-10-302-0/+2
* main: fix basename match's check if it's an array or structSamuel Iglesias Gonsalvez2015-10-301-1/+2
* i965: Fix invalid memory accesses after resizing brw_codegen's store tableKristian Høgsberg2015-10-301-4/+13
* i965/sched: use liveness analysis for computing register pressureConnor Abbott2015-10-301-56/+229
* i965/fs: split out calculation of payload live rangesConnor Abbott2015-10-302-22/+31
* i965: dump scheduling cycle estimatesConnor Abbott2015-10-304-10/+36
* i965: always run the post-RA schedulerConnor Abbott2015-10-301-2/+1
* i965/sched: write-after-read dependencies are freeConnor Abbott2015-10-301-5/+5
* i965: fix cycle estimates when there's a pipeline stallConnor Abbott2015-10-301-7/+8
* i965: Add INTEL_DEBUG=nocompact to disable instruction compaction.Matt Turner2015-10-293-0/+5
* i965: Add INTEL_DEBUG=hex to print the hex with the disassembly.Matt Turner2015-10-293-1/+3
* i965: Print the type and writemask on null destinations.Matt Turner2015-10-291-1/+1
* i965: Test fixed_hw_reg.file against BRW_IMMEDIATE_VALUE, not IMM.Matt Turner2015-10-291-4/+4
* i965/vec4: Test against BRW_IMMEDIATE_VALUE, not IMM.Matt Turner2015-10-291-1/+1
* i965/fs: Use group(4, 0) to emit an exec-size 4 MOV.Matt Turner2015-10-291-2/+3
* i965/cfg: Handle no-idom case in cfg_t::dump_domtree().Matt Turner2015-10-291-1/+3
* i965/disasm: Remove unused _addr_mode argument from src_ia1().Matt Turner2015-10-291-3/+0
* i965: Set correct field for indirect align16 addrimm.Matt Turner2015-10-291-1/+1
* i965/vec4: Drop brw_set_default_* before popping insn state.Matt Turner2015-10-291-3/+0
* i965/vec4: Remove unnecessary #includes from the generator.Matt Turner2015-10-291-8/+0
* i965/vec4: Eliminate the vec4_generator class altogether.Kenneth Graunke2015-10-291-284/+180
* i965/vec4: Move vec4_generator class definition into the .cpp file.Kenneth Graunke2015-10-292-111/+110
* i965/vec4: Wrap vec4_generator in a C function.Kenneth Graunke2015-10-294-9/+37
* i965/vec4: Convert src_reg/dst_reg to brw_reg at the end of the visitor.Kenneth Graunke2015-10-294-110/+92
* st/mesa: fix mipmap generation for immutable textures with incomplete pyramidsNicolai Hähnle2015-10-291-32/+36
* mesa: Enable ASTC in GLES' [NUM_]COMPRESSED_TEXTURE_FORMATS queriesNanley Chery2015-10-291-22/+63
* mesa/texcompress: Restrict FXT1 format to desktop GL subsetNanley Chery2015-10-291-1/+2
* st/mesa: create temporary textures with the same nr_samples as sourceIlia Mirkin2015-10-291-2/+6
* mesa: add fragdata_arrays list to gl_shaderTapani Pälli2015-10-291-0/+1
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