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| * i965/vec4_nir: Properly handle integer multiplies on BDW+Jason Ekstrand2015-08-101-24/+28
| * i965/vec4_nir: Do boolean source modifier resolves on BDW+Jason Ekstrand2015-08-103-0/+29
| * i965/vec4-nir: Handle boolean resolvese on ILK-Jason Ekstrand2015-08-101-0/+14
| * i965/nir: Don't mark bany or ball instructions for resolveJason Ekstrand2015-08-101-0/+23
| * i965/nir: Use nir_op_info.output_type for determining when to resolveJason Ekstrand2015-08-101-25/+15
| * mesa/format_utils: Add src_bits == dst_bits cases to unorm_to_unormJason Ekstrand2015-08-101-1/+3
| * mesa/es3.1: Allow Multisampled FrameBufferTexturesMarta Lofstedt2015-08-101-2/+3
| * mesa/es3.1: Pass sample count check for multisampled texturesMarta Lofstedt2015-08-101-1/+4
| * mesa: clear existing swizzle info before bitwise-OROded Gabbay2015-08-091-0/+5
| * i965/skl: (trivial) Remove invalid comment about thread countsBen Widawsky2015-08-071-1/+0
| * i965: Fix HW binding tables editingChris Wilson2015-08-071-6/+9
| * mesa: NULL check InfoLogMarta Lofstedt2015-08-071-2/+2
| * i965/vec4: Fix indentation in vec4_visitor::evaluate_spill_costsIago Toral Quiroga2015-08-071-12/+12
| * i965/vec4: do not predicate scratch writes for BRW_OPCODE_SEL instructionsIago Toral Quiroga2015-08-071-1/+2
| * i965: Rename MIPTREE_LAYOUT_ALLOC_* -> MIPTREE_LAYOUT_TILING_*.Matt Turner2015-08-067-20/+20
| * i965: Correct a mistake that always forced texture tiling.Matt Turner2015-08-061-5/+3
| * i965: Request a miptree with no tiling intel_miptree_map_blit().Matt Turner2015-08-061-1/+1
| * st/mesa: implement DrawTransformFeedbackStreamMarek Olšák2015-08-063-31/+34
| * mesa: save which transform feedback buffer is associated with which streamMarek Olšák2015-08-061-0/+5
| * vbo: pass the stream from DrawTransformFeedbackStream to driversMarek Olšák2015-08-0619-26/+39
| * mesa: handle no-op cases sooner in _mesa_[Client]ActiveTexture()Brian Paul2015-08-061-10/+10
| * i965/fs: Lower arithmetic instructions with register regions of unsupported w...Francisco Jerez2015-08-061-0/+62
| * i965/fs: Fix fs_inst::regs_read() for sources in the ATTR file.Francisco Jerez2015-08-061-0/+1
| * i965/fs: Implement nir_op_imul/umul_high in terms of MULH.Francisco Jerez2015-08-061-31/+2
| * i965/fs: Lower the MULH virtual instruction.Francisco Jerez2015-08-061-0/+55
| * i965/fs: Indent the implementation of 32x32-bit MUL lowering by one level.Francisco Jerez2015-08-061-130/+134
| * i965/fs: Lower 32x32 bit multiplication on BXT.Francisco Jerez2015-08-061-2/+2
| * i965: Define virtual instruction to calculate the high 32 bits of a multiply.Francisco Jerez2015-08-066-0/+13
| * mesa: Add missing check of format and type in glTexSubImageXD on GLES 3.0Eduardo Lima Mitev2015-08-051-47/+69
| * mesa: Fix error returned by glCopyTexImage2D() upon an invalid internal formatEduardo Lima Mitev2015-08-051-9/+9
| * mesa: Validate target before resolving tex obj in glTex(ture)SubImageXDEduardo Lima Mitev2015-08-051-15/+14
| * mesa: Fix errors values returned by glShaderBinary()Eduardo Lima Mitev2015-08-051-3/+14
| * mesa: do not modify args when errors with GetProgramResourceNameTapani Pälli2015-08-051-6/+0
| * dri: set the __DRI_API_OPENGL bit based on max gl compat versionFrank Binns2015-08-041-1/+3
| * mesa: Use _mesa_lroundevenf() in some more places.Matt Turner2015-08-041-2/+2
| * i965: Make gen7_upload_ps_state staticIan Romanick2015-08-032-10/+1
| * i965: Remove extern declaration for nonexistent state atomIan Romanick2015-08-031-1/+0
| * i965: Trivial formatting changes in gen7_vs_state.cIan Romanick2015-08-031-5/+5
| * i965: Trivial formatting changes in gen6_multisample_state.cIan Romanick2015-08-031-5/+2
| * i965: Trivial formatting changes in brw_misc_state.cIan Romanick2015-08-031-26/+23
| * i965: Trivial formatting changes in brw_draw_upload.cIan Romanick2015-08-031-3/+6
| * i965: Trivial formatting changes in brw_draw.cIan Romanick2015-08-031-51/+51
| * i965: Trivial formatting changes in brw_wm.cIan Romanick2015-08-031-43/+41
| * i965/nir: Do not scalarize phis in non-scalar setupsIago Toral Quiroga2015-08-031-2/+6
| * i965/vec4: Handle uniform and GRF array access on vertex programs (NIR)Antia Puentes2015-08-031-1/+1
| * i965/nir/vec4: Handle uniforms on vertex programsAntia Puentes2015-08-031-2/+32
| * i965/vec4: Enable NIR-vec4 pass on ARB_vertex_programsAntia Puentes2015-08-031-23/+24
| * i965/nir/gs: Implement support for gl_InvocationID system valueIago Toral Quiroga2015-08-032-0/+29
| * i965/gs/gen6: Refactor ir_emit_vertex and ir_end_primitive for gen6Samuel Iglesias Gonsalvez2015-08-032-1/+14
| * i965/nir/gs: Implement EmitVertex and EndPrimitiveIago Toral Quiroga2015-08-032-0/+23
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