summaryrefslogtreecommitdiffstats
path: root/src/mesa
Commit message (Collapse)AuthorAgeFilesLines
* i965/vec4: Use nir_move_vec_src_uses_to_destJason Ekstrand2015-09-171-0/+3
| | | | | | | | | | | | | | | | | | | The idea here is not that it gives register coalescing a little bit of a helping hand. It doesn't actually fix the coalescing problems, but it seems to help a good bit. Shader-db results for vec4 programs on Haswell: total instructions in shared programs: 1746280 -> 1683959 (-3.57%) instructions in affected programs: 1259166 -> 1196845 (-4.95%) helped: 11363 HURT: 148 v2 (Jason Ekstrand): - Run nir_move_vec_src_uses_to_dest after going out of SSA - New shader-db numbers Reviewed-by: Eduardo Lima Mitev <[email protected]>
* mesa: Fix texture compression on big-endian systemsUlrich Weigand2015-09-174-7/+14
| | | | | | | | | | | | | | | | | | | | | | | Various pieces of code to create compressed textures will first generate an uncompressed RGBA texture into a temporary buffer, and then read from that buffer while creating the final compressed texture in the requested format. The code reading from the temporary buffer assumes the buffer is formatted as an array of bytes in RGBA order. However, the buffer is filled using a _mesa_texstore call with MESA_FORMAT_R8G8B8A8_UNORM format -- this is defined as an array of *integers* holding the RGBA values in packed format (least-significant to most-significant). This means incorrect bytes are accessed on big-endian systems. This patch fixes this by using the MESA_FORMAT_A8B8G8R8_UNORM format instead on big-endian systems when filling the buffer. This fixes about 100 piglit test case failures on s390x for me. Signed-off-by: Ulrich Weigand <[email protected]> Tested-by: Oded Gabbay <[email protected]> Cc: "10.6" "11.0" <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* mesa: return initial value for VALIDATE_STATUS if pipe not boundTapani Pälli2015-09-171-1/+2
| | | | | | | | | | | | | | | | | | From OpenGL 4.5 Core spec (7.13): "If pipeline is a name that has been generated (without subsequent deletion) by GenProgramPipelines, but refers to a program pipeline object that has not been previously bound, the GL first creates a new state vector in the same manner as when BindProgramPipeline creates a new program pipeline object." I interpret this as "If GetProgramPipelineiv gets called without a bound (but valid) pipeline object, the state should reflect initial state of a new pipeline object." This is also expected behaviour by ES31-CTS.sepshaderobjs.PipelineApi conformance test. Signed-off-by: Tapani Pälli <[email protected]> Reviewed-by: Marta Lofstedt <[email protected]>
* mesa: return initial value for PROGRAM_SEPARABLE when not linkedTapani Pälli2015-09-171-1/+2
| | | | | | | | | | | | | | | | | From OpenGL ES 3.1 spec (7.12): "Most properties set within program objects are specified not to take effect until the next call to LinkProgram or ProgramBinary. Some properties further require a successful call to either of these commands before taking effect. GetProgramiv returns the properties currently in effect for program, which may differ from the properties set within program since the most recent call to LinkProgram or ProgramBinary, which have not yet taken effect. If there has been no such call putting changes to pname into effect, initial values are returned." Signed-off-by: Tapani Pälli <[email protected]> Reviewed-by: Marta Lofstedt <[email protected]>
* mesa: enable query of PROGRAM_PIPELINE_BINDING for ES 3.1Tapani Pälli2015-09-171-3/+3
| | | | | | | Specified in OpenGL ES 3.1 spec, Table 23.32: Program Object State. Signed-off-by: Tapani Pälli <[email protected]> Reviewed-by: Marta Lofstedt <[email protected]>
* Revert "mesa/extensions: restrict GL_OES_EGL_image to GLES"Dave Airlie2015-09-171-1/+2
| | | | | | | | | | | | | This reverts commit 48961fa3ba37999a6f8fd812458b735e39604a95. glamor/Xwayland use this, the spec saying something when it was written, and the fact that the comment says Mesa relies on it hasn't changed. I also don't have a copy of this patch in my mail archive, which seems wierd, did it get posted to mesa-dev? Signed-off-by: Dave Airlie <[email protected]>
* st/mesa: avoid integer overflows with buffers >= 512MBIlia Mirkin2015-09-161-2/+2
| | | | | | | | | This fixes failures with the newly-submitted max-size texture buffer piglit test for GPUs exposing >= 128M max texels. Signed-off-by: Ilia Mirkin <[email protected]> Cc: "10.6 11.0" <[email protected]> Reviewed-by: Glenn Kennard <[email protected]>
* mesa: move GL_APPLE_object_purgeable functions to new fileBrian Paul2015-09-165-388/+460
| | | | | | | Move this code out of bufferobj.c since it's not strongly connected to buffer objects. Acked-by: Matt Turner <[email protected]>
* mesa: remove trailing whitespace in bufferobj.cBrian Paul2015-09-161-7/+7
| | | | Trivial.
* mesa: whitespace, line wrap fixes in varray.cBrian Paul2015-09-161-12/+20
| | | | Trivial.
* glsl: shader-enum to name debug fxnsRob Clark2015-09-161-1/+3
| | | | | Signed-off-by: Rob Clark <[email protected]> Reviewed-by: Iago Toral Quiroga <[email protected]>
* i965/fs: The barrier send uses only 1 payload registerJordan Justen2015-09-152-2/+5
| | | | | | | | | | | | | | | | | | | When preparing the barrier payload, the instructions should operate in simd8 mode since we only use 1 payload register. fs_inst::regs_read is also updated to indicate that it only reads one register for SHADER_OPCODE_BARRIER. These issues were flagged by: commit cadd7dd384b33a779d46bd664f456bed4a21a5b7 Author: Jason Ekstrand <[email protected]> Date: Thu Jul 2 15:41:02 2015 -0700 i965/fs: Add a very basic validation pass Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* i965/vec4: Use the replicated fdot instruction in NIRJason Ekstrand2015-09-152-3/+11
| | | | | Reviewed-by: Connor Abbott <[email protected]> Reviewed-by: Eduardo Lima Mitev <[email protected]>
* i965/vec4_nir: Use partial SSA form rather than full non-SSAJason Ekstrand2015-09-153-4/+20
| | | | | | | | | We made this switch in the FS backend some time ago and it seems to make a number of things a bit easier. In particular, supporting SSA values takes very little work in the backend and allows us to take advantage of the majority of the SSA information even after we've gotten rid of Phi nodes. Reviewed-by: Eduardo Lima Mitev <[email protected]>
* i965/fs: Add a very basic validation passJason Ekstrand2015-09-154-0/+69
| | | | | | | | Currently the validation pass only validates that regs_read and regs_written are consistent with the sizes of VGRF's. We can add more as we find it to be useful. Reviewed-by: Matt Turner <[email protected]>
* i965/fs_surface_builder: Only apply predicate to components that existJason Ekstrand2015-09-151-1/+1
| | | | | | | | | | | | In certain conditions, we have to do bounds-checking in the shader for image_load_store. The way this works for image loads is that we do a predicated load and then emit a series of selects, one per component, that gives us 0 or the loaded value depending on whether or not you're in bounds. However, we were hard-coding 4 components which may not be correct. Instead, we should be using size which is the number of components read. Reviewed-by: Francisco Jerez <[email protected]>
* i965/fs: Only read output_components many components when writing an outputJason Ekstrand2015-09-151-1/+3
| | | | Reviewed-by: Kristian Høgsberg <[email protected]>
* i965/fs: Set output_components for lowered clip distance outputsJason Ekstrand2015-09-151-0/+2
| | | | Reviewed-by: Kristian Høgsberg <[email protected]>
* mesa/teximage: restrict GL_ETC1_RGB8_OES support to GLESNanley Chery2015-09-151-1/+2
| | | | | | | | | | | According to the extensions table and our glext headers, OES_compressed_ETC1_RGB8_texture is only supported in GLES1 and GLES2. Since we may give users a GLES3 context when a GLES2 context is requested, we also allow this extension for GLES3 as well. Reviewed-by: Anuj Phogat <[email protected]> Signed-off-by: Nanley Chery <[email protected]>
* mesa/extensions: restrict GL_OES_EGL_image to GLESNanley Chery2015-09-151-2/+1
| | | | | | | | Driver vendors do this as well. The extension specification lists GLES 1.1 or 2.0 as requirements. Reviewed-by: Chad Versace <[email protected]> Signed-off-by: Nanley Chery <[email protected]>
* mesa/extensions: restrict luminance alpha formats to API_OPENGL_COMPATNanley Chery2015-09-152-4/+6
| | | | | | | According the GL 3.1 spec, luminance alpha formats are deprecated. Reviewed-by: Anuj Phogat <[email protected]> Signed-off-by: Nanley Chery <[email protected]>
* i965: Move perf_debug code to brw_codegen_*_prog()Kristian Høgsberg Kristensen2015-09-145-76/+75
| | | | | | | | | | We're trying to avoid a libdrm dependency in the core compiler, so let's move the perf_debug code one level up from the brw_*_emit() helpers to the brw_codegen_*_prog() helpers. Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Jordan Justen <[email protected]> Signed-off-by: Kristian Høgsberg Kristensen <[email protected]>
* i965: Move brw_fs_precompile() to brw_wm.cKristian Høgsberg Kristensen2015-09-142-58/+59
| | | | | | | | | All other precompile functions live in the brw_<stage>.c files, make fs follow the convention. Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Jordan Justen <[email protected]> Signed-off-by: Kristian Høgsberg Kristensen <[email protected]>
* i965: Move compute shader code aroundKristian Høgsberg Kristensen2015-09-145-333/+362
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | This moves the compute shader code around in order to make the way the code is split up more consistent. There should be no functional changes. Typically we have a few files per stage: brw_vs.c, brw_wm.c brw_gs.c: code to drive code generation and implement precompiling and cache search. genX_<stage>_state.c gen specific implementation of the state emission for the shader stage. The brw_*_emit() functions are all in the same files as the visitor classes they use (with the exception of VS, which may use either vec4 or fs). To make compute follow this convention, we move the brw_cs_emit() function into brw_fs.cpp. We can then rename brw_cs.cpp to brw_cs.c and do this in C like the other similar files. Finally, move state setup and atoms to gen7_cs_state.c. Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Jordan Justen <[email protected]> Signed-off-by: Kristian Høgsberg Kristensen <[email protected]>
* meta: Abort meta pbo path if TexSubImage need signed unsigned conversionAnuj Phogat2015-09-141-18/+25
| | | | | | | | | See similar fix for Readpixels in mesa commit 0d20790. Jason suggested we need that for TexSubImage as well. Cc: <[email protected]> Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* i965/vec4_nir: Load constants as integersAntia Puentes2015-09-141-2/+2
| | | | | | | | | | | Loads constants using integer as their register type, like it is done in FS backend. No shader-db changes in HSW. Cc: "10.6 11.0" <[email protected]> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=91716 Reviewed-by: Jason Ekstrand <[email protected]>
* i965/vec4: Fix saturation errors when coalescing registersAntia Puentes2015-09-141-0/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If the register types do not match and the instruction that contains the final destination is saturated, register coalescing generated non-equivalent code. This did not happen when using IR because types usually matched, but it is visible in nir-vec4. For example, mov vgrf7:D vgrf2:D mov.sat m4:F vgrf7:F is coalesced to: mov.sat m4:D vgrf2:D The patch prevents coalescing in such scenario, unless the instruction we want to coalesce into is a MOV (without type conversion implied). In that case, the patch sets the register types to the type of the final destination. Shader-db results in HSW (only vec4 instructions shown): total instructions in shared programs: 1754415 -> 1754416 (0.00%) instructions in affected programs: 74 -> 75 (1.35%) helped: 0 HURT: 1 GAINED: 0 LOST: 0 Only one extra instruction in one of the shaders, that comes from eliminating a saturation error by preventing register coalesce. Cc: "10.6 11.0" <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* st/mesa: emit TXQS, support ARB_shader_texture_image_samplesIlia Mirkin2015-09-132-1/+6
| | | | | | | | | The image component of the ext is a no-op since there is no image support in gallium (yet). Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Edward O'Callaghan <[email protected]> Reviewed-by: Brian Paul <[email protected]>
* i965/nir: Support gl_WorkGroupID variableJordan Justen2015-09-131-1/+9
| | | | | Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Kristian Høgsberg <[email protected]>
* i965/cs: Initialize gl_WorkGroupID variable from payloadJordan Justen2015-09-132-0/+20
| | | | | Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Kristian Høgsberg <[email protected]>
* i965/nir: Support gl_LocalInvocationID variableJordan Justen2015-09-131-0/+17
| | | | | Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Kristian Høgsberg <[email protected]>
* i965/cs: Initialize gl_LocalInvocationID from payloadJordan Justen2015-09-132-2/+24
| | | | | Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Kristian Høgsberg <[email protected]>
* i965/cs: Initialize gl_LocalInvocationID in push constant dataJordan Justen2015-09-131-4/+52
| | | | | Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Kristian Høgsberg <[email protected]>
* i965/cs: Reserve local invocation id in payload regsJordan Justen2015-09-134-0/+45
| | | | | | Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Kristian Høgsberg <[email protected]> Reviewed-by: Iago Toral Quiroga <[email protected]>
* i965/vec4: Don't reswizzle hardware registersJason Ekstrand2015-09-121-0/+8
| | | | | | Cc: "11.0 10.6" <[email protected]> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=91719 Reviewed-by: Kenneth Graunke <[email protected]>
* i965/emit: Add assertions for accumulator restrictionsJason Ekstrand2015-09-121-0/+17
| | | | Reviewed-by: Kenneth Graunke <[email protected]>
* i965/vec4: check writemask when bailing out at register coalesceAlejandro Piñeiro2015-09-111-4/+6
| | | | | | | | | | | | | | | | | | | | | | | opt_register_coalesce stopped to check previous instructions to coalesce with if somebody else was writing on the same destination. This can be optimized to check if somebody else was writing to the same channels of the same destination using the writemask. Shader DB results (taking into account only vec4): total instructions in shared programs: 1781593 -> 1734957 (-2.62%) instructions in affected programs: 1238390 -> 1191754 (-3.77%) helped: 12782 HURT: 0 GAINED: 0 LOST: 0 v2: removed some parenthesis, fixed indentation, as suggested by Matt Turner v3: added brackets, for consistency, as suggested by Eduardo Lima Reviewed-by: Matt Turner <[email protected]>
* i965: Use hash tables for brw_fs_vector_splitting().Kenneth Graunke2015-09-111-22/+22
| | | | | | | | | | | | | | | Cuts compile/link time of the fragment shader in #91857 by 25% (21.64 -> 16.28). v2: Drop unnecessary _mesa_hash_table_destroy call, and use refs.ht->entries == 0 rather than ad-hoc checking (suggested by Timothy Arceri). Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=91857 Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Thomas Helland <[email protected]> Reviewed-by: Timothy Arceri <[email protected]> Tested-by: Tapani Pälli <[email protected]>
* meta: Use result of texture coordinate clamping operationIan Romanick2015-09-101-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | Previously the result of the complicated clamp() expression just dropped on the floor: clamp does not modify any of its parameters. Looking at the surrounding code, I believe this is supposed to modify the value of tex_coord. This change (along with a change to avoid the use of brw_blorp_framebuffer) does not affect any existing piglit tests. I'm not sure what this clamp is trying to accomplish, so I'm not sure how to write a test to exercise this path. I also noticed another bug in this code. There is no way the array texture case could possibly work. This will generate code for the TEXEL_FETCH macro like: #define TEXEL_FETCH(coord) texelFetch(texSampler, ivec3(coord), sample_map[int(2 * fract(coord.x))]); Since the coord parameter of this macro is a vec2 at all invocations, no expansion of this macro will even compile. Signed-off-by: Ian Romanick <[email protected]> Reviewed-by: Anuj Phogat <[email protected]> Cc: Topi Pohjolainen <[email protected]> Cc: Jordan Justen <[email protected]>
* meta: Always bind the textureIan Romanick2015-09-101-3/+6
| | | | | | | | | | | | | | | | We may have been called from glGenerateTextureMipmap with CurrentUnit still set to 0, so we don't know when we can skip binding the texture. Assume that _mesa_BindTexture will be fast if we're rebinding the same texture. v2: Remove currentTexUnitSave because it is now unused. Suggested by both Neil and Anuj. Signed-off-by: Ian Romanick <[email protected]> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=91847 Cc: "11.0" <[email protected]> Reviewed-by: Neil Roberts <[email protected]> Reviewed-by: Anuj Phogat <[email protected]>
* i915, i965: Silence unused parameter warnings in intel_batchbuffer_advanceIan Romanick2015-09-102-0/+4
| | | | | | | | | | | | | These only occurred in release builds, but they occurred in every file that included intel_batchbuffer.h. Lots of spam. :( intel_batchbuffer.h: In function 'intel_batchbuffer_advance': intel_batchbuffer.h:153:47: warning: unused parameter 'brw' [-Wunused-parameter] intel_batchbuffer_advance(struct brw_context *brw) ^ Signed-off-by: Ian Romanick <[email protected]> Reviewed-by: Anuj Phogat <[email protected]>
* i915: Silence unused parameter warning in intel_miptree_create_layoutIan Romanick2015-09-103-15/+5
| | | | | | | | | | | | | | The for_bo parameter of intel_miptree_create_layout appears to be unused since 27eedca when Eric removed some Gen5 code (after the i915 and i965 drivers parted ways). intel_mipmap_tree.c: In function 'old_intel_miptree_create_layout': intel_mipmap_tree.c:77:35: warning: unused parameter 'for_bo' [-Wunused-parameter] bool for_bo) ^ Signed-off-by: Ian Romanick <[email protected]> Reviewed-by: Anuj Phogat <[email protected]>
* i915, i965: Silence unused parameter warnings in intel_miptree_unmap_gttIan Romanick2015-09-102-12/+4
| | | | | | | | | | | | | | | | intel_mipmap_tree.c: In function 'intel_miptree_unmap_gtt': intel_mipmap_tree.c:777:34: warning: unused parameter 'map' [-Wunused-parameter] struct intel_miptree_map *map, ^ intel_mipmap_tree.c:778:17: warning: unused parameter 'level' [-Wunused-parameter] unsigned int level, ^ intel_mipmap_tree.c:779:17: warning: unused parameter 'slice' [-Wunused-parameter] unsigned int slice) ^ Signed-off-by: Ian Romanick <[email protected]> Reviewed-by: Anuj Phogat <[email protected]>
* i915: Silence unused parameter warningsIan Romanick2015-09-103-7/+5
| | | | | | | | | | intel_mipmap_tree.c: In function 'old_intel_miptree_unmap_raw': intel_mipmap_tree.c:726:51: warning: unused parameter 'intel' [-Wunused-parameter] intel_miptree_unmap_raw(struct intel_context *intel, ^ Signed-off-by: Ian Romanick <[email protected]> Reviewed-by: Anuj Phogat <[email protected]>
* i915: Remove prototype for nonexistent brw_miptree_layoutIan Romanick2015-09-101-2/+0
| | | | | | | | Hasn't existed in the i915 source since the i915 and i965 drivers parted ways. Signed-off-by: Ian Romanick <[email protected]> Reviewed-by: Anuj Phogat <[email protected]>
* i965: Make intel_miptree_map_raw staticIan Romanick2015-09-102-19/+17
| | | | | | | | | | This hasn't been used outside intel_mipmap_tree.c since d5d4ba9 started using meta instead of the blitter for PBO TexSubImage. While we're here, remove the unused brw parameter from the function formerly known as intel_miptree_unmap_raw. Signed-off-by: Ian Romanick <[email protected]> Reviewed-by: Anuj Phogat <[email protected]>
* i915, i965: Silence unused parameter warnings in intel_mipmap_tree.hIan Romanick2015-09-102-0/+8
| | | | | | | | | | | | | | | | | | | These only occurred in release builds, but they occurred in every file that included intel_mipmap_tree.h. Lots of spam. :( intel_mipmap_tree.h: In function 'intel_miptree_check_level_layer': intel_mipmap_tree.h:595:59: warning: unused parameter 'mt' [-Wunused-parameter] intel_miptree_check_level_layer(struct intel_mipmap_tree *mt, ^ intel_mipmap_tree.h:596:42: warning: unused parameter 'level' [-Wunused-parameter] uint32_t level, ^ intel_mipmap_tree.h:597:42: warning: unused parameter 'layer' [-Wunused-parameter] uint32_t layer) ^ Signed-off-by: Ian Romanick <[email protected]> Reviewed-by: Anuj Phogat <[email protected]>
* i965: Silence unused parameter warnings in intel_mipmap_tree.cIan Romanick2015-09-103-11/+9
| | | | | | | | | | | | | | | | | | | | | | The target parameter of compute_msaa_layout appears to be unused since 83b83fb when support for CMS textures was added for Gen7. The brw parameter of intel_get_non_msrt_mcs_alignment appears to be unused since e92fbdc when the GEN check (along with the "can we fast clear" decision) was moved to a different function. intel_mipmap_tree.c: In function 'compute_msaa_layout': intel_mipmap_tree.c:62:73: warning: unused parameter 'target' [-Wunused-parameter] compute_msaa_layout(struct brw_context *brw, mesa_format format, GLenum target, ^ intel_mipmap_tree.c: In function 'intel_get_non_msrt_mcs_alignment': intel_mipmap_tree.c:143:54: warning: unused parameter 'brw' [-Wunused-parameter] intel_get_non_msrt_mcs_alignment(struct brw_context *brw, ^ Signed-off-by: Ian Romanick <[email protected]> Reviewed-by: Anuj Phogat <[email protected]> Cc: Ben Widawsky <[email protected]>
* i965: Silence unused parameter warnings in intel_fbo.cIan Romanick2015-09-101-3/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | intel_fbo.c: In function 'intel_alloc_window_storage': intel_fbo.c:415:48: warning: unused parameter 'ctx' [-Wunused-parameter] intel_alloc_window_storage(struct gl_context * ctx, struct gl_renderbuffer *rb, ^ intel_fbo.c: In function 'intel_nop_alloc_storage': intel_fbo.c:428:74: warning: unused parameter 'rb' [-Wunused-parameter] intel_nop_alloc_storage(struct gl_context * ctx, struct gl_renderbuffer *rb, ^ intel_fbo.c:429:32: warning: unused parameter 'internalFormat' [-Wunused-parameter] GLenum internalFormat, GLuint width, GLuint height) ^ intel_fbo.c:429:55: warning: unused parameter 'width' [-Wunused-parameter] GLenum internalFormat, GLuint width, GLuint height) ^ intel_fbo.c:429:69: warning: unused parameter 'height' [-Wunused-parameter] GLenum internalFormat, GLuint width, GLuint height) ^ intel_fbo.c: In function 'intel_blit_framebuffer_with_blitter': intel_fbo.c:790:61: warning: unused parameter 'filter' [-Wunused-parameter] GLbitfield mask, GLenum filter) ^ Signed-off-by: Ian Romanick <[email protected]> Reviewed-by: Anuj Phogat <[email protected]>
* st/mesa: set the vbuffer to NULL if we are skipping itDave Airlie2015-09-111-1/+5
| | | | | | | | | | | | If we skip a vbuffer we need to make sure we NULL out the contents, otherwise when it gets passed to the driver it will get confused. This was hit by: GL41-CTS.gpu_shader_fp64.varyings Reviewed-by: Marek Olšák <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-29 19:12:24 +0000