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* glsl: remove needless conditionalBrian Paul2011-01-261-14/+10
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* glsl: move ir_var_out codeBrian Paul2011-01-261-7/+7
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* glsl: move ir_var_system_value codeBrian Paul2011-01-261-5/+5
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* glsl: use local var to simplify code a bitBrian Paul2011-01-261-22/+23
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* mesa: Propagate gl_FragDepth layout from GLSL IR to Mesa IRChad Versace2011-01-261-0/+23
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* ir_to_mesa: Add several assertions about sizes of arraysIan Romanick2011-01-251-0/+4
| | | | | Both of these assertions are triggered by the test case in bugzilla size of 0.
* ra: Use the same context when realloc'ing arrays.Kenneth Graunke2011-01-211-2/+2
| | | | | | The original allocations use regs->regs as the context, so talloc will happily ignore the context given here. Change it to match to clarify that it isn't changing.
* ra: Take advantage of the adjacency list in finding a node to spill.Eric Anholt2011-01-181-6/+6
| | | | | | | | This revealed a bug in ra_get_spill_benefit where we only considered the benefit of the first adjacency we were to remove, explaining some of the ugly spilling I've seen in shaders. Because of the reduced spilling, it reduces the runtime of glsl-fs-convolution-1 36.9% +/- 0.9% (n=5).
* ra: Remove unused "name" field in regs.Eric Anholt2011-01-181-1/+0
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* ra: Take advantage of the adjacency list in ra_select() too.Eric Anholt2011-01-181-5/+6
| | | | Reduces runtime of glsl-fs-convolution-1 another 13.9% +/- 0.6% (n=5).
* ra: Add an adjacency list to trade space for time in ra_simplify().Eric Anholt2011-01-181-14/+21
| | | | | | This was recommended in the original paper, but I figued "make it run" before "make it fast". Now we make it fast. Reduces the runtime of glsl-fs-convolution-1 by 12.7% +/- 0.6% (n=5).
* ra: Trade off some space to get time efficiency in ra_set_finalize().Eric Anholt2011-01-181-6/+32
| | | | | | | | | | | | | | | | | Our use of the register allocator in i965 is somewhat unusual. Whereas most architectures would have a smaller set of registers with fewer register classes and reuse that across compilation, we have 1, 2, and 4-register classes (usually) and a variable number up to 128 registers per compile depending on how many setup parameters and push constants are present. As a result, when compiling large numbers of programs (as with glean texCombine going through ff_fragment_shader), we spent much of our CPU time in computing the q[] array. By keeping a separate list of what the conflicts are for a particular reg, we reduce glean texCombine time 17.0% +/- 2.3% (n=5). We don't expect this optimization to be useful for 915, which will have a constant register set, but it would be useful if we were switch to this register allocator for Mesa IR.
* Merge branch 'draw-instanced'Brian Paul2011-01-154-0/+15
|\ | | | | | | | | | | | | | | Conflicts: src/gallium/auxiliary/draw/draw_llvm.c src/gallium/drivers/llvmpipe/lp_state_fs.c src/glsl/ir_set_program_inouts.cpp src/mesa/tnl/t_vb_program.c
| * mesa: implement system values in program interpreterBrian Paul2010-12-102-0/+5
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| * mesa: ir_to_mesa support for system valuesBrian Paul2010-12-081-0/+5
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| * mesa: program printing for PROGRAM_SYSTEM_VALUEBrian Paul2010-12-081-0/+5
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* | ir_to_mesa: Fix segfaults on ir_to_mesa invocation after MSVC change.Eric Anholt2011-01-141-6/+6
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* | mesa: Dynamically allocate acp array in ir_to_mesa_visitor::copy_propagate.Vinson Lee2011-01-141-2/+4
| | | | | | | | | | | | | | | | | | | | Fixes these MSVC errors. ir_to_mesa.cpp(2644) : error C2057: expected constant expression ir_to_mesa.cpp(2644) : error C2466: cannot allocate an array of constant size 0 ir_to_mesa.cpp(2644) : error C2133: 'acp' : unknown size ir_to_mesa.cpp(2646) : error C2070: 'ir_to_mesa_instruction *[]': illegal sizeof operand ir_to_mesa.cpp(2709) : error C2070: 'ir_to_mesa_instruction *[]': illegal sizeof operand ir_to_mesa.cpp(2718) : error C2070: 'ir_to_mesa_instruction *[]': illegal sizeof operand
* | mesa: Add channel-wise copy propagation to ir_to_mesa.Eric Anholt2011-01-141-0/+129
| | | | | | | | | | | | | | | | This catches more opportunities than the prog_optimize.c code on openarena's fixed function shaders turned to GLSL, mostly due to looking at multiple source instructions for copy propagation opportunities. It should also be much more CPU efficient than prog_optimize.c's code.
* | mesa: Include mfeatures.h in program.c.Vinson Lee2011-01-091-0/+1
| | | | | | | | Include mfeatures.h for feature tests.
* | glsl: Support if-flattening beyond a given maximum nesting depth.Kenneth Graunke2010-12-271-1/+1
| | | | | | | | | | | | | | | | | | | | | | This adds a new optional max_depth parameter (defaulting to 0) to lower_if_to_cond_assign, and makes the pass only flatten if-statements nested deeper than that. By default, all if-statements will be flattened, just like before. This patch also renames do_if_to_cond_assign to lower_if_to_cond_assign, to match the new naming conventions.
* | mesa: Clean up header file inclusion in prog_statevars.h.Vinson Lee2010-12-181-1/+3
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* | mesa: more program debug codeBrian Paul2010-12-141-0/+12
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* | mesa: Clean up header file inclusion in prog_optimize.h.Vinson Lee2010-12-141-1/+2
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* | mesa: Clean up header file inclusion in prog_cache.h.Vinson Lee2010-12-141-1/+2
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* | mesa: Clean up header file inclusion in nvvertparse.h.Vinson Lee2010-12-141-1/+4
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* | ir_to_mesa: Don't generate swizzles for record derefs of non-scalar/vectorsIan Romanick2010-12-131-1/+7
| | | | | | | | | | | | | | | | This is the same as what the array dereference handler does. Fixes piglit test glsl-link-struct-array (bugzilla #31648). NOTE: This is a candidate for the 7.9 and 7.10 branches.
* | mesa: Clean up header file inclusion in nvfragparse.h.Vinson Lee2010-12-111-1/+4
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* | mesa: Clean up header file inclusion in ir_to_mesa.h.Vinson Lee2010-12-111-2/+5
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* | mesa: Clean up header file inclusion in arbprogparse.h.Vinson Lee2010-12-091-1/+5
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* | symbol_table: Add support for adding a symbol at top-level/global scope.Kenneth Graunke2010-12-062-5/+84
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* | mesa: Bump the number of bits in the register index.José Fonseca2010-12-061-1/+1
| | | | | | | | | | | | More than 1023 temporaries were being used for a Cinebench shader before doing temporary optimization, causing the index value to wrap around to -1024.
* | mesa: update comments, remove dead codeBrian Paul2010-12-031-3/+3
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* | mesa: remove unneeded castBrian Paul2010-12-031-1/+1
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* | mesa, st/mesa: fix gl_FragCoord with FBOs in GalliumMarek Olšák2010-12-032-0/+23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | gl_FragCoord.y needs to be flipped upside down if a FBO is bound. This fixes: - piglit/fbo-fragcoord - https://bugs.freedesktop.org/show_bug.cgi?id=29420 Here I add a new program state STATE_FB_WPOS_Y_TRANSFORM, which is set based on whether a FBO is bound. The state contains a pair of transformations. It can be either (XY=identity, ZW=transformY) if a FBO is bound, or (XY=transformY, ZW=identity) otherwise, where identity = (1, 0), transformY = (-1, height-1). A classic driver (or st/mesa) may, based on some other state, choose whether to use XY or ZW, thus negate the conditional "if (is a FBO bound) ...". The reason for this is that a Gallium driver is allowed to only support WPOS relative to either the lower left or the upper left corner, so we must flip the Y axis accordingly again. (the "invert" parameter in emit_wpos_inversion) NOTE: This is a candidate for the 7.9 branch. Signed-off-by: Marek Olšák <[email protected]> Signed-off-by: Brian Paul <[email protected]>
* | glsl: Lower ir_binop_pow to a sequence of EXP2 and LOG2Ian Romanick2010-12-011-2/+3
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* | glsl: Add a lowering pass to move discards out of if-statements.Kenneth Graunke2010-12-011-1/+3
| | | | | | | | | | | | | | This should allow lower_if_to_cond_assign to work in the presence of discards, fixing bug #31690 and likely #31983. NOTE: This is a candidate for the 7.9 branch.
* | ir_to_mesa: Add support for conditional discards.Marek Olšák2010-12-011-2/+7
|/ | | | | | | NOTE: This is a candidate for the 7.9 branch. Signed-off-by: Marek Olšák <[email protected]> Signed-off-by: Kenneth Graunke <[email protected]>
* glsl: start restoring some geometry shader codeBrian Paul2010-11-231-0/+11
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* glsl: better handling of linker failuresBrian Paul2010-11-231-19/+33
| | | | | Upon link error, exit translation loop, free program instructions. Check for null pointers in calling code.
* mesa: replace #defines with new gl_shader_type enumBrian Paul2010-11-232-2/+2
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* mesa: _mesa_valid_register_index() to validate register indexesBrian Paul2010-11-232-0/+103
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* mesa: rename, make _mesa_register_file_name() non-staticBrian Paul2010-11-232-11/+12
| | | | Plus remove unused parameter.
* glsl: use gl_register_file in a few placesBrian Paul2010-11-231-4/+4
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* glsl: fix off by one in register index assertionBrian Paul2010-11-231-1/+1
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* ir_to_mesa: Detect and emit MOV_SATs for saturate constructs.Eric Anholt2010-11-191-0/+32
| | | | | The goal here is to avoid regressing performance on ir_to_mesa drivers for fixed function fragment shaders requiring saturates.
* glsl: Combine many instruction lowering passes into one.Kenneth Graunke2010-11-191-3/+2
| | | | | | | This should save on the overhead of tree-walking and provide a convenient place to add more instruction lowering in the future. Signed-off-by: Ian Romanick <[email protected]>
* glsl: Add ir_quadop_vector expressionIan Romanick2010-11-191-0/+132
| | | | | | | | | | The vector operator collects 2, 3, or 4 scalar components into a vector. Doing this has several advantages. First, it will make ud-chain tracking for components of vectors much easier. Second, a later optimization pass could collect scalars into vectors to allow generation of SWZ instructions (or similar as operands to other instructions on R200 and i915). It also enables an easy way to generate IR for SWZ instructions in the ARB_vertex_program assembler.
* glsl: Eliminate assumptions about size of ir_expression::operandsIan Romanick2010-11-191-1/+1
| | | | This may grow in the near future.
* glsl: Add ir_unop_sin_reduced and ir_unop_cos_reducedIan Romanick2010-11-191-0/+110
| | | | | | | | | | | | The operate just like ir_unop_sin and ir_unop_cos except that they expect their inputs to be limited to the range [-pi, pi]. Several GPUs require this limited range for their sine and cosine instructions, so having these as operations (along with a to-be-written lowering pass) helps this architectures. These new operations also matche the semantics of the GL_ARB_fragment_program SCS instruction. Having these as operations helps in generating GLSL IR directly from assembly fragment programs.
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