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* mesa: Add a convenience interface for register allocator conflicts setup.Eric Anholt2011-08-101-0/+21
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* ra: Add ra_set_node_reg()Tom Stellard2011-04-301-4/+24
| | | | | | | | This function can be used to avoid creating single register classes for input/payload registers. This makes optimistic coloring less likely to fail. Reviewed-by: Eric Anholt <[email protected]>
* mesa: Add a bunch of documentation to the register allocator.Eric Anholt2011-04-291-3/+65
| | | | Reviewed-by: Kenneth Graunke <[email protected]>
* Convert everything from the talloc API to the ralloc API.Kenneth Graunke2011-01-311-20/+17
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* ra: Use the same context when realloc'ing arrays.Kenneth Graunke2011-01-211-2/+2
| | | | | | The original allocations use regs->regs as the context, so talloc will happily ignore the context given here. Change it to match to clarify that it isn't changing.
* ra: Take advantage of the adjacency list in finding a node to spill.Eric Anholt2011-01-181-6/+6
| | | | | | | | This revealed a bug in ra_get_spill_benefit where we only considered the benefit of the first adjacency we were to remove, explaining some of the ugly spilling I've seen in shaders. Because of the reduced spilling, it reduces the runtime of glsl-fs-convolution-1 36.9% +/- 0.9% (n=5).
* ra: Remove unused "name" field in regs.Eric Anholt2011-01-181-1/+0
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* ra: Take advantage of the adjacency list in ra_select() too.Eric Anholt2011-01-181-5/+6
| | | | Reduces runtime of glsl-fs-convolution-1 another 13.9% +/- 0.6% (n=5).
* ra: Add an adjacency list to trade space for time in ra_simplify().Eric Anholt2011-01-181-14/+21
| | | | | | This was recommended in the original paper, but I figued "make it run" before "make it fast". Now we make it fast. Reduces the runtime of glsl-fs-convolution-1 by 12.7% +/- 0.6% (n=5).
* ra: Trade off some space to get time efficiency in ra_set_finalize().Eric Anholt2011-01-181-6/+32
| | | | | | | | | | | | | | | | | Our use of the register allocator in i965 is somewhat unusual. Whereas most architectures would have a smaller set of registers with fewer register classes and reuse that across compilation, we have 1, 2, and 4-register classes (usually) and a variable number up to 128 registers per compile depending on how many setup parameters and push constants are present. As a result, when compiling large numbers of programs (as with glean texCombine going through ff_fragment_shader), we spent much of our CPU time in computing the q[] array. By keeping a separate list of what the conflicts are for a particular reg, we reduce glean texCombine time 17.0% +/- 2.3% (n=5). We don't expect this optimization to be useful for 915, which will have a constant register set, but it would be useful if we were switch to this register allocator for Mesa IR.
* mesa: move declaration before codeBrian Paul2010-10-221-1/+2
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* i965: Add support for register spilling.Eric Anholt2010-10-211-0/+63
| | | | | It can be tested with if (0) replaced with if (1) to force spilling for all virtual GRFs. Some simple tests work, but large texturing tests fail.
* ra: First cut at a graph-coloring register allocator for mesa.Eric Anholt2010-09-291-0/+361
Notably missing is choice of registers to spill.
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