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According to the Intel Software Development Manual (Volume 1: Basic
Architecture, 12.10.3 Streaming Load Hint Instruction):
Streaming loads may be weakly ordered and may appear to software to
execute out of order with respect to other memory operations.
Software must explicitly use fences (e.g. MFENCE) if it needs to
preserve order among streaming loads or between streaming loads and
other memory operations.
That is, a memory fence is needed to preserve the order between the GPU
writing the buffer and the streaming loads reading it back.
Reported-by: Joseph Nuzman <[email protected]>
Reviewed-by: Jordan Justen <[email protected]>
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This reverts commit 8d3f739383fbdf671752fdec707f1c2b9b2aa6a3.
In the last commit we've updated our check to determine if the actual
code is buildable, rather than if the compiler acknowledges the option.
I.e. did anyone provide -mno-sse4.1 vs is my compiler too old.
Now this code will never be attemped to be build, in both cases.
Confirmed by building mesa with
export CFLAGS='-march=native -mno-sse4.1'
./configure && make
Tested-by: David Heidelberg <[email protected]>
Reviewed-by: Matt Turner <[email protected]>
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Because people insist on doing things like explicitly disabling SSE 4.1.
Cc: "10.0 10.1" <[email protected]>
Tested-by: David Heidelberger <[email protected]>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=71547
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Uses SSE 4.1's MOVNTDQA instruction (streaming load) to read from
uncached memory without polluting the cache.
Reviewed-by: Chad Versace <[email protected]>
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