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* i965: add 2xMSAA 16xMSAA modes to DRI configs.Kevin Rogovin2017-08-301-5/+18
| | | | | | | | | | | For Gen8, add 2xMSAA. For Gen9, add 2xMSAA and 16xMSAA. Special thanks to Eero Tamminen for reporting rasterizer numbers being twice what it should be for 2xMSAA under a benchmark. V2: Make pointer name less ugly + add 2xMSAA for Gen8 Reviewed-by: Kenneth Graunke <[email protected]>
* Revert "i965: add 2xMSAA and 16xMSAA to DRI configs for Gen9."Kenneth Graunke2017-08-301-10/+3
| | | | | | | | | This reverts commit f6d38785e8b28a6dd303884798b823e289817741. Kevin's original patch accidentally didn't add 2x for Gen8; he sent a v2 with a bunch of style fixes shortly after I pushed the original patch, not knowing it was coming. Let's just revert this one, apply v2, and move on.
* i965: Bump the initial program cache size from 4kB to 16kB.Kenneth Graunke2017-08-291-1/+1
| | | | | | | | | | | | | | | | Our initial size of 4kB is way too small to do anything useful, so we end up growing it at least a few times. We may as well start it larger. Some data points: - Dinoshade (from Mesa Demos): hit 8kB. - Chromium 60: hit 16kB after browsing a few things in Google Docs. - GFXBench4 TRex/Manhattan 3.1: hit 128kB - Unigine Valley 1.0: hit 512kB It might make sense to start it even larger. Acked-by: Matt Turner <[email protected]>
* i965: Issue performance warnings when growing the program cacheKenneth Graunke2017-08-291-0/+3
| | | | | | | This involves a bunch of unnecessary copying, a batch flush, and state re-emission. Reviewed-by: Matt Turner <[email protected]>
* i965: add 2xMSAA and 16xMSAA to DRI configs for Gen9.Kevin Rogovin2017-08-291-3/+10
| | | | | | | | | Special thanks to Eero Tamminen for reporting rasterizer numbers being twice what it should be for 2xMSAA under a benchmark. Signed-off-by: Kevin Rogovin <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Add $(WNO_OVERRIDE_INIT) to AM_CFLAGSMatt Turner2017-08-291-0/+1
| | | | | | | | brw_surface_formats.c and genX_blorp_exec.c do this a lot, causing lots of warnings from clang. Reviewed-by: Emil Velikov <[email protected]> Reviewed-by: Eric Engestrom <[email protected]>
* i965: Mark functions used conditionally as UNUSEDMatt Turner2017-08-292-3/+3
| | | | | | | | The functions we're marking as UNUSED in genX_state_upload.c are used only when compiling for particular generations. Reviewed-by: Emil Velikov <[email protected]> Reviewed-by: Eric Engestrom <[email protected]>
* i965: Explicitly cast between different enumsMatt Turner2017-08-291-4/+4
| | | | | | | | | | | | | Fixes warnings like warning: implicit conversion from enumeration type 'enum isl_format' to different enumeration type 'enum GEN10_SURFACE_FORMAT' [-Wenum-conversion] .SourceElementFormat = ISL_FORMAT_R32_UINT, ^~~~~~~~~~~~~~~~~~~ Reviewed-by: Emil Velikov <[email protected]> Reviewed-by: Eric Engestrom <[email protected]>
* i965: Remove some 'inline' keywordsMatt Turner2017-08-291-7/+7
| | | | | | | | | brw_texture_view_sane() is only used by an assert()... No difference in the resulting binary with gcc-6.3.0 or clang-4.0. Reviewed-by: Emil Velikov <[email protected]> Reviewed-by: Eric Engestrom <[email protected]>
* i965: Fix whitespace issues in intel_buffer_objects.c.Kenneth Graunke2017-08-281-31/+29
| | | | Convert tabs to spaces and rewrap one long line.
* i965: Use GEN_GEN and GEN_IS_HASWELL in genX_state_upload.c code.Kenneth Graunke2017-08-251-4/+4
| | | | | | | | We were using brw->gen, brw->is_haswell, and devinfo->gen in a few places, when we could just use GEN_GEN and GEN_IS_HASWELL, which are evaluated at compile time. Reviewed-by: Eduardo Lima Mitev <[email protected]>
* mesa: Implement GL_ARB_polygon_offset_clampAdam Jackson2017-08-251-1/+1
| | | | | | | | | | | Semantically identical to the EXT version (whose string is still valid for GLES), so rename the bit but expose both extension strings. (Suggested by Ilia Mirkin and Ian Romanick.) v3: Fix the entrypoint alias in GL4x.xml (Ilia) Signed-off-by: Adam Jackson <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* mesa: Implement GL_ARB_texture_filter_anisotropicAdam Jackson2017-08-253-0/+3
| | | | | | | | | | | The only difference from the EXT version is bumping the minmax to 16, so just hit all the drivers at once. v2: Fix driver names, add to 17.3 release notes (Ilia Mirkin) Reviewed-by: Ilia Mirkin <[email protected]> Signed-off-by: Adam Jackson <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965: add missing `const` in function signatureEric Engestrom2017-08-241-1/+1
| | | | | | | | | | | | | Gets rid of a few warnings of the form: src/mesa/drivers/dri/i965/intel_screen.c:918:49: warning: passing argument 2 of ‘modifier_is_supported’ discards ‘const’ qualifier from pointer target type [-Wdiscarded-qualifiers] !modifier_is_supported(&screen->devinfo, f, 0, modifier)) ^ src/mesa/drivers/dri/i965/intel_screen.c:301:1: note: expected ‘struct intel_image_format *’ but argument is of type ‘const struct intel_image_format *’ Fixes: 1efd73df39b39589d26f "i965: Advertise the CCS modifier" Cc: Ben Widawsky <[email protected]> Signed-off-by: Eric Engestrom <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* i965: Stop using wm_prog_data->binding_table.render_target_start.Kenneth Graunke2017-08-231-7/+3
| | | | | | | | | | | | | Render target surfaces always start at binding table index 0. This is required for us to use headerless FB writes, which we really want to do. So, we'll never change that. Given that, it's not necessary to look up a wm_prog_data field which we already know contains 0. We can drop the dependency in brw_renderbuffer_surfaces (Gen4-5)...which was already confusingly missing from gen6_renderbuffer_surfaces. Reviewed-by: Topi Pohjolainen <[email protected]>
* i965: Add a brw_wm_prog_data::has_render_target_reads field.Kenneth Graunke2017-08-231-4/+2
| | | | | | | State upload code should use prog_data rather than poking at shader_info directly. Reviewed-by: Topi Pohjolainen <[email protected]>
* i965: Inline brw_update_renderbuffer_surfaces().Kenneth Graunke2017-08-232-38/+20
| | | | | | Less baklava layers. Reviewed-by: Topi Pohjolainen <[email protected]>
* i965: Pass fb into emit_null_surface instead of dimensions.Kenneth Graunke2017-08-231-16/+12
| | | | | | | We either want the framebuffer dimensions or 1x1x1. Passing fb and falling back to 1x1x1 lets us shorten some calls. Reviewed-by: Topi Pohjolainen <[email protected]>
* i965: Devirtualize update_renderbuffer_surface.Kenneth Graunke2017-08-234-30/+5
| | | | | | Replace piles of my own boilerplate with 1-2 lines of code. Reviewed-by: Topi Pohjolainen <[email protected]>
* i965: Delete update_renderbuffer_surface flags.Kenneth Graunke2017-08-232-21/+5
| | | | | | | | | We don't need yet another set of flags. The function already has access to both brw and the unit, so it can check brw->draw_aux_buffer_disabled itself in one line of code. The layered flag was only used to assert that Gen4-5 doesn't do layered rendering, which isn't that useful. Reviewed-by: Topi Pohjolainen <[email protected]>
* i965: Make brw_update_renderbuffer_surface static.Kenneth Graunke2017-08-232-11/+6
| | | | | | | | Also rename it to gen6_update_renderbuffer_surface, as this is the function for Gen6+. Having functions named "brw_*" and "gen4_*" is confusing...if we're using gens, let's stick with those. Reviewed-by: Topi Pohjolainen <[email protected]>
* i965: Drop BRW_NEW_BLORP from SURFACE_STATE setup code.Kenneth Graunke2017-08-235-29/+1
| | | | | | | BLORP invalidates the binding tables, but it doesn't destroy any of the existing SURFACE_STATE entries in the statebuffer. We can reuse those. Reviewed-by: Jason Ekstrand <[email protected]>
* i965: Make a BRW_NEW_FAST_CLEAR_COLOR dirty bit.Kenneth Graunke2017-08-238-5/+25
| | | | | | | | | | | | | | | | | | | When changing fast clear colors, we need to emit new SURFACE_STATE with the updated color at the next draw call. Most things work today because the atoms that handle SURFACE_STATE for images (mutable images, textures, render targets) also listen to BRW_NEW_BLORP, causing us to re-emit these on every BLORP operation. However, this is overkill - most BLORP operations don't require us to re-emit SURFACE_STATE. One case where this is broken today is a fast clear to a different color followed by a non-coherent framebuffer fetch. The renderbuffer read atom doesn't listen to BRW_NEW_BLORP, and would not get the new fast clear color. Cc: [email protected] Reviewed-by: Jason Ekstrand <[email protected]>
* i965: Drop Gen7+ nonsense from brw_ff_gs.c.Kenneth Graunke2017-08-231-4/+3
| | | | | | | | | | brw_ff_gs.c is about using the geometry shader to implement things that the fixed function ought to do, but doesn't on old hardware. Gen7+ does not need this. We should drop the misleading comment about Gen7 not using geometry shaders. Reviewed-by: Timothy Arceri <[email protected]>
* i965: Only set key->flat_shade if COL0/COL1 are written.Kenneth Graunke2017-08-231-1/+3
| | | | | | This may reduce some recompiles. Reviewed-by: Timothy Arceri <[email protected]>
* i965: Clean up brwNewProgram().Kenneth Graunke2017-08-231-28/+5
| | | | | | | | | | All shader stages do the exact same thing, so we don't need the switch statement, or the redundant FS case. I believe these used to be different before Tim eliminated the (e.g.) brw_vertex_program subclasses. Reviewed-by: Tapani Pälli <[email protected]> Reviewed-by: Timothy Arceri <[email protected]>
* i965/clear: Quantize the depth clear value based on the formatJason Ekstrand2017-08-211-2/+12
| | | | | | | | | | | | | | | | | | In f9fd976e8adba733b08d we changed the clear value to be stored as an isl_color_value. This had the side-effect same clear value check is now happening directly between the f32[0] field of the isl_color_value and ctx->Depth.Clear. This isn't what we want for two reasons. One is that the comparison happens in floating point even for Z16 and Z24 formats. Worse than that, ctx->Depth.Clear is a double so, even for 32-bit float formats, we were comparing as doubles and not floats. This means that the test basically always fails for anything other than 0.0f and 1.0f. This caused a slight performance regression in Lightsmark 2008 because it was using a depth clear value of 0.999 which can't be stored in a 32-bit float so we were doing unneeded resolves. Reviewed-by: Kenneth Graunke <[email protected]> Bugzilla: https://bugs.freedesktop.org/101678 Cc: "17.2" <[email protected]>
* i965: enable STD430 packing by default on IVB+Timothy Arceri2017-08-221-0/+16
| | | | Reviewed-by: Jason Ekstrand <[email protected]>
* i965/bufmgr: s/BO_ALLOC_FOR_RENDER/BO_ALLOC_BUSY/Jason Ekstrand2017-08-204-19/+18
| | | | | | | | | | "Alloc for render" is a terrible name for a flag because it means basically nothing. What the flag really does is allocate a busy BO which someone theorized at one point in time would be more efficient if you're planning to immediately render to it. If the flag really means "alloc a busy BO" we should just call it that. Reviewed-by: Kenneth Graunke <[email protected]>
* i965/tex: Change the flags type on create_for_teximageJason Ekstrand2017-08-201-1/+1
| | | | | | This matches the actual function declaration. Reviewed-by: Kenneth Graunke <[email protected]>
* i965/tex: Don't pass samples to miptree_create_for_teximageJason Ekstrand2017-08-191-1/+1
| | | | | | | | | | | | | | | | | In 76e2f390f9863a35, when Topi switched num_samples from 0 to 1 for single-sampled, he accidentally switched the last parameter in the call to miptree_create_for_teximage from 0 to 1 thinking it was num_samples when it was actually layout_flags. Switching from 0 to 1 added the MIPTREE_LAYOUT_ACCELERATED_UPLOAD flag which causes us to allocate a busy BO instead of an idle one. This caused the subsequent CPU upload to consistently stall. The end result was a 15% performance drop in the SynMark v7 DrvRes microbenchmark. This restores the old behavior and fixes the performance regression. Reviewed-by: Topi Pohjolainen <[email protected]> Fixes: 76e2f390f9863a356d1419982dec705260d67eff Bugzilla: https://bugs.freedesktop.org/102260 Cc: [email protected]
* i965: Use ISL for emitting null surface states.Kenneth Graunke2017-08-197-351/+49
| | | | | | | We handle the Sandybridge multisampled 2D surface hack here, rather than in ISL, because it requires allocating a BO, and is kind of messy. Reviewed-by: Jason Ekstrand <[email protected]>
* i965: Remove tabs in intel_batchbuffer.c.Kenneth Graunke2017-08-181-7/+7
| | | | | | | Our coding style is to use spaces. Some of this was also messed up during my bufmgr import series. (Trivial, just whitespace changes.)
* i965/miptree: Return NONE from texture_aux_usage when fully resolvedJason Ekstrand2017-08-181-1/+14
| | | | | | | | | | | This little optimization improves the performance of SynMark v7 TexFilterTri by almost 10% on Sky Lake GT4 among other improvements. We've been doing it for some time but somehow it got dropped during the miptree refactoring. Reviewed-by: Kenneth Graunke <[email protected]> Bugzilla: https://bugs.freedesktop.org/102258 Cc: "17.2" <[email protected]>
* i965: Stop looking at NewDriverState when emitting 3DSTATE_URBJason Ekstrand2017-08-183-5/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | Looking at NewDriverState is not safe in general. The state atom system is set up to ensure that new bits that get added to NewDriverState get accumulated into the set of bits used when emitting atoms but it doesn't go the other way. If we read NewDriverState, we may not get the full picture because the per-pipeline state (3D or compute) does not get added to NewDriverState before state emit is done. It's especially dangerous to do this from BLORP (either explicitly or implicitly when BLORP calls gen7_upload_urb) because that does not happen during one of the normal state upload paths. This commit solves the problem by whacking all of the per-shader-stage URB sizes to zero whenever we change the total URB size. We still have to flag BRW_NEW_URB_SIZE to ensure that the gen7_urb atom triggers but the actual decision in gen7_upload_urb can now be based entirely on URB sizes rather than on state atoms. This also makes BLORP correct because it just asks for a new URB config whenever the vsize is too small and so any change to the total URB size will trigger blorp to re-emit as well because 0 < vs_entry_size. Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Jordan Justen <[email protected]> Bugzilla: https://bugs.freedesktop.org/102289 Cc: [email protected]
* i965: Mark all EGLimages as non-coherent.Kenneth Graunke2017-08-181-5/+3
| | | | | | | | | | | | | | | | EGLimages are shared with external users, and we don't know what they're going to do with them. They might scan them out. They might access them in a way that doesn't work with our explicit clflushing. It's safest to simply mark them non-coherent. Chris Wilson caught this problem and wrote a similar (though less aggressive) patch to solve it; the miptree code has since undergone a lot of refactoring so I had to rewrite it. Cc: "17.2" <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> Reviewed-by: Chris Wilson <[email protected]>
* i965: Fix missing newlines in perf_debug messages.Kenneth Graunke2017-08-172-3/+3
| | | | perf_debug() doesn't append a newline for you.
* i965: Alphabetize TCS image dirty bitsKenneth Graunke2017-08-161-1/+1
| | | | Trivial.
* i965: Always allow CPU readback of the scanout on LLC platformsChris Wilson2017-08-161-1/+15
| | | | | | | | | LLC platforms are magic in that reads from the CPU are always cache coherent, or rather GPU writes that bypass LLC do still invalidate the appropriate cache line. Cc: "17.2" <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965: make sure check_and_emit_atom gets inlinedTapani Pälli2017-08-161-1/+1
| | | | | | | | | | | | | | Improves performance of 3DMark "Ice Storm Unlimited" benchmark by 1-2% on Apollolake (on Android-IA using clang 3.8.256229). Change is based on the performance profiling work and results by Aravindan Muthukumar and Yogesh Marathe. Signed-off-by: Tapani Pälli <[email protected]> Signed-off-by: Aravindan Muthukumar <[email protected]> Signed-off-by: Yogesh Marathe <[email protected]> Reviewed-by: Scott D Phillips <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* i965: Advertise the CCS modifierBen Widawsky2017-08-141-4/+40
| | | | | | | | | | | | | | | | | | | | | | | | v2: Rename modifier to be more smart (Jason) FINISHME: Use the kernel's final choice for the fb modifier bwidawsk@norris2:~/intel-gfx/kmscube (modifiers $) ~/scripts/measure_bandwidth.sh ./kmscube none Read bandwidth: 603.91 MiB/s Write bandwidth: 615.28 MiB/s bwidawsk@norris2:~/intel-gfx/kmscube (modifiers $) ~/scripts/measure_bandwidth.sh ./kmscube ytile Read bandwidth: 571.13 MiB/s Write bandwidth: 555.51 MiB/s bwidawsk@norris2:~/intel-gfx/kmscube (modifiers $) ~/scripts/measure_bandwidth.sh ./kmscube ccs Read bandwidth: 259.34 MiB/s Write bandwidth: 337.83 MiB/s v2: Move all references to the new fourcc code(s) to this patch. v3: Rebase, remove Yf_CCS (Daniel) Signed-off-by: Ben Widawsky <[email protected]> Signed-off-by: Jason Ekstrand <[email protected]> Acked-by: Daniel Stone <[email protected]> Reviewed-by: Chad Versace <[email protected]>
* i965/miptree: More conservatively resolve external imagesJason Ekstrand2017-08-143-1/+47
| | | | | | | | | Instead of always doing a full resolve, only resolve the bits that are needed. This means that we only do a partial resolve when the miptree modifier is I915_FORMAT_MOD_Y_TILED_CCS. Reviewed-by: Topi Pohjolainen <[email protected]> Reviewed-by: Chad Versace <[email protected]>
* i965: Pretend that CCS modified images are two planesBen Widawsky2017-08-141-21/+34
| | | | | | | | | | | | | | | | v2: move is_aux into if block. (Jason) Use else block instead of goto (Jason) v3: Fix up logic for is_aux (Ben) Fix up size calculations and add FIXME (Ben) v4 (Jason Ekstrand): Use the aux_pitch in the image instead of calculating it Signed-off-by: Ben Widawsky <[email protected]> Acked-by: Daniel Stone <[email protected]> Reviewed-by: Topi Pohjolainen <[email protected]> Reviewed-by: Chad Versace <[email protected]>
* i965/screen: Support import and export of surfaces with CCSJason Ekstrand2017-08-141-8/+71
| | | | | Reviewed-by: Topi Pohjolainen <[email protected]> Reviewed-by: Chad Versace <[email protected]>
* i965/miptree: Allocate mcs_buf for an image's CCSBen Widawsky2017-08-141-4/+91
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This code will disable actually creating these buffers for the scanout, but it puts the allocation in place. Primarily this patch is split out for review, it can be squashed in later if preferred. v2: assert(mt->offset == 0) in ccs creation (as requested by Topi) Remove bogus is_scanout check in miptree_release v3: Remove is_scanout assert in intel_miptree_create. It doesn't work with latest codebase - not sure it ever should have worked. v4: assert(mt->last_level == 0) and assert(mt->first_level == 0) in ccs setup (Topi) v5 (Jason Ekstrand): - Base the decision to allocate a CCS on the image modifier Signed-off-by: Ben Widawsky <[email protected]> Acked-by: Daniel Stone <[email protected]> Reviewed-by: Topi Pohjolainen <[email protected]> Reviewed-by: Chad Versace <[email protected]>
* i965: Support images with aux buffersBen Widawsky2017-08-141-0/+6
| | | | | | | | | | | | | | Previously images did not support any auxiliary compression surfaces (CCS, MCS, or HiZ). That's about to change. This patch just adds the fields to __DRIimageRec to make auxiliary surfaces possible. v2 (Jason Ekstrand): - Add an aux_pitch parameter as well as aux_offset Signed-off-by: Ben Widawsky <[email protected]> Acked-by: Daniel Stone <[email protected]> Reviewed-by: Topi Pohjolainen <[email protected]> Reviewed-by: Chad Versace <[email protected]>
* i965/screen: Stop redefining DRM_FORMAT_MOD_(INVALID|LINEAR)Jason Ekstrand2017-08-141-8/+0
| | | | Reviewed-by: Ben Widawsky <[email protected]>
* i965/blorp: Correct type of src_format in call to ↵Scott D Phillips2017-08-141-1/+2
| | | | | | | | | | | | | | | | | | intel_miptree_texture_aux_usage intel_miptree_texture_aux_usage() takes an isl_format, but we are passing a mesa_format. clang warns: brw_blorp.c:305:52: warning: implicit conversion from enumeration type 'mesa_format' to different enumeration type 'enum isl_format' [-Wenum-conversion] intel_miptree_texture_aux_usage(brw, src_mt, src_format); ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ^~~~~~~~~~ Fixes: fc1639e46d ("i965/blorp: Use texture/render_aux_usage for blits") Cc: "17.2" <[email protected]> Reviewed-by: Jordan Justen <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* i965: Guard GetBufferSubData's streaming memcpy load with USE_SSE41Kenneth Graunke2017-08-121-0/+2
| | | | | | | | | | This should hopefully fix build issues on 32-bit Android-x86. v2: s/USE_SSE4_1/USE_SS41/, caught by Gražvydas Ignotas. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=102050 Reviewed-by: Tapani Pälli <[email protected]> Reviewed-by: Emil Velikov <[email protected]>
* i965: Clean up intel_batchbuffer_init().Kenneth Graunke2017-08-123-12/+11
| | | | | | | | | | | | | Passing screen lets us get the kernel features, devinfo, and bufmgr, without needing container_of. This use of container_of could cause crashes due to issues with the "sample" macro parameter. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=102062 Reviewed-by: Tapani Pälli <[email protected]> Reviewed-by: Emil Velikov <[email protected]> Reviewed-by: Iago Toral Quiroga <[email protected]>
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