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* i965/disasm: Cut piles of duplicate swizzle printing.Kenneth Graunke2014-06-301-89/+26
| | | | | | | | Making a helper function saves us from cut and pasting this four times. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Matt Turner <[email protected]> Reviewed-by: Kristian Høgsberg <[email protected]>
* i965/disasm: Properly decode negate source modifiers on Broadwell.Kenneth Graunke2014-06-301-4/+49
| | | | | | | | | This is a port of Abdiel's 6f9f916b9b042a294813ab0542390846a38739da to brw_disasm.c. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Matt Turner <[email protected]> Reviewed-by: Kristian Høgsberg <[email protected]>
* i965/disasm: Improve disassembly of atomic messages on Haswell+.Kenneth Graunke2014-06-301-7/+21
| | | | | | | | | | This backports the atomic message disassembly support from gen8_disasm.c, which additionally offers support for decoding atomic surface read/write messages, and showing SIMD modes and other details. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Matt Turner <[email protected]> Reviewed-by: Kristian Høgsberg <[email protected]>
* i965/disasm: Actually disassemble Gen7+ URB opcodes.Kenneth Graunke2014-06-301-3/+19
| | | | | | | | | | | I never bothered implementing the disassembler for Gen7+ URB opcodes, so we were just disassembling them as Ironlake/Sandybridge ones. This looked pretty bad when running Paul's GS EndPrimitive tests, as the "write OWord" message was decoded at ff_sync, which doesn't exist. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Matt Turner <[email protected]> Reviewed-by: Kristian Høgsberg <[email protected]>
* i965/disasm: Decode Broadwell's invm/rsqrtm math functions.Kenneth Graunke2014-06-301-0/+2
| | | | | | | | We don't use these yet, but we may as well disassemble them. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Matt Turner <[email protected]> Reviewed-by: Kristian Høgsberg <[email protected]>
* i965/disasm: Properly disassemble the "atomic" ThreadCtrl value.Kenneth Graunke2014-06-301-2/+3
| | | | | | Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Matt Turner <[email protected]> Reviewed-by: Kristian Høgsberg <[email protected]>
* i965/disasm: Properly disassemble all32h/any32h align1 predicates.Kenneth Graunke2014-06-301-11/+13
| | | | | | | | | While we're adding things, use symbolic constants rather than magic numbers. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Matt Turner <[email protected]> Reviewed-by: Kristian Høgsberg <[email protected]>
* i965: Add #defines for any32h/all32h predication.Kenneth Graunke2014-06-301-0/+2
| | | | | | | | | | These have existed since Ivybridge. We don't use them today, but the Gen8+ disassembler supports them, and I'd like to use symbolic names rather than magic numbers. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Matt Turner <[email protected]> Reviewed-by: Kristian Høgsberg <[email protected]>
* i965/disasm: Mark ELSE as having UIP on Gen8+.Kenneth Graunke2014-06-301-0/+1
| | | | | | | | | This makes brw_disasm.c able to disassemble ELSE instructions correctly on Broadwell. (gen8_disasm.c already handles this correctly.) Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Matt Turner <[email protected]> Reviewed-by: Kristian Høgsberg <[email protected]>
* i965/disasm: Properly disassemble jump targets on Gen4-5.Kenneth Graunke2014-06-301-0/+15
| | | | | | | | | | | | | | | | | | | Previously, our dissasembly for flow control instructions looked like: 0x00000040: else(8) ip 65540D { align16 switch }; It didn't print InstCount properly for ELSE/ENDIF, and didn't even attempt to disassemble PopCount. Now it looks like: 0x00000040: else(8) Jump: 4 Pop: 1 { align16 switch }; which is much more readable. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Matt Turner <[email protected]> Reviewed-by: Kristian Høgsberg <[email protected]>
* i965/disasm: Improve disassembly of jump targets on Gen6+.Kenneth Graunke2014-06-301-18/+41
| | | | | | | | | | | | | | | | | | | | | | | | | | Previously, flow control instructions generated output like: (+f0) if(8) 12 8 null 0x000c0008UD { align16 WE_normal 1Q }; which included a dissasembly of the register fields, even though those are meaningless for flow control instructions---those bits are reused for another purpose. It also wasn't immediately obvious which number was UIP and which was JIP. With this patch, we instead output: (+f0) if(8) JIP: 8 UIP: 12 { align16 WE_normal 1Q }; which is much clearer. The patch also introduces has_uip/has_jip helper functions which clear up a some generation/opcode checking mess. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Matt Turner <[email protected]> Reviewed-by: Kristian Høgsberg <[email protected]>
* i965/disasm: Add support for new Gen8+ register types.Kenneth Graunke2014-06-301-16/+24
| | | | | | | | | While we're at it, use proper names rather than magic numbers for the existing fields. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Matt Turner <[email protected]> Reviewed-by: Kristian Høgsberg <[email protected]>
* i965: Restyle brw_disasm.c.Kenneth Graunke2014-06-301-1234/+1231
| | | | | | | | | | | | | | | | | | | | brw_disasm.c basically wasn't following the Mesa coding style at all. It used 4-space indent instead of 3-space, didn't cuddle braces, didn't put function return types on a separate line, put extra spaces in function calls (between the name and parenthesis), and a number of other things. This made it fairly obnoxious to work on, since my editor is configured to follow Mesa style in the Mesa source repository. Fixing it to follow a consistent style now should save time dealing with it later. These modifications were originally generated by: $ indent -br -i3 -npcs -ce -cs -l80 --no-tabs with some manual changes afterwards to fit our style better. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Matt Turner <[email protected]> Reviewed-by: Kristian Høgsberg <[email protected]>
* i965/disasm: Create an "opcode" temporary.Kenneth Graunke2014-06-301-31/+30
| | | | | | | | This saves typing brw_inst_opcode(brw, inst) everywhere. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Matt Turner <[email protected]> Reviewed-by: Kristian Høgsberg <[email protected]>
* i965/disasm: Eliminate opcode pointer.Kenneth Graunke2014-06-301-8/+7
| | | | | | | | | opcode is just a pointer to opcode_descs; we may as well use that directly. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Matt Turner <[email protected]> Reviewed-by: Kristian Høgsberg <[email protected]>
* Remove the ATI_envmap_bumpmap extensionJason Ekstrand2014-06-302-2/+0
| | | | | | | | | | | As far as I can tell, the Intel mesa driver is the only driver in the world still supporting this legacy extension. If someone wants to do bump mapping, they can use shaders. Signed-off-by: Jason Ekstrand <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> [v1] Reviewed-by: Chris Forbes <[email protected]> [v2] Reviewed-by: Ian Romanick <[email protected]> [v3]
* meta: Use AMD_vertex_shader_layer instead of a GS for layered clears.Kenneth Graunke2014-06-301-37/+16
| | | | | | | | | | | | | | | | | | | | | | | On i965, enabling and disabling the GS is not free: you have to do a full pipeline stall, reconfigure the URB and push constant space, and emit a bunch of state. Most clears aren't layered, so the GS isn't needed in the common case. But we turned it on universally. Using AMD_vertex_shader_layer allows us to skip setting up the GS altogether, while achieving the same effect. According to Ilia, current nVidia GPUs can't do AMD_vertex_shader_layer. However, since nouveau is Gallium-based, they're unlikely to ever care about this path. Intel and AMD GPUs both support the extension. Since i965 is the only driver using this path which does layered rendering, we may as well target it at that. v2: Improve commit message. No code changes. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Chris Forbes <[email protected]> Reviewed-by: Jordan Justen <[email protected]>
* i965: Enable vertex streams up to MAX_VERTEX_STREAMS.Iago Toral Quiroga2014-06-301-0/+4
| | | | Reviewed-by: Ian Romanick <[email protected]>
* i965: Implement GL_PRIMITIVES_GENERATED with non-zero streams.Iago Toral Quiroga2014-06-302-7/+26
| | | | | | | | | | | | | | | | | So far we have been using CL_INVOCATION_COUNT to resolve this query but this is no good with streams, as only stream 0 reaches the clipping stage. Instead we will use SO_PRIM_STORAGE_NEEDED which can keep track of the primitives sent to each individual stream. Since SO_PRIM_STORAGE_NEEDED is related to the SOL stage and according to ARB_transform_feedback3 we need to be able to query primitives generated in each stream whether transform feedback is active or not what we do is to enable the SOL unit even if transform feedback is not active but disable all output buffers in that case. This effectively disables transform feedback but permits activation of statistics enabling SO_PRIM_STORAGE_NEEDED even when transform feedback is not active. Reviewed-by: Chris Forbes <[email protected]>
* i965: Implement GL_TRANSFORM_FEEDBACK_PRIMITIVES_WRITTEN with non-zero streams.Iago Toral Quiroga2014-06-301-4/+4
| | | | Reviewed-by: Chris Forbes <[email protected]>
* i965/gs: Set control data bits for vertices emitted in stream mode.Iago Toral Quiroga2014-06-302-1/+51
| | | | | | | In stream mode we have to set control data bits with the StreamID information for every vertex. Reviewed-by: Chris Forbes <[email protected]>
* i965/gs: Set number of control data bits for stream mode.Iago Toral Quiroga2014-06-301-4/+5
| | | | | | | | | If the geometry shader is indeed using streams then we need 2 control data bits per vertex for the StreamID. If the shader is not using streams then we don't need control data bits. Reviewed-by: Chris Forbes <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* i965: Enable transform feedback for streams > 0Iago Toral Quiroga2014-06-301-24/+43
| | | | | | | Configure hardware to read vertex data for all streams and have all streams write their varyings to the corresponsing output buffers. Reviewed-by: Ian Romanick <[email protected]>
* i965: Enable compressed multisample support (CMS) on Broadwell.Kenneth Graunke2014-06-261-8/+0
| | | | | | | Everything is in place and appears to be working. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Jordan Justen <[email protected]>
* i965: Add 2x MSAA support to the MCS allocation function.Kenneth Graunke2014-06-261-0/+1
| | | | | | | 2x MSAA also uses 8 bits, just like 4x. More bits are unused. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Jordan Justen <[email protected]>
* i965: Hook up the MCS buffers in SURFACE_STATE on Broadwell.Kenneth Graunke2014-06-261-0/+10
| | | | | | | | | MCS buffers are never allocated on Broadwell, so this does nothing for now, but puts the infrastructure in place for when they do exist. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Jordan Justen <[email protected]> Reviewed-by: Ben Widawsky <[email protected]>
* i965: Drop SINT workaround for CMS layout on Broadwell.Kenneth Graunke2014-06-261-3/+1
| | | | | | | | | According to the documentation, we don't need this SINT workaround on Broadwell. (Or at least, it doesn't mention that we need it.) Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Jordan Justen <[email protected]> Reviewed-by: Ben Widawsky <[email protected]>
* i965: Add plumbing for Broadwell's auxiliary surface support.Kenneth Graunke2014-06-261-7/+37
| | | | | | | | | | | | | | Broadwell generalizes the MCS fields to allow for multiple kinds of auxiliary surfaces. This patch adds the plumbing to set those values, but doesn't yet hook any up. v2: (by Jordan Justen) Use mt for qpitch; pitch is tiles - 1. v3: Don't forget to subtract 1 from aux_mt->pitch. v4: Drop unnecessary aux_mt->offset (caught by Jordan Justen). Signed-off-by: Kenneth Graunke <[email protected]> Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Ben Widawsky <[email protected]>
* i965: Add auxiliary surface field #defines for Broadwell.Jordan Justen2014-06-261-0/+10
| | | | | | Signed-off-by: Jordan Justen <[email protected]> Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Ben Widawsky <[email protected]>
* i965: Disassemble all of DP write message control bits on Gen6.Kenneth Graunke2014-06-261-1/+1
| | | | | | | | | Prior to the new brw_inst API, the brw_instruction structure split off bits 4 and 5 of msg_control for specific fields, and we failed to disassemble them. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* i965: Pass brw to brw_try_compact_instruction().Matt Turner2014-06-263-5/+4
| | | | | Signed-off-by: Matt Turner <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Add is_cherryview flag to brw_context.Matt Turner2014-06-262-0/+2
| | | | | Signed-off-by: Matt Turner <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Add CSEL opcode definition for Gen8.Matt Turner2014-06-261-0/+1
| | | | | Signed-off-by: Matt Turner <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Document which instructions are generation specific.Matt Turner2014-06-261-20/+20
| | | | | Signed-off-by: Matt Turner <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Don't set UIP for ENDIF/WHILE.Matt Turner2014-06-261-0/+4
| | | | | | | | | | They don't have a UIP. We used UIP in an array dereference, which never caused problems on Gen < 8, since UIP was a small integer (number of instructions). On Gen 8 UIP is in bytes, so it's large enough that it caused us to read out of bounds of the array. Signed-off-by: Matt Turner <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Replace struct brw_compact_instruction with brw_compact_inst.Matt Turner2014-06-266-61/+24
| | | | | Signed-off-by: Matt Turner <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Convert brw_eu_compact.c to the new brw_compact_inst API.Matt Turner2014-06-261-38/+44
| | | | | Signed-off-by: Matt Turner <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Introduce a new brw_compact_inst API.Matt Turner2014-06-261-0/+90
| | | | | | | For now nothing uses this, but we can incrementally convert. Signed-off-by: Matt Turner <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Replace 'struct brw_instruction' with 'brw_inst'.Matt Turner2014-06-2612-273/+223
| | | | | | | | Use this an an opportunity to clean up the formatting of some old code (brw_ADD, for instance). Signed-off-by: Matt Turner <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Throw out guts of struct brw_instruction.Matt Turner2014-06-261-644/+1
| | | | | Signed-off-by: Matt Turner <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Convert brw_gs_emit.c to the new brw_inst API.Matt Turner2014-06-261-3/+4
| | | | | Signed-off-by: Matt Turner <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Convert brw_disasm.c to the new brw_inst API.Matt Turner2014-06-261-341/+316
| | | | | | | | | | | | | | | | | | v2: (by Kenneth Graunke) - Fix disassembly of Gen4-5 SEND messages to print base MRF correctly. - Only print URB opcode on Gen5+, to match previous output (besides, there is only one opcode AFAICT.) - Only print the low 3 bits of msg_control, to match previous output. (We probably should decode all the fields, but hadn't previously due to the brw_instruction structure definition splitting out bits 4/5 for last_render_target and slot_group_select.) - Fix 3-source MRF/GRF file decoding on Sandybridge. - Fix compression code to use qtr_control rather than cmpt_control (which is compaction, not compression). Signed-off-by: Matt Turner <[email protected]> Signed-off-by: Kenneth Graunke <[email protected]> [v2] Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Pass brw rather than gen to brw_disassemble_inst().Matt Turner2014-06-265-33/+33
| | | | | | | We will need it in order to use the new brw_inst API. Signed-off-by: Matt Turner <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Convert brw_eu_compact.c to the new brw_inst API.Matt Turner2014-06-261-105/+104
| | | | | | | | v2: Use brw_inst_bits rather than pulling out individual fields and reassembling them. Signed-off-by: Matt Turner <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Extend is_haswell checks to gen >= 8 in Gen4-7 generators.Kenneth Graunke2014-06-262-7/+7
| | | | | | | | | We're going to use fs_generator/vec4_generator for Gen8+ code soon, thanks to the new brw_instruction API. When we do, we'll generally want to take the Haswell paths on Gen8+ as well. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* i965: Convert test_eu_compact.c to the new brw_inst API.Kenneth Graunke2014-06-261-22/+19
| | | | | Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* i965: Convert vec4_generator to the new brw_inst API.Kenneth Graunke2014-06-261-8/+8
| | | | | Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* i965: Convert fs_generator to the new brw_inst API.Kenneth Graunke2014-06-261-9/+9
| | | | | Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* i965: Convert Gen4-5 clipping code to the new brw_inst API.Kenneth Graunke2014-06-264-41/+52
| | | | | Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* i965: Convert brw_sf_emit.c to the new brw_inst API.Kenneth Graunke2014-06-261-3/+4
| | | | | Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Matt Turner <[email protected]>
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