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* | intel: disable intel_stencil_drawpixels() for nowBrian Paul2009-09-101-0/+16
* | Fix merge failIan Romanick2009-09-101-13/+0
* | mesa: need to set all stencil bits to 0 before setting the 1 bitsBrian Paul2009-09-101-0/+9
* | Merge branch 'mesa_7_5_branch' into mesa_7_6_branchIan Romanick2009-09-102-1/+6
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| * intel: add B43 chipset supportZhenyu Wang2009-09-102-1/+6
* | i965: Fix relocation delta for WM surfaces.Eric Anholt2009-09-101-1/+1
* | radeon: Change debugging code to use macros instead of inline functions.Pauli Nieminen2009-09-102-43/+27
* | radeon: Add more verbose error message for failed command buffer.Pauli Nieminen2009-09-091-1/+3
* | Merge branch 'mesa_7_5_branch' into mesa_7_6_branchBrian Paul2009-09-095-1/+24
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| * i965: fix incorrect test for vertex position attributeBrian Paul2009-09-083-1/+4
| * i965: Fix warnings in intel_pixel_read.c.Eric Anholt2009-09-041-0/+4
| * intel: Also get the DRI2 front buffer when doing front buffer reading.Eric Anholt2009-09-044-1/+29
| * intel: Update Mesa state before span setup in glReadPixels.Eric Anholt2009-09-043-3/+13
| * intel: Move intel_pixel_read.c to shared for use with i965.Eric Anholt2009-09-042-306/+307
| * i965: Add missing state dependency of sf_unit on _NEW_BUFFERS.Eric Anholt2009-09-041-2/+4
| * intel: Align cubemap texture height to its padding requirements.Eric Anholt2009-09-041-0/+10
| * intel: Align untiled region height to 2 according to 965 docs.Eric Anholt2009-09-041-0/+7
| * i965: Fix source depth reg setting for FSes reading and writing to depth.Eric Anholt2009-09-043-1/+5
| * i965: Respect CondSwizzle in OPCODE_IF.Eric Anholt2009-09-041-1/+21
| * i965: asst clean-ups, etc in brw_vs_emit()Brian Paul2009-09-041-11/+10
| * i965: Emit conditional code updates as required for GLSL VS if statements.Eric Anholt2009-09-041-0/+13
| * i965: Spell "conditional" correctly.Eric Anholt2009-09-043-15/+15
| * i965: Fix RECT shadow sampling by not losing the other texcoords.Eric Anholt2009-09-041-1/+5
| * i965: Assert that the offset in the VBO is below the VBO size.Eric Anholt2009-09-041-0/+14
| * i965: Even if no VS inputs are set, still load some amount of URB as required.Eric Anholt2009-09-041-0/+11
| * i965: Make sure the VS URB size is big enough to fit a VF VUE.Eric Anholt2009-09-041-1/+8
| * i965: Don't emit bad packets when no VBs are referenced.Eric Anholt2009-09-041-0/+22
| * i965: Calculate enabled[] and nr_enabled once and re-use the values.Eric Anholt2009-09-042-29/+18
| * i965: Set the max index buffer address correctly according to the docs.Eric Anholt2009-09-041-1/+1
| * i965: rename var: s/tmp/vs_inputs/Brian Paul2009-09-041-8/+8
| * dri: Fix problems with unitialized values in dri screen object.Pauli Nieminen2009-08-071-1/+1
* | mesa: disable GL_LUMINANCE case in _mesa_meta_draw_pixels()Brian Paul2009-09-091-1/+4
* | r600: fix Elts handlingAlex Deucher2009-09-042-3/+16
* | r600: rework cb/db setupAlex Deucher2009-09-033-130/+109
* | r600: make sure the active vertex shader bo is re-added to persistent list.Alex Deucher2009-09-031-0/+7
* | mesa: rename gl_sync_object::Status to StatusFlagBrian Paul2009-09-031-2/+2
* | Add ARB_sync to the xorg sw dri driver.Eric Anholt2009-09-031-0/+2
* | savage: Fix driver build post-ARB_sync.Eric Anholt2009-09-032-8/+6
* | s3v: Fix driver build for ARB_sync.Eric Anholt2009-09-031-3/+2
* | intel: Add support for ARB_sync.Eric Anholt2009-09-038-0/+147
* | ARB sync / swrast: Use GL_ARB_sync_functions instead of GL_ARB_sync. Oops.Ian Romanick2009-09-031-1/+1
* | ARB sync: Add support for GL_ARB_sync to swrastIan Romanick2009-09-032-0/+10
* | Eliminate trailing whitespace in extension_helper.cIan Romanick2009-09-031-673/+673
* | ARB sync: Regenerate files from previous commitIan Romanick2009-09-031-0/+62
* | intel: helper to debug bufmgr (disabled)Brian Paul2009-09-031-0/+4
* | mesa: change ctx->Driver.BufferData() to return GLboolean for success/failureBrian Paul2009-09-032-5/+15
* | r600: visual depth has no meaning here.Dave Airlie2009-09-031-12/+2
* | r600: make sure the active shader bo is re-added to persistent list.Dave Airlie2009-09-031-0/+8
* | radeon: pass internal format into the miptree.Dave Airlie2009-09-033-11/+14
* | radeon/dri2: add gl20 bits for r300/r600 just like dri1 doesDave Airlie2009-09-031-0/+2
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