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* i965: Regenerate blob without gen program for shader cacheJordan Justen2018-07-091-1/+63
| | | | | Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Timothy Arceri <[email protected]>
* i965: Add support for driver cache blob containing the gen programJordan Justen2018-07-091-0/+41
| | | | | Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Timothy Arceri <[email protected]>
* i965: Use brw_prog_key_set_id in disk cache load/store codeJordan Justen2018-07-091-16/+8
| | | | | Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Timothy Arceri <[email protected]>
* i965: Add brw_prog_key_set_id helper to set the program id on any stageJordan Justen2018-07-092-0/+19
| | | | | | | | | | | For saving programs (shader cache; get program binary) it is useful to set the id to 0, with the stage being a parameter. For restoring programs it is useful to set the id to the id allocated to the program at creation time. Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Timothy Arceri <[email protected]>
* i965: Add brw_stage_cache_id to map gl stages to brw cache_idsJordan Justen2018-07-092-0/+17
| | | | | Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Timothy Arceri <[email protected]>
* i965: Add brw_(read|write)_blob_program_data functionsJordan Justen2018-07-093-41/+61
| | | | | | | | We will want to use these for both the disk shader cache, and for the ARB_get_program_binary. Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Timothy Arceri <[email protected]>
* i965: Add brw_program_deserialize_driver_blobJordan Justen2018-07-093-21/+48
| | | | | | | | | | | brw_program_deserialize_driver_blob will be a more generic form of brw_program_deserialize_nir. In addition to nir, it will also be able to extract gen binaries and upload them to the program cache. In this commit, it continues to only support nir. Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Timothy Arceri <[email protected]>
* i965: Move brw_program_*serialize_nir to brw_program_binary.cJordan Justen2018-07-092-37/+37
| | | | | | | | This will allow get_program_binary to add the gen program into its serialization in addition to just the nir program. Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Timothy Arceri <[email protected]>
* i965: Use ShaderCacheSerializeDriverBlob driver functionJordan Justen2018-07-093-11/+7
| | | | | | | | This function is called just before the gl_program::driver_cache_blob is saved out as part of the gl_program serialization. Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Timothy Arceri <[email protected]>
* i965/icl: Don't set float blend optimization bit in CACHE_MODE_SSAnuj Phogat2018-07-091-4/+0
| | | | | | | | | | | | CACHE_MODE_SS is not listed in gfxspecs table for user mode non-privileged registers. So, making any changes from Mesa will do nothing. Kernel is already setting this bit in CACHE_MODE_SS register which is saved/restored to/from the HW context image. Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> Reviewed-by: Lionel Landwerlin <[email protected]>
* swrast: Fix eglMakeCurrent(dpy, NULL, NULL, ctx) (v2)Adam Jackson2018-07-091-21/+20
| | | | | | | | | | Fixes 14 piglits, mostly in egl_khr_create_context. v2: Also short-circuit the same-context-no-drawables case (Eric Anholt) Fixes: https://github.com/anholt/libepoxy/issues/177 Reviewed-by: Eric Anholt <[email protected]> Signed-off-by: Adam Jackson <[email protected]>
* i965: fix clear color bo address relocationLionel Landwerlin2018-07-071-1/+1
| | | | | | Fixes: 7987d041fda0c9 ("i965/surface_state: Emit the clear color address instead of value.") Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Use the new nir atomic counter linker for SPIR-V shadersNeil Roberts2018-07-031-0/+2
| | | | Reviewed-by: Timothy Arceri <[email protected]>
* i965: enable AtomicStorage capability for gen7+Alejandro Piñeiro2018-07-031-0/+1
| | | | | | That is the same gen requirement for ARB_shader_atomic_counters. Reviewed-by: Timothy Arceri <[email protected]>
* i965: Fix BRW_NEW_NUM_SAMPLES to be in .brw, not .mesaKenneth Graunke2018-07-021-2/+2
| | | | | | | | This is the wrong kind of dirty bit. Caught by GCC warnings, due to 64-bit values being truncated to 32 bits. Fixes: b95b0e2918c052068caeb4f6c2802ba89be043a3 (intel/anv,blorp,i965: Implement the SKL 16x MSAA SIMD32 workaround) Reviewed-by: Jason Ekstrand <[email protected]>
* st/mesa/i965: Allow decompressing ETC2 to GL_RGBATomeu Vizoso2018-07-021-1/+1
| | | | | | | | | | | | | | | | | | | | | When Mesa itself implements ETC2 decompression, it currently decompresses to formats in the GL_BGRA component order. That can be problematic for drivers which cannot upload the texture data as GL_BGRA, such as Virgl when it's backed by GLES on the host. So this commit adds a flag to _mesa_unpack_etc2_format so callers can specify the optimal component order. In Gallium's case, it will be requested if the format isn't in PIPE_FORMAT_B8G8R8A8_SRGB format. For i965, it will remain GL_BGRA, as before. v2: * Remove unnecesary include (Emil Velikov) Signed-off-by: Tomeu Vizoso <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* intel/anv,blorp,i965: Implement the SKL 16x MSAA SIMD32 workaroundJason Ekstrand2018-06-281-0/+17
| | | | Reviewed-by: Kenneth Graunke <[email protected]>
* intel/fs: Add fields to wm_prog_data for SIMD32 dispatchJason Ekstrand2018-06-282-0/+3
| | | | Reviewed-by: Matt Turner <[email protected]>
* i965: Add plumbing for shader time in 32-wide FS dispatch mode.Francisco Jerez2018-06-283-2/+11
| | | | | Reviewed-by: Jason Ekstrand <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* intel/compiler: Add and use helpers for working with KSP indicesJason Ekstrand2018-06-282-23/+47
| | | | | | | | The pixel shader dispatch table is kind-of a confusing mess. This adds some helpers for dealing with it and for easily extracting the correct data from wm_prog_data. Reviewed-by: Matt Turner <[email protected]>
* i965: Re-arrange shader kernel setup in WM stateJason Ekstrand2018-06-281-37/+57
| | | | Reviewed-by: Matt Turner <[email protected]>
* i965/bufmgr: Use the correct argument order for bo_alloc_internalJason Ekstrand2018-06-271-2/+2
| | | | | | | The memzone and flags parameters were accidentally flipped in the call from brw_bo_alloc_tiled_2d. Reviewed-by: Kenneth Graunke <[email protected]>
* i965: small cleanup in blorp debug printing output (trivial)Tapani Pälli2018-06-271-1/+1
| | | | | Signed-off-by: Tapani Pälli <[email protected]> Reviewed-by: Jordan Justen <[email protected]>
* nir: Remove old-school deref chain supportJason Ekstrand2018-06-221-1/+0
| | | | | | | Acked-by: Rob Clark <[email protected]> Acked-by: Bas Nieuwenhuizen <[email protected]> Acked-by: Dave Airlie <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* nir: Use derefs in nir_lower_samplersJason Ekstrand2018-06-221-2/+0
| | | | | | | | | | | We change glsl_to_nir to provide derefs for bot textures and samplers while we're at it. This makes the lowering much easier since we only either replace sources or remove them. Acked-by: Rob Clark <[email protected]> Acked-by: Bas Nieuwenhuizen <[email protected]> Acked-by: Dave Airlie <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Move nir_lower_deref_instrs to right before locals_to_regsJason Ekstrand2018-06-221-3/+2
| | | | | | | | Reviewed-by: Caio Marcelo de Oliveira Filho <[email protected]> Acked-by: Rob Clark <[email protected]> Acked-by: Bas Nieuwenhuizen <[email protected]> Acked-by: Dave Airlie <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* intel/nir: Fixup deref modes after lowering patch verticesJason Ekstrand2018-06-221-0/+2
| | | | | | | | Reviewed-by: Caio Marcelo de Oliveira Filho <[email protected]> Acked-by: Rob Clark <[email protected]> Acked-by: Bas Nieuwenhuizen <[email protected]> Acked-by: Dave Airlie <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* anv,i965,radv,st,ir3: Call nir_lower_deref_instrsJason Ekstrand2018-06-222-2/+7
| | | | | | | | | | | This inserts a call to nir_lower_deref_instrs at every call site of glsl_to_nir, spirv_to_nir, and prog_to_nir. Reviewed-by: Caio Marcelo de Oliveira Filho <[email protected]> Acked-by: Rob Clark <[email protected]> Acked-by: Bas Nieuwenhuizen <[email protected]> Acked-by: Dave Airlie <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Link uniforms of SPIR-V programs using the NIR linkerEduardo Lima Mitev2018-06-211-0/+6
| | | | | | | | | v2: nir_link_uniforms renamed to gl_nir_link_uniforms Signed-off-by: Eduardo Lima <[email protected]> Signed-off-by: Alejandro Piñeiro <[email protected]> Reviewed-by: Timothy Arceri <[email protected]>
* i965: Setup glsl uniforms by index rather than name matchingNeil Roberts2018-06-211-13/+37
| | | | | | | | | | | | | | | Previously when setting up a uniform it would try to walk the uniform storage slots and find one that matches the name of the given variable. However, each variable already has a location which is an index into the UniformStorage array so we can just directly jump to the right slot. Some of the variables take up more than one slot so we still need to calculate how many it uses. The main reason to do this is to support ARB_gl_spirv because in that case the uniforms don’t have names so the previous approach won’t work. Reviewed-by: Timothy Arceri <[email protected]>
* i965: account for NIR uniforms without nameEduardo Lima Mitev2018-06-212-8/+5
| | | | | | | | | | | | | | | | | | | | | | | | Right now, the BRW linker code assumes nir_variable::name is always non-NULL, but thanks to ARB_gl_spirv we will soon be linking SPIR-V programs, and those explicitly require matching uniforms by location. The name is just a debug hint. Instead of checking for the name this patch makes it check for var->num_state_slots on the assumption that everything that had an internal name also had some state slots. This seems likely because the two code paths that are taken when the name begins with "gl_" already have an assert that var->state_slots is not NULL. v2: simplified, most of it moved to glsl/nir/spirv (Neil Roberts) v3: check for num_state_slots instead of the name. This is needed because we do actually have nameless builtins with SPIR-V such as PatchVerticesIn and we want them to hit the _mesa_add_state_reference code path (Neil Roberts) Signed-off-by: Eduardo Lima <[email protected]> Signed-off-by: Neil Roberts <[email protected]> Reviewed-by: Timothy Arceri <[email protected]>
* i965: Update TexturesUsed after linking the shadersNeil Roberts2018-06-211-1/+3
| | | | | | | | | Otherwise if the shader is SPIR-V then SamplerUsed won’t have been initialised yet so it will end up thinking no textures are used. This was causing a crash later on if nothing causes it to regenerate TexturesUsed before the next render. Reviewed-by: Timothy Arceri <[email protected]>
* i965: Build SPIR-V programs' resource list using NIREduardo Lima Mitev2018-06-211-1/+7
| | | | | | v2: tweak after nir_linker.h being renamed to gl_nir_linker.h Reviewed-by: Timothy Arceri <[email protected]>
* i965: use gl_shader_program_data::spirvAlejandro Piñeiro2018-06-211-1/+1
| | | | Reviewed-by: Timothy Arceri <[email protected]>
* mesa: remove struct gl_extensions::ATI_separate_stencilEmil Velikov2018-06-212-2/+0
| | | | | | | | | | | | Virtually every driver that supports ATI_separate_stencil also supports EXT_stencil_two_side. Use the latter boolean for both extension. With that in mind we can drop the explicit true from the drivers and the nasty comment in compute_version(). Signed-off-by: Emil Velikov <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* meson: fix i965/anv/isl genX static lib namesEric Engestrom2018-06-181-1/+1
| | | | | | | | | | | Shouldn't make any functional difference, just that `liblibanv_gen90.a` will now be called `libanv_gen90.a`. Fixes: 3218056e0eb375eeda470 "meson: Build i965 and dri stack" Fixes: d1992255bb29054fa5176 "meson: Add build Intel "anv" vulkan driver" Signed-off-by: Eric Engestrom <[email protected]> Reviewed-by: Tapani Pälli <[email protected]> Reviewed-by: Dylan Baker <[email protected]>
* drivers/dri/i965: add missing #includeRoss Burton2018-06-121-0/+2
| | | | | | brw_bufmgr.h uses time_t without include time.h, so the build fails under musl. Reviewed-by: Eric Engestrom <[email protected]>
* i965: fix resource leakEric Engestrom2018-06-111-1/+3
| | | | | | | | | | v2: intel_miptree_release() already takes care of the planes, no need to hand-code the loop (Lionel) Coverity ID: 1436909 Fixes: 3352f2d746d3959b22ca4 "i965: Create multiple miptrees for planar YUV images" Reviewed-by: Lionel Landwerlin <[email protected]> Signed-off-by: Eric Engestrom <[email protected]>
* i965/screen: Sanity check that all formats we advertise are useableJason Ekstrand2018-06-071-4/+20
| | | | Reviewed-by: Lionel Landwerlin <[email protected]>
* i965/screen: Use RGBA non-sRGB formats for imagesJason Ekstrand2018-06-071-0/+9
| | | | | | | | | | Not all of the MESA_FORMAT and ISL_FORMAT helpers we use can properly handle RGBX formats. Also, we don't want to make decisions based on those in the first place because we can't render to RGBA and we use the non-sRGB version to determine whether or not to allow CCS_E. Cc: [email protected] Reviewed-by: Lionel Landwerlin <[email protected]>
* i965/screen: Return false for unsupported formats in query_modifiersJason Ekstrand2018-06-071-2/+14
| | | | | Cc: [email protected] Reviewed-by: Lionel Landwerlin <[email protected]>
* i965/screen: Refactor query_dma_buf_formatsJason Ekstrand2018-06-071-12/+13
| | | | | | | | | This reworks it to work like query_dma_buf_modifiers and, in particular, makes it more flexible so that we can disallow a non-static set of formats. Cc: [email protected] Reviewed-by: Lionel Landwerlin <[email protected]>
* i965: Require softpin support for Cannonlake and later.Kenneth Graunke2018-06-061-0/+10
| | | | | | | | | | | This isn't strictly necessary, but anyone running Cannonlake will already have Kernel 4.5 or later, so there's no reason to support the relocation model on Gen10+. This will let us avoid dealing with them for new features. Reviewed-by: Scott D Phillips <[email protected]> Reviewed-by: Jordan Justen <[email protected]>
* i965: Allocate VMA in userspace for full-PPGTT systems.Kenneth Graunke2018-06-061-1/+1
| | | | | | | | | | | | | | | | This patch enables soft-pinning of all buffers, allowing us to skip relocation processing entirely. All systems with full PPGTT and > 4GB of VMA should gain these benefits. This should be most Gen8+. Unfortunately, this excludes a few systems: - Cherryview (only has 32-bit addressing, despite 48-bit pointers) - Broadwell with a 32-bit kernel - Anybody running pre-4.5 kernel. We may enable it for Cherryview in the future, but it would require some tweaks to the memory zone. Reviewed-by: Jordan Justen <[email protected]>
* intel/blorp: Emit VF cache invalidates for 48-bit bugs with softpin.Kenneth Graunke2018-06-061-0/+29
| | | | | | | | | | | | | | | | | | commit 92f01fc5f914fd500497d0c3aed75f3ac8dc054d made i965 start emitting VF cache invalidates when the high bits of vertex buffers change. But we were not tracking vertex buffers emitted by BLORP. This was papered over by a mistake where I emitted VF cache invalidates all the time, which Chris fixed in commit 3ac5fbadfd8644d30fce9ff267cb811ad157996a. This patch adds a new hook which allows the driver to track addresses and request a VF cache invalidate as appropriate. v2: Make the driver do the PIPE_CONTROL so it can apply workarounds (caught by Jason Ekstrand). Rebase on anv bug fix. v3: Don't screw up the boolean (caught by Jason Ekstrand). Fixes: 92f01fc5f914 ("i965: Emit VF cache invalidates for 48-bit addressing bugs with softpin.") Reviewed-by: Jason Ekstrand <[email protected]>
* dri: add missing 16bits formats mappingLionel Landwerlin2018-06-071-0/+16
| | | | | | | | | | | | | | | | | | i965 advertises the 16-bit R and RG formats through eglQueryDmaBufFormatsEXT but falls over when a client tries to use or asks more information about such a format because driImageFormatToGLFormat returns MESA_FORMAT_NONE. Found by Eero Tamminen. v2: Add G16R16 formats (Lionel) v3: Fix G16R16 mapping to mesa format (Jason) Signed-off-by: Lionel Landwerlin <[email protected]> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106642 Reviewed-by: Plamena Manolova <[email protected]> (v2) Reviewed-by: Jason Ekstrand <[email protected]>
* i965: Prepare batchbuffer module for softpin support.Kenneth Graunke2018-06-042-3/+39
| | | | | | | | | | | | | | | | | | | | If EXEC_OBJECT_PINNED is set, we don't want to emit any relocations. We simply want to add the BO to the validation list, and possibly mark it as writeable. The new brw_use_pinned_bo() interface does just that. To avoid having to make every caller consider both the relocation and softpin cases, we make emit_reloc() call brw_use_pinned_bo() when given a softpinned buffer. We also can't grow buffers that are softpinned - the mechanism places a larger BO at the same offset as the original, which requires moving BOs around in the VMA. With softpin, we only allocate enough VMA for the original size of the BO. v2: Assert that BOs aren't pinned if the kernel says we should move them (feedback from Chris Wilson) Reviewed-by: Scott D Phillips <[email protected]>
* i965: Add virtual memory allocator infrastructure to brw_bufmgr.Kenneth Graunke2018-06-042-1/+286
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This introduces a new fast virtual memory allocator integrated with our BO cache bucketing. For larger objects, it falls back to the simple free-list allocator (util_vma). This puts the allocators in place but doesn't enable softpin yet. v2: (feedback from Chris Wilson) - Check (bo->kflags & EXEC_OBJECT_PINNED) instead of a global flag - Avoid vma_free(0ull) on the err_free path. - Only enable if the kernel says we have full PPGTT support - Make bucketing allocators more resistant to failing to grow arrays (feedback from Scott Phillips) - Don't use node after popping it from the list. - Avoid undefined behavior in canonicalization by reusing new helper - Comment updates (feedback from myself) - Avoid __vma_alloc vs. vma_alloc by making a zero_high_bits helper to return a non-canonical address with the high bits zeroed. - Don't shadow loop variable 'i' when destroying things (ugly; worked) v3: - Replace zero_high_bits with new common gen_48b_address helper. Reviewed-by: Scott D Phillips <[email protected]> Reviewed-by: Jordan Justen <[email protected]>
* i965: Disable internal CCS for shadows of multi-sampled windowsJason Ekstrand2018-06-041-1/+10
| | | | | | | | | | | | | | If window system supports Y-tiling but not CCS_E, we currently create an internal CCS for any window system buffers and then resolve right before handing it off to X or Wayland. In the case of the single-sampled shadow of a multi-sampled window system buffer, this is pointless because the only thing we do with it is use it as a MSAA resolve target so we do MSAA resolve -> CCS resolve -> hand to the window system. Instead, just disable CCS for the shadow and then the MSAA resolve will write uncompressed directly into it. If the window system supports CCS_E, we will still use CCS_E, we just won't do internal CCS. Reviewed-by: Kenneth Graunke <[email protected]>
* i965/miptree: Rename a parameter to create_for_dri_imageJason Ekstrand2018-06-042-4/+4
| | | | | | | Instead of having it be a general "is this a winsys image" boolean, make it more specific to the actual purpose. Reviewed-by: Kenneth Graunke <[email protected]>
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