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* i965/fs: Don't use backend_visitor::instructions after creating the CFG.Matt Turner2015-03-021-10/+0
| | | | | | | | | | | | | | | | | | | | This is a fix for a regression introduced in commit a9f8296d ("i965/fs: Preserve the CFG in a few more places."). The errata this code works around is described in a comment before the function: "[DevBW, DevCL] Errata: A destination register from a send can not be used as a destination register until after it has been sourced by an instruction with a different destination register. The framebuffer write's sources must be in message registers, which SEND instructions cannot have as a destination. There's no way for this errata to affect anything at the end of the program. Just remove the code. Cc: 10.4, 10.5 <[email protected]> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=84613 Reviewed-by: Kenneth Graunke <[email protected]>
* meta/TexSubImage: Stash everything other than PIXEL_TRANSFER/store in meta_beginJason Ekstrand2015-03-021-4/+4
| | | | | | | | | | | Previously, there were bugs where if the app set a scissor it could affect the area of the texture that was downloaded. There was also potential that the framebuffer SRGB state could affect downloads. This ensures that those will get saved/restored and can't affect the texture download. Cc: 10.5 <[email protected]> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=89292 Reviewed-by: Neil Roberts <[email protected]>
* i915: Remove hand-rolled memcpy implementation.Matt Turner2015-03-022-29/+1
| | | | Reviewed-by: Eric Anholt <[email protected]>
* i965: Remove hand-rolled memcpy implementation.Matt Turner2015-03-022-28/+1
| | | | Reviewed-by: Eric Anholt <[email protected]>
* i965: Consider scratch writes to have side effects.Matt Turner2015-03-021-0/+1
| | | | | | | | We could do better by tracking scratch reads and writes. Cc: 10.5 <[email protected]> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=88793 Reviewed-by: Jason Ekstrand <[email protected]>
* radeon: replace Elements() with ARRAY_SIZE()Brian Paul2015-03-021-10/+10
| | | | Acked-by: Ilia Mirkin <[email protected]>
* r200: replace Elements() with ARRAY_SIZE()Brian Paul2015-03-021-10/+10
| | | | Acked-by: Ilia Mirkin <[email protected]>
* nouveau: replace Elements() with ARRAY_SIZE()Brian Paul2015-03-021-4/+4
| | | | Acked-by: Ilia Mirkin <[email protected]>
* i965: replace Elements() with ARRAY_SIZE()Brian Paul2015-03-025-8/+8
| | | | Acked-by: Ilia Mirkin <[email protected]>
* i915: replace Elements() with ARRAY_SIZE()Brian Paul2015-03-021-1/+1
| | | | Acked-by: Ilia Mirkin <[email protected]>
* i965: Remove the create_raw_surface vtbl hook.Francisco Jerez2015-03-025-47/+8
| | | | | | | | It's a wrapper around emit_buffer_surface_state with format=RAW, pitch=1, rw=true and the remaining arguments ordered differently. There's no point in having a separate vtbl pointer for that. Reviewed-by: Kristian Høgsberg <[email protected]>
* i965: Add missing defines for render cache messages.Francisco Jerez2015-03-022-2/+8
| | | | | | And remove duplicated definition of OWORD_DUAL_BLOCK_WRITE. Reviewed-by: Paul Berry <[email protected]>
* i965/skl: Lay out a 1D miptree horizontallyNeil Roberts2015-03-021-2/+60
| | | | | | | On Gen9+ the 1D miptree is laid out with all of the mipmap levels in a horizontal line. Reviewed-by: Ben Widawsky <[email protected]>
* i965/skl: Lay out 3D textures the same as array texturesNeil Roberts2015-03-021-2/+8
| | | | | | | On Gen9+ the 3D textures use the same mipmap layout as 2D array textures. Reviewed-by: Ben Widawsky <[email protected]>
* i965/skl: Fix the maximum thread count format for the PSNeil Roberts2015-03-021-1/+6
| | | | | | | According to the bspec for some reason the format of the maximum number of threads field has changed from U8-2 to U8-1 for the PS. Reviewed-by: Anuj Phogat <[email protected]>
* i965/gs: Check newly-generated GS-out VUE map against correct stageChris Forbes2015-03-011-1/+1
| | | | | | | | | | | | | | | Previously, we compared our new GS-out VUE map to the existing *VS*-out VUE map, which is bogus. This would mostly manifest as redundant dirty flagging where the GS is in use but the VS and GS output layouts differ; but there is a scary case where we would fail to flag a GS-out layout change if it happened to match the VS-out layout. Signed-off-by: Chris Forbes <[email protected]> Cc: "10.5, 10.4" <[email protected]> Reviewed-by: Matt Turner <[email protected]> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=88885
* i965: add GLSL_TYPE_DOUBLE switch case to silence warningBrian Paul2015-02-281-0/+1
| | | | Reviewed-by: Matt Turner <[email protected]>
* i965/fs/nir: Mark fallthrough.Matt Turner2015-02-281-0/+1
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* i965/fs/nir: Mark fallthrough.Matt Turner2015-02-281-0/+1
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* i965: Avoid applying negate to wrong MAD source.Matt Turner2015-02-272-30/+26
| | | | | | | | | | | | For some given GLSL IR like (+ (neg x) (* 1.2 x)), the try_emit_mad function would see that one of the +'s sources was a negate expression and set mul_negate = true without confirming that it was actually a multiply. Cc: 10.5 <[email protected]> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=89315 Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=89095 Reviewed-by: Ian Romanick <[email protected]>
* i965/vec4: Fix implementation of i2b.Matt Turner2015-02-271-1/+1
| | | | | | | | I broke this in commit 2881b123d. I must have misread i2b as b2i. Cc: 10.5 <[email protected]> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=88246 Reviewed-by: Ian Romanick <[email protected]>
* i965/fs/nir: Use emit_math for nir_op_fpowIan Romanick2015-02-271-1/+1
| | | | | | | | | It appears that all the other instructions that need it already use it. This one just got missed. Signed-off-by: Ian Romanick <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> Cc: "10.5" <[email protected]>
* meta: silence declaration after code warning on MinGWBrian Paul2015-02-271-1/+2
| | | | Reviewed-by: Anuj Phogat <[email protected]>
* meta: silence uninitialized variable warnings for MinGWBrian Paul2015-02-271-0/+2
| | | | Reviewed-by: Anuj Phogat <[email protected]>
* i965: Fix I/L/LA SNORM formats.Kenneth Graunke2015-02-271-1/+19
| | | | | | | | | | | | | | | _mesa_choose_tex_format (texformat.c) tries I8_SNORM, L8_SNORM, and either L8A8_SNORM or A8L8_SNORM, none of which are supported by our driver. Failing that, it falls back to RGBX for luminance, and RGBA intensity and luminance alpha. So, we need to use swizzle overrrides to obtain the correct values. Fixes Piglit's EXT_texture_snorm/fbo-blending-formats and fbo-clear-formats. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> Reviewed-by: Chris Forbes <[email protected]>
* i965/fs: Patch the instruction generating discards; don't use CMP.Z.Kenneth Graunke2015-02-271-2/+3
| | | | | | | | | | | | | | | | | | | CMP.Z doesn't work on Gen4-5 because the boolean isn't guaranteed to be 0 or 0xFFFFFFFF - only the low bit is defined. We can call emit_bool_to_cond_code to generate the condition in f0.0; the last instruction will generate the flag value. We can patch it to use f0.1, and negate the condition. Fixes discard tests on Gen4-5. Haswell shader-db stats: total instructions in shared programs: 5770279 -> 5769112 (-0.02%) instructions in affected programs: 64342 -> 63175 (-1.81%) helped: 1069 Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* i965/fs: Introduce brw_negate_cmod().Kenneth Graunke2015-02-272-0/+23
| | | | | Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* swrast: replace INLINE with inlineBrian Paul2015-02-262-6/+6
| | | | Reviewed-by: Alex Deucher <[email protected]>
* radeon: replace INLINE with inlineBrian Paul2015-02-265-8/+8
| | | | Reviewed-by: Alex Deucher <[email protected]>
* r200: replace INLINE with inlineBrian Paul2015-02-263-4/+4
| | | | Reviewed-by: Alex Deucher <[email protected]>
* i915: replace INLINE with inlineBrian Paul2015-02-2610-22/+22
| | | | Reviewed-by: Alex Deucher <[email protected]>
* mesa: don't include math.h in compiler.hBrian Paul2015-02-262-0/+2
| | | | | | | | Not needed by anything in that header. Include math.h or c99_math.h where needed instead. Reviewed-by: Matt Turner <[email protected]> Reviewed-by: Jose Fonseca <[email protected]>
* mesa: include stdarg.h only where it's usedBrian Paul2015-02-261-0/+1
| | | | | Reviewed-by: Matt Turner <[email protected]> Reviewed-by: Jose Fonseca <[email protected]>
* meta: In pbo_{Get,}TexSubImage don't repeatedly rebind the source texNeil Roberts2015-02-261-4/+0
| | | | | | | | A layered PBO image is now interpreted as a single tall 2D image so the z argument in _mesa_meta_bind_fbo_image is ignored. Therefore this was just redundantly rebinding the same image repeatedly. Reviewed-by: Jason Ekstrand <[email protected]>
* i965/gen8: Use HALIGN_16 if MCS is enabled for non-MSRTAnuj Phogat2015-02-251-0/+3
| | | | | Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Neil Roberts <[email protected]>
* i965: Pass pointer to miptree as function parameter in ↵Anuj Phogat2015-02-251-6/+6
| | | | | | | | | intel_horizontal_texture_alignment_unit This will be used by next patch in the series. Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Neil Roberts <[email protected]>
* i965: Allocate texture buffer in intelTexImageAnuj Phogat2015-02-251-2/+11
| | | | | | | | | before calling _mesa_meta_pbo_TexSubImage(). This will be used in later patches and will be required in Skylake to get the tile resource mode of miptree before calling _mesa_meta_pbo_TexSubImage(). Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Neil Roberts <[email protected]>
* i965: Make a function to check the conditions to use the blitterAnuj Phogat2015-02-251-11/+29
| | | | | | | No functional changes in the patch. Just makes the code look cleaner. Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Neil Roberts <[email protected]>
* i965: Move the comment to the right placeAnuj Phogat2015-02-251-1/+1
| | | | | Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Neil Roberts <[email protected]>
* i965: Fix condition to use Y tiling in blitter in intel_miptree_create()Anuj Phogat2015-02-251-3/+3
| | | | | | | Y tiling is supported in blitter on SNB+. Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Neil Roberts <[email protected]>
* meta: Pass null pointer for the pixel data to avoid unnecessary data uploadAnuj Phogat2015-02-251-1/+4
| | | | | | | to a temporary pbo created in _mesa_meta_pbo_GetTexSubImage(). Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Neil Roberts <[email protected]>
* meta: Fix buffer object assignment to account for both pack and unpack bo'sAnuj Phogat2015-02-251-1/+1
| | | | | | | | | create_texture_for_pbo() is shared by _mesa_meta_pbo_GetTexSubImage() and _mesa_meta_pbo_TexSubImage() functions. So, we need to account for both pack and unpack buffer objects. Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Neil Roberts <[email protected]>
* meta: Use GL_STREAM_READ for pbo created with GL_PIXEL_PACK_BUFFERAnuj Phogat2015-02-251-1/+7
| | | | | | | | | | create_texture_for_pbo() is used by both _mesa_meta_pbo_GetTexSubImage() and _mesa_meta_pbo_TexSubImage() functions with different PBO targets. Use GL_STREAM_READ with GL_PIXEL_PACK_BUFFER and GL_STREAM_DRAW with GL_PIXEL_UNPACK_BUFFER. Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Neil Roberts <[email protected]>
* meta: Add assertion check for ctx->Meta->SaveStackDepthAnuj Phogat2015-02-251-0/+2
| | | | | | | before using it for derefrencing. Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Neil Roberts <[email protected]>
* meta: Do power of two samples check only for samples > 0Anuj Phogat2015-02-251-2/+2
| | | | | | | otherwise samples=0 passes the check, which is invalid. Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Neil Roberts <[email protected]>
* i965: Don't force x-tiling for 16-bpp formats on Gen>7Neil Roberts2015-02-251-3/+3
| | | | | | | | | | | | Sandybridge doesn't support y-tiling for surface formats with 16 or more bpp. There was previously an override to explicitly allow this for Gen7. However, this restriction is also removed in Gen8+ so we should use y-tiling there too. This is important to do for Skylake which doesn't support x-tiling for 3D surfaces. Reviewed-by: Ben Widawsky <[email protected]>
* dri/common: Update comment about driQueryRendererIntegerCommonAndreas Boll2015-02-251-0/+1
| | | | | | | | | Since 87d3ae0b45b6b6bb50b583dafa55eb109449a005 driQueryRendererIntegerCommon handles __DRI2_RENDERER_PREFFERED_PROFILE too. Signed-off-by: Andreas Boll <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* common: Fix PBOs for 1D_ARRAY.Laura Ekstrand2015-02-241-26/+36
| | | | | | | | | | | Corrects the way that _mesa_meta_pbo_TexSubImage and _mesa_meta_pbo_GetTexSubImage handle 1D_ARRAY textures. Fixes a failure in the Piglit arb_direct_state_access/gettextureimage-targets test. Reviewed-by: Jason Ekstrand <[email protected]> Tested-by: Laura Ekstrand <[email protected]> Cc: "10.4, 10.5" <[email protected]>
* common: Correct PBO 2D_ARRAY handling.Laura Ekstrand2015-02-241-9/+17
| | | | | | | | | | | | | | | | | | | Changes PBO uploads and downloads to use a tall (height * depth) 2D texture for blitting. This fixes the bug where 2D_ARRAY, 3D, and CUBE_MAP_ARRAY textures are not properly uploaded and downloaded. Removes the option to use a 2D ARRAY texture for the PBO during upload and download. This option didn't work because the miptree couldn't be set up reliably. v2: Review from Jason Ekstrand and Neil Roberts: -Delete the depth parameter from create_texture_for_pbo -Abandon the option to create a 2D ARRAY texture in create_texture_for_pbo Reviewed-by: Ian Romanick <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> Cc: "10.4, 10.5" <[email protected]>
* common: Correct texture init for meta pbo uploads and downloads.Laura Ekstrand2015-02-241-1/+4
| | | | | | | | | | | | | | | | | This moves the line setting immutability for the texture to after _mesa_initialize_texture_object so that the initializer function will not cancel it out. Moreover, because of the ARB_texture_view extension, immutable textures must have NumLayers > 0, or depth will equal (0-1)=0xFFFFFFFF during SURFACE_STATE setup, which triggers assertions. v2: Review from Kenneth Graunke: - Include more explanation in the commit message. - Make texture setup bug fixes into a separate patch. Reviewed-by: Ian Romanick <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> Cc: "10.4, 10.5" <[email protected]>
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