aboutsummaryrefslogtreecommitdiffstats
path: root/src/mesa/drivers
Commit message (Collapse)AuthorAgeFilesLines
* intel: Also get the DRI2 front buffer when doing front buffer reading.Eric Anholt2009-06-194-1/+29
|
* intel: Update Mesa state before span setup in glReadPixels.Eric Anholt2009-06-193-3/+13
| | | | | We could have mapped the wrong set of draw buffers. Noticed while looking into a DRI2 glean ReadPixels issue.
* intel: Move intel_pixel_read.c to shared for use with i965.Eric Anholt2009-06-192-306/+307
|
* intel: Don't map regions with drm_intel_gem_bo_map_gtt() unless they're tiled.Eric Anholt2009-06-191-2/+4
| | | | | | | | This fixes a regression in region read performance that came in with the texture tiling changes. Ideally we'd have an access flag coming in so we could also use bo_map_gtt for writing, like we do for buffer objects. Bug #22190
* intel: Fix other metaops versus GL_COMPILE_AND_EXECUTE dlists.Eric Anholt2009-06-193-4/+4
| | | | Fixes oglconform zbfunc.c and pxtrans-cidraw.c, at least.
* intel: Fix glClear behavior versus display lists.Eric Anholt2009-06-191-1/+1
| | | | | | The CALL_DrawArrays was leaking the clear's primitives into the display list with GL_COMPILE_AND_EXECUTE. Use _mesa_DrawArrays instead, which doesn't appear to leak. Fixes piglit dlist-clear test.
* intel: Do not access pbo's buffer directly when attaching.Chia-I Wu2009-06-191-2/+7
| | | | | | | | pbo might be system buffer based or attached to another region. Call intel_bufferobj_buffer to make sure pbo has a buffer of its own. Signed-off-by: Chia-I Wu <[email protected]> Signed-off-by: Eric Anholt <[email protected]>
* intel: Data are copied in the wrong direction when breaking COW tie.Chia-I Wu2009-06-191-1/+1
| | | | | Signed-off-by: Chia-I Wu <[email protected]> Signed-off-by: Eric Anholt <[email protected]>
* intel: Fix migration from sys_buffer in intel_bufferobj_buffer.Chia-I Wu2009-06-191-3/+7
| | | | | | | | intel_bufferobj_subdata is called to migrate data from sys_buffer, and it expects only one of buffer or sys_buffer is non-NULL. Signed-off-by: Chia-I Wu <[email protected]> Signed-off-by: Eric Anholt <[email protected]>
* radeon: make cubemap mipmap generation workRoland Scheidegger2009-06-201-16/+13
| | | | | | need to pass target parameter to radeon_teximage/radeon_subteximage functions otherwise mipmap generation for cube maps can't work (assert/segfault in _mesa_generate_mipmap)
* intel: Fixups for 'mesa: create/destroy buffer objects via driver functions'.Michel Dänzer2009-06-193-16/+11
| | | | | | | Initialize all driver function hooks before calling _mesa_initialize_context(), and handle all buffer objects in intel_buffer_object(). Fixes assertion failure when running glxinfo.
* radeon: fix cube maps for non-mm pathRoland Scheidegger2009-06-191-2/+33
| | | | | | | drm cmd checker would refuse cube emits also fix an issue in the cs path which would calculate the register offset off by one dword. Only same testing done as original code (none except compile tested).
* r200: fix cube maps for non-mm pathRoland Scheidegger2009-06-191-1/+28
| | | | drm cmd checker rightfully fell over any cube emit
* i965: initial code for loops in vertex programsBrian Paul2009-06-191-2/+38
|
* i965: asst clean-ups, etc in brw_vs_emit()Brian Paul2009-06-191-11/+10
|
* i965: asst clean-ups, var renaming in brw_wm_emit_glsl()Brian Paul2009-06-191-21/+23
|
* radeons: use dp4 for position invariant vertex programsRoland Scheidegger2009-06-193-0/+6
| | | | | | | | Fixes #22181. R200 requires this since DP4 is used in hw tnl mode. R300 prefers it (should be faster due to no instruction dependencies), but both methods should be correct (when sw tcl is used though, MUL/MAD might be faster). Probably doesn't make much difference for R100 since vertex progs are executed in software anyway, but let's just keep it the same there too.
* mesa: make query-related driver fallback functions staticBrian Paul2009-06-191-8/+4
| | | | Plug them in via _mesa_init_query_object_functions().
* mesa: make buffer object-related driver fallback functions staticBrian Paul2009-06-191-18/+1
| | | | Plug them in via _mesa_init_buffer_object_functions().
* Merge branch 'ext-provoking-vertex'Brian Paul2009-06-191-0/+14
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Conflicts: docs/relnotes-7.6.html progs/tests/Makefile src/gallium/drivers/softpipe/sp_prim_vbuf.c src/glx/x11/indirect.c src/mesa/glapi/Makefile src/mesa/glapi/dispatch.h src/mesa/glapi/glapioffsets.h src/mesa/glapi/glapitable.h src/mesa/glapi/glapitemp.h src/mesa/glapi/glprocs.h src/mesa/main/dlist.c src/mesa/main/enums.c src/mesa/sparc/glapi_sparc.S src/mesa/x86-64/glapi_x86-64.S src/mesa/x86/glapi_x86.S
| * mesa: regenerated API files for GL_EXT_provoking_vertexBrian Paul2009-05-281-8/+22
| |
* | mesa driconf: Add macro to specify an option with a quoted default value.Thomas Hellstrom2009-06-171-0/+4
| | | | | | | | | | | | | | | | | | | | The default values true and false will expand to "1" and "0" when gcc -std=c99, causing bool option defaults to generate runtime failures. One solution is to specify bool option defaults quoted as "true" and "false". Add a macro to assist this. Signed-off-by: Thomas Hellstrom <[email protected]>
* | i965: Add decode for the G4X x,y offset in surface state.Eric Anholt2009-06-171-0/+2
| |
* | i965: Fix up texture layout for small things with wide pitches (tiled)Eric Anholt2009-06-171-1/+1
| | | | | | | | | | | | | | We were packing according to the pitch, while the hardware appears to base it on the base level width. With this and the previous commit, fbo-cubemap now matches untiled behavior.
* | i965: Fall back or appropriately adjust offsets of drawing to tiled regions.Eric Anholt2009-06-173-3/+54
| | | | | | | | | | | | 3D rendering to tiled textures was being done with non-tile-aligned offsets. The G4X hardware has fields to let us support it easily and correctly, while the pre-G4X hardware requires a path full of suffering, so we just fall back.
* | r300: use vbo_split_prims to split up large vertex buffers.Dave Airlie2009-06-182-2/+11
| | | | | | | | This lets ut2004 avoid hitting the elt warning.
* | i965: Fix tiling for FBO depth attachments by making DEPTH_COMPONENT Y tiled.Eric Anholt2009-06-172-4/+8
| | | | | | | | | | This may hurt if miptree relayout occurs, since we can't blit Y tiled objects. But it corrects depth tests on FBOs using textures.
* | radeon: don't re-add BOs to validate listDave Airlie2009-06-181-0/+7
| | | | | | | | | | | | if its on the list its on the list don't go readding it. multitexturing from the same texture could cause this.
* | radeon: Flush command buffer on viewport changeJerome Glisse2009-06-171-0/+1
| | | | | | | | | | | | We flush the command buffer so we don't emit mixed state (with new and previous buffer size) command buffer, this is especialy affecting zbuffer states.
* | r300: don't emit vap index offset on r5xx hw when using csJerome Glisse2009-06-171-1/+1
| | | | | | | | | | | | | | vap index offset is programmed to 0 by the kernel, it would add work to kernel checker to allow userspace programming of this so it's now disallowed with CS on KMS.
* | GLX: attempt to fix glean makeCurrent test cases.Dave Airlie2009-06-171-1/+5
| | | | | | | | | | | | | | | | | | | | | | Two parts to this: One we don't keep pointers to possibly freed memory anymore once we unbind the drawables from the context. Brian I need to figure out what the comment you made there, can we get a glean/piglit test so we can fix it properly? If the new gc is the same as the oldGC, we call the unbind even though we just bound it in that function. doh.
* | radeon: fix warnings in wrapper with libdrmDave Airlie2009-06-171-15/+15
| |
* | Merge branch 'mesa_7_5_branch'Brian Paul2009-06-166-20/+78
|\ \ | | | | | | | | | | | | | | | Conflicts: src/mesa/main/api_validate.c
| * | i965: fix bugs in projective texture coordinatesBrian Paul2009-06-165-20/+54
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For the TXP instruction we check if the texcoord is really a 4-component atttibute which requires the divide by W step. This check involved the projtex_mask field. However, the projtex_mask field was being miscalculated because of some confusion between vertex program outputs and fragment program inputs. 1. Rework the size_masks calculation so we correctly set bits corresponding to fragment program input attributes. 2. Rename projtex_mask to proj_attrib_mask since we're interested in more than just texcoords (generic varying vars too). 3. Simply the indexing of the size_masks and proj_attrib_mask fields. 4. The tracker::active[] array was mis-dimensioned. Use MAX_PROGRAM_TEMPS instead of a magic number. 5. Update comments, add new assertions. With these changes the Lightsmark demo/benchmark renders correctly, until we eventually hit a GPU lockup...
| * | intel: Release fb backing regions in intelDestroyBuffer()Shuang He2009-06-151-0/+24
| | | | | | | | | | | | Fixes memory leak when destroying framebuffers.
* | | i965: handle OPCODE_SWZ in the glsl pathRoland Scheidegger2009-06-161-0/+1
| | | | | | | | | | | | | | | | | | glsl compiler will not generate OPCODE_SWZ, and as a first step it would be translated away to a MOV anyway (why?), but later internally this opcode is generated (for EXT_texture_swizzling).
* | | Merge branch 'arb_map_buffer_range'Brian Paul2009-06-152-4/+31
|\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | Conflicts: docs/relnotes-7.6.html src/mesa/main/mtypes.h
| * | | mesa: implement GL_ARB_map_buffer_rangeBrian Paul2009-06-081-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Only enabled for software drivers at this point. Note that the gl_buffer_object::Access enum field has been replaced by a gl_buffer_object::AccessFlags bitfield. The new field is a mask of the GL_MAP_x_BIT flags which is a superset of the old GL_READ_ONLY, GL_WRITE_ONLY and GL_READ_WRITE modes. When we query GL_BUFFER_ACCESS_ARB we translate the bitfield into the conventional enum values.
| * | | mesa: regenerated files for GL_ARB_map_buffer_rangeBrian Paul2009-06-081-4/+26
| | | |
* | | | enable ARB_half_float_pixel for intel driversRoland Scheidegger2009-06-151-0/+1
| | | |
* | | | intel: fix (cosmetic) typo flag used twiceRoland Scheidegger2009-06-151-1/+0
| | | |
* | | | r300: fix 3D texturesMaciej Cencora2009-06-151-1/+20
| | | |
* | | | i965: interpolate colors with perspective correction by defaultBrian Paul2009-06-126-13/+38
| | | | | | | | | | | | | | | | | | | | | | | | | | | | ...rather than with linear interpolation. Modern hardware should use perspective-corrected interpolation for colors (as for texcoords). glHint(GL_PERSPECTIVE_CORRECTION_HINT, mode) can be used to get linear interpolation if mode = GL_FASTEST.
* | | | r300: add support for EXT_texture_sRGBMaciej Cencora2009-06-124-0/+27
| | | | | | | | | | | | | | | | Tested with glean/texture_srgb and wine/d3d9 tests on RV535
* | | | Merge branch 'mesa_7_5_branch'Jakob Bornecrantz2009-06-121-0/+1
|\ \ \ \ | | |/ / | |/| |
| * | | mesa: add default function for ctx->Driver.CheckQuery() hookBrian Paul2009-06-111-0/+1
| | | |
| * | | osmesa: Allow building standalone in all three channel widthsDan Nicholson2009-06-041-27/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | autoconf had been designating the 8 bit libOSMesa as the default standalone osmesa, but the Makefile expected it to be linked to libGL. Fix up the osmesa Makefile so that it allows any of the combinations of standalone and channel width to be built. Fixes bug #21980. (cherry picked from commit 7441dcd90b01df8351026af8bbb50e11bb86071a)
| * | | intel: Clip to window after calling Driver.TexImage2DIan Romanick2009-06-021-9/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This prevents the width / height from being clipped to the window size before the texture is allocated. This matches intelCopyTexImage1D. This should fix bug #21227 Signed-off-by: Ian Romanick <[email protected]> (cherry picked from commit 129f311673c99eb912d659023e50bc5f0ef53249)
* | | | radeon: fix size of mipmap texture arrayDave Airlie2009-06-121-1/+3
| | | |
* | | | radeon/r200/r300: fix max texture levels assertDave Airlie2009-06-122-6/+3
| | | | | | | | | | | | | | | | use the actual value set in the context
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-12 09:21:22 +0000