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* i965: warning fixEric Anholt2009-08-041-1/+1
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* i965: Fix RECT shadow sampling by not losing the other texcoords.Eric Anholt2009-08-041-1/+5
| | | | Bug #20821
* i965: Assert that the offset in the VBO is below the VBO size.Eric Anholt2009-08-031-0/+14
| | | | | | | | | | This avoids sending a bad buffer address to the GPU due to programmer error, and is permitted by the ARB_vbo spec. Note that we still have the opportunity to dereference past the end of the GPU, because we aren't clipping to a correct _MaxElement, but that appears to be harder than it should be. This gets us the 90% solution. Bug #19911.
* i965: Even if no VS inputs are set, still load some amount of URB as required.Eric Anholt2009-08-031-0/+11
| | | | | | See comment on Vertex URB Entry Read Length for VS_STATE. This, combined with the previous three commits, fixes #22945.
* i965: Make sure the VS URB size is big enough to fit a VF VUE.Eric Anholt2009-08-031-2/+8
| | | | | This fix is just from code and docs inspection, but it may fix hangs on some applications.
* i965: Don't emit bad packets when no VBs are referenced.Eric Anholt2009-08-031-0/+22
| | | | | | | | | It appears that sometimes Mesa (and I suppose a VS could as well) emits a program which references no vertex data, and thus we end up with nr_enabled == 0 even though some VBs are enabled. We'd end up emitting VB/VE packet headers of 0xffffffff in that case, leading to GPU hangs. Bug #22945 (wine with an uncompiled VS)
* i965: Calculate enabled[] and nr_enabled once and re-use the values.Eric Anholt2009-08-032-29/+18
| | | | The code duplication bothered me.
* radeon: more fixes for compressed texturesRoland Scheidegger2009-08-042-11/+30
| | | | | | | | | | | | | | | | - fix not respecting required hardware stride with compressedTexImage - this fixes #22615. - make sure correct stride is used in various places - fix stored miptree never matching with a TexImage call with compressed texture - don't always store data with compressedtexsubimage at offset 0, and actually use the supplied pixel data... (untested) - make sure rows for compressed texture handling are rounded up not down Note that trying to access stored compressed textures in hardware miptrees from core mesa (get_compressed_teximage, swrast fallbacks) can't work correctly, since RowStride isn't really set to anything useful, plus some places (at least get_compressed_teximage) assume this data has native stride and no padding.
* radeon: Fix inverted test for disabling flushing of front buffer output.Eric Anholt2009-08-031-1/+1
| | | | (corresponding fix to the intel driver one)
* intel: Fix inverted test for disabling flushing of front buffer output.Eric Anholt2009-08-031-1/+1
| | | | | | | | The comment disagreed with the code, and nicely drew my eyes to what was going wrong. Bug #21774 (blender) Bug #21788 (readpix)
* intel: Wait on the last swapbuffers to complete before queuing a new one.Eric Anholt2009-08-033-0/+28
| | | | | | | | | | | This fixes jerkiness in doom3 and other apps since the kernel change to throttle less absurdly, which led to a thundering herd of frames. Because this is a rather minimal fix, there is at least one downside: If the whole scene completes in one batchbuffer, we'll end up stalling the GPU. Thanks to Michel Dänzer for suggesting using glFlush to signal frame end instead of going to all the effort of adding a new DRI2 extension.
* r600: add some new r7xx pci idsAlex Deucher2009-08-032-0/+10
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* egl: Replace IsBound by a pointer to the binding.Chia-I Wu2009-08-031-2/+2
| | | | | | | | | IsBound tells if a context or surface is current. What it does not tell is, to which thread a context is current, or to which context a surface is current. This commit replaces IsBound by a pointer to the binding thread or context. Signed-off-by: Chia-I Wu <[email protected]>
* r600: add some missing pci idsAlex Deucher2009-08-032-0/+4
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* r600: fix the build when RADEON_DEBUG_BO is setAlex Deucher2009-08-031-1/+1
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* r600: fix r600SetTexOffsetAlex Deucher2009-08-033-5/+39
| | | | | | | | | We need to properly set up a fake bo for the texture override, so add a new function to radeon_bo_legacy.c. This could probably be used on radeon/r200/r300 to unify the bo handling for texture override. compiz now works :)
* r600: handle state emit betterAlex Deucher2009-08-023-8/+16
| | | | | - move shader-related state with the rest of the shader setup/emit - start to track dirty state better
* r600: Logic Operations Fixvehemens2009-08-021-5/+37
| | | | fixes bug 23087
* r600: fix regression in texenvAlex Deucher2009-08-023-60/+37
| | | | Emit shader consts with the shader program itself
* r300: Fix a regression on non-KMSNicolai Hähnle2009-08-021-8/+11
| | | | | | The regression was introduced by 9a1c336253579d8b58b31910325227b22b4af395 Signed-off-by: Nicolai Hähnle <[email protected]>
* r600: fix rectangle texturesAlex Deucher2009-08-012-11/+27
| | | | | | | | It might be better to add an instruction to normalize the coordinates for rectanglular textures as there are some limitations to wrap modes on unnormalized tex coords. fixes texrect
* r300: Fix corner-case of KIL on R300Nicolai Hähnle2009-08-012-51/+60
| | | | | | | | R300 hardware (but _not_ R500) hardware requires an enabled texture unit if KIL is used in fragment programs. We now work around the CS checker correctly when enabling such a fake texture unit. Signed-off-by: Nicolai Hähnle <[email protected]>
* r300: Fix Z buffer re-emit after window resizeNicolai Hähnle2009-08-012-5/+9
| | | | | | | | | | | | | | We used to not always correctly re-emit the Z buffer size in all cases, in particular the clear path, and invalidated state was not always picked up correctly. This fixes a bug where the kernel CS checker correctly complains about a Z buffer that is too small. Note that this bug was probably only visible with ridiculously high framerates, i.e. glxgears. Signed-off-by: Nicolai Hähnle <[email protected]>
* radeon: fix r100/r200 compressed texture strideRoland Scheidegger2009-07-312-6/+12
| | | | | | | | This almost fixes compressed mipmapped textures on r200, though some small mip levels are still broken. Leave r300 compressed texture stride as is though afaik it's different to pre-radeon-rewrite too. Also do the fixup for rs600 uncompressed row stride at same place.
* radeon: s/r300/radeon in shared code error messageRoland Scheidegger2009-07-311-1/+1
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* radeon: Cliprects has to be updated before doing anything with clip rectanglesPauli Nieminen2009-07-311-1/+2
| | | | | | | Reported to fix corruption while dragging an active window by John Bridgman. Signed-off-by: Pauli Nieminen <[email protected]> Signed-off-by: Nicolai Hähnle <[email protected]>
* radeon: Remove unused variable from context.Pauli Nieminen2009-07-312-3/+0
| | | | Signed-off-by: Nicolai Hähnle <[email protected]>
* r600: make sure bos are valid before usign thatAlex Deucher2009-07-312-0/+15
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* r600: fix reloc setupAlex Deucher2009-07-311-37/+31
| | | | | | | re-use the same reloc index for bos that are referenced multiple times. Fixes rain demo.
* r600: remove unused offset_mod stuffAlex Deucher2009-07-316-81/+14
| | | | this is a step in migrating to the common cs code
* r600: ensure we have enough room for full state emitAlex Deucher2009-07-314-12/+5
| | | | | | full state is roughly 4000 dwords, but will vary depending on the rendering. Also fix some warnings.
* r600: unify state emit into one functionAlex Deucher2009-07-313-28/+34
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* r600: re-arrange state setup and emit so they are not mixedAlex Deucher2009-07-314-108/+130
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* Rename TGSI LOOP instruction to better match theri usage.Michal Krol2009-07-311-1/+1
| | | | | | | | The LOOP/ENDLOOP pair is renamed to BGNFOR/ENDFOR as its behaviour is similar to a C language for-loop. The BGNLOOP2/ENDLOOP2 pair is renamed to BGNLOOP/ENDLOOP as now there is no name collision.
* r600: get updated pending age from cs ioctlAlex Deucher2009-07-311-34/+3
| | | | REQUIRES AN UPDATED DRM
* r600: warning fixesAlex Deucher2009-07-302-9/+1
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* r600: split primitive draw into a separate functionAlex Deucher2009-07-302-57/+60
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* r300/compiler: Remove inst_offset from r500_fragment_program_codeNicolai Hähnle2009-07-303-6/+4
| | | | | | | | The field is not used, and in any case it would be more interesting to manipulate from *outside* the compiler if we ever wanted to load several fragment programs at the same time or something. Signed-off-by: Nicolai Hähnle <[email protected]>
* i965: Postpone ff_sync message in CLIP kernel on IGDNGXiang, Haihao2009-07-306-20/+53
| | | | In addition, it guarantees ff_sync message is issued
* r600: fix mipmapsAlex Deucher2009-07-302-1/+6
| | | | redbook mipmap works
* i915: Add support for EXT_stencil_two_side and ATI_separate_stencil.Eric Anholt2009-07-296-54/+115
| | | | Passes tests/stencil_twoside and glean/stencil2.
* i915: Add ARB_point_sprite since we already expose NV_point_sprite.Eric Anholt2009-07-291-0/+1
| | | | It's all fallbacks anyway due to the DD_POINT_ATTEN fallback.
* r600: remove extraneous semicolonAlex Deucher2009-07-291-1/+1
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* r600: fix texture pitch alignmentAlex Deucher2009-07-294-6/+21
| | | | fixes texwrap
* r600: minor fixesAlex Deucher2009-07-293-2/+16
| | | | | | - set MAX_LOD properly - min texel pitch is 8 texels - emit old command buffer when re-initing base state
* r300: Cleanup r300_fragment_program_codeNicolai Hähnle2009-07-294-115/+145
| | | | | | Configuration register values are now stored directly in that structure. Signed-off-by: Nicolai Hähnle <[email protected]>
* r300/compiler: Adapt AllocateHwInputs interface to common usage patternNicolai Hähnle2009-07-293-5/+6
| | | | Signed-off-by: Nicolai Hähnle <[email protected]>
* swrast: enable ARB_vertex_array_object.Eric Anholt2009-07-291-0/+2
| | | | It was getting enabled anyway but without the entrypoints installed. Whoops.
* r600: emit fog color in PS input map, fix fog related applicationsCooper Yuan2009-07-291-0/+13
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* R6xx/r7xx: VS export fog color as parameterCooper Yuan2009-07-292-0/+22
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