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* i965/fs: Fix slight layering violation in emit_single_fb_writes().Francisco Jerez2015-07-291-12/+10
| | | | | | | | | | | | | | | | | In cases where the color0 argument wasn't being provided, emit_single_fb_writes() would take the alpha channel directly from the visitor state instead of taking it from its arguments. This sort of hack didn't fit nicely into the logical send-message approach because all parameters of the instruction have to be visible to the SIMD lowering pass for it to be able to split them into halves at all. Fix it by using LOAD_PAYLOAD in fs_visitor::emit_fb_writes() to provide an actual color0 vector with undefined contents except for the alpha component to match the previous behavior when no color buffers are enabled. Reviewed-by: Jason Ekstrand <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965/fs: Make sure that the type sizes are compatible during copy propagation.Francisco Jerez2015-07-291-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | It's surprising that we weren't checking for this already. A future patch will cause code like the following to be emitted: MOV(16) tmp<1>:uw, src MOV(8) dst<1>:ud, tmp<8,8,1>:ud The second MOV comes from the expansion of a LOAD_PAYLOAD header copy, so I don't have control over its types. Copy propagation will happily turn this into: MOV(8) dst<1>:ud, src Which has different semantics. Fix it by preventing propagation in cases where a single channel of the instruction would span several channels of the copy (this requirement could in fact be relaxed if the copy is just a trivial memcpy, but this case is unusual enough that I don't think it matters in practice). I'm deliberately only checking if the type of the instruction is larger than the original, because the converse case seems to be handled correctly already in the code below. Reviewed-by: Jason Ekstrand <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965/fs: Honour the instruction force_sechalf and exec_size fields for FB ↵Francisco Jerez2015-07-291-2/+2
| | | | | | | | | | writes. We were previously guessing the half based on the EOT flag which seems rather gross. Reviewed-by: Jason Ekstrand <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965/fs: Define logical framebuffer write opcode.Francisco Jerez2015-07-294-1/+53
| | | | | | | | | | | | | | | | The logical variant is largely equivalent to the original opcode but instead of taking a single payload source it expects its arguments that make up the payload separately as individual sources, like: fb_write_logical null, color0, color1, src0_alpha, src_depth, dst_depth, sample_mask, num_components This patch defines the opcode and usual instruction boilerplate, including a placeholder lowering function provided mainly as self-documentation. Reviewed-by: Jason Ekstrand <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965/fs: Implement pass to lower instructions of unsupported SIMD width.Francisco Jerez2015-07-292-0/+144
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This lowering pass implements an algorithm to expand SIMDN instructions into a sequence of SIMDM instructions in cases where the hardware doesn't support the original execution size natively for some particular instruction. The most important use-cases are: - Lowering send message instructions that don't support SIMD16 natively into SIMD8 (several texturing, framebuffer write and typed surface operations). - Lowering messages that don't support SIMD8 natively into SIMD16 (*cough*gen4*cough*). - 64-bit precision operations (e.g. FP64 and 64-bit integer multiplication). - SIMD32. The algorithm works by splitting the sources of the original instruction into chunks of width appropriate for the lowered instructions, and then interleaving the results component-wise into the destination of the original instruction. The pass is controlled by the get_lowered_simd_width() function that currently just returns the original execution size making the whole pass a no-op for the moment until some user is introduced. Reviewed-by: Jason Ekstrand <[email protected]> v2: Reverse order of the source transformations and split_inst emit call to make the code a bit easier to understand.
* i965/fs: Fix return value of fs_inst::regs_read() for BAD_FILE.Francisco Jerez2015-07-291-0/+1
| | | | | | | | | | | | Typically BAD_FILE sources are used to mark a source as not present what implies that no registers are read. This will become much more frequent with logical send opcodes which have a large number of sources, many of them optionally used and marked as BAD_FILE when they aren't applicable. It will prove to be useful to be able to rely on the value of regs_read() regardless of whether a source is present or not. Reviewed-by: Jason Ekstrand <[email protected]>
* i965/fs: Add builder emit method taking a variable number of source registers.Francisco Jerez2015-07-291-3/+12
| | | | | | | | And start using it in fs_builder::LOAD_PAYLOAD(). This will be used to emit logical send message opcodes which have an unusually large number of arguments. Reviewed-by: Jason Ekstrand <[email protected]>
* i965/fs: Add stub lowering pass for logical send-message opcodes.Francisco Jerez2015-07-292-1/+29
| | | | | | | | | | | | | | | | This pass will house ad-hoc lowering code for several send message-like virtual opcodes that will represent their logically independent arguments as separate instruction sources rather than as a single payload blob. This pass will basically just take the separate arguments that are supposed to be part of the payload and concatenate them to construct a message in the form required by the hardware. Virtual instructions in separate-source form will eventually allow some simplification of the visitor code and make several transformations easier like lowering SIMD16 instructions to SIMD8 algorithmically in cases where the hardware doesn't support the former natively. Reviewed-by: Jason Ekstrand <[email protected]>
* i965/fs: Factor out source components calculation to a separate method.Francisco Jerez2015-07-292-10/+24
| | | | | | | | | | | | | | | | | | This cleans up fs_inst::regs_read() slightly by disentangling the calculation of "components" from the handling of message payload arguments. This will also simplify the SIMD lowering and logical send message lowering passes, because it will avoid expressions like 'regs_read * REG_SIZE / component_size' which are not only ugly, they may be inaccurate because regs_read rounds up the result to the closest register multiple so they could give incorrect results when the component size is lower than one register (e.g. uniforms). This didn't seem to be a problem right now because all such expressions happen to be dealing with per-channel GRFs only currently, but that's by no means obvious so better be safe than sorry. v2: Split PIXEL_X/Y and LINTERP into separate case blocks. Reviewed-by: Jason Ekstrand <[email protected]>
* i965/fs: Simplify instruction rewrite loop in the register coalesce pass.Francisco Jerez2015-07-291-14/+13
| | | | | | | | | | | | For some reason the loop that rewrites all occurrences of the coalesced register was iterating over all possible offsets until it would find one that compares equal to the offset of a source or destination of any instruction in the program. Since the mapping between old and new offsets is already available in the regs_to_offset array and we know that the whole register has been coalesced we can just look it up. Reviewed-by: Jason Ekstrand <[email protected]>
* i965/fs: Fix rewrite of the second half of 16-wide coalesced registers.Francisco Jerez2015-07-291-15/+12
| | | | | | | | | | | | | | | | | | | | | | | | The register coalesce pass wasn't rewriting the destination and sources of instructions that accessed the second half of a coalesced register previously copied with a 16-wide MOV instruction. E.g.: | ADD (16) vgrf0:f, vgrf0:f, 1.0:f | MOV (16) vgrf1:f, vgrf0:f | MOV (8) vgrf2:f, vgrf0+1:f { sechalf } would get incorrectly register-coalesced into: | ADD (16) vgrf1:f, vgrf1:f, 1.0:f | MOV (8) vgrf2:f, vgrf0+1:f { sechalf } The reason is that the mov[i] pointer was being left equal to NULL for every other register. The fact that we've made it to the rewrite loop implies that the whole register will be coalesced, so it doesn't seem right not to update something that uses it depending on whether mov[i] is NULL or not. Fixes an amount of texturing and image_load_store piglit tests on my SIMD-lowering branch. Reviewed-by: Jason Ekstrand <[email protected]>
* i965/fs: Detect multi-register MOVs correctly in register_coalesce.Francisco Jerez2015-07-291-1/+1
| | | | | | | | | | | register_coalesce() was considering the exec_size of the MOV instruction alone to decide whether the register at offset+1 of the source VGRF was being copied to inst->dst.reg_offset+1 of the destination VGRF, which is only a valid assumption if the move has a 32-bit execution type. Use regs_read() instead to find out the number of registers copied by the instruction. Reviewed-by: Jason Ekstrand <[email protected]>
* i965: Use real stage in "Unsupported form of variable indexing" warning.Kenneth Graunke2015-07-281-2/+3
| | | | | | | Other stages can be miserably slow too! Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Tapani Pälli <[email protected]>
* meta/copy_image: Stash off the scissorJason Ekstrand2015-07-281-2/+2
| | | | | | | | | | | The meta CopyImageSubData path uses BlitFramebuffers to do the actual copy. The only thing that can affect BlitFramebuffers other than the currently bound framebuffers is the scissor so we need to save that off and reset it. If we don't do this, applications that use a scissor together with CopyImageSubData will get accidentally scissored copies. Tested-by: Markus Wick <markus at selfnet.de> Reviewed-by: Anuj Phogat <[email protected]>
* i965: Support importing R8 and GR88 dma_bufsChad Versace2015-07-281-0/+6
| | | | | | | | | | | EGL_EXT_image_dma_buf_import now supports those formats. Tests: - Tested by Piglit ext_image_dma_buf_import-transcode-nv12-as-r8-gr88. - Tested by Peter in Kodi/XBMC to obtain 60fps NV12 transcode at 4K. Tested-by: Peter Frühberger <[email protected]> Signed-off-by: Chad Versace <[email protected]>
* meta: Use _mesa_need_rgb_to_luminance_conversion() in decompress_texture_image()Anuj Phogat2015-07-241-5/+2
| | | | | Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Iago Toral Quiroga <[email protected]>
* mesa: Change the signature of _mesa_need_rgb_to_luminance_conversion()Anuj Phogat2015-07-241-1/+3
| | | | | | | | | This allows us to handle cases when texImage->_BaseFormat doesn't match _mesa_format_get_base_format(texImage->Format). _BaseFormat is what we care about in this function. Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Iago Toral Quiroga <[email protected]>
* meta: Fix reading luminance texture as rgba in _mesa_meta_pbo_GetTexSubImage()Anuj Phogat2015-07-241-2/+34
| | | | | | | | | | | | | | After recent addition of pbo testing in piglit test getteximage-luminance, it fails on i965. This patch makes a sub test pass. This patch adds a clear color operation to meta pbo path, which I think is better than falling back to software path. V2: Fix color mask for GL_LUMINANCE_ALPHA Cc: <[email protected]> Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Iago Toral Quiroga <[email protected]>
* meta: Use _mesa_need_luminance_to_rgb_conversion() in decompress_texture_image()Anuj Phogat2015-07-241-10/+2
| | | | | Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Iago Toral Quiroga <[email protected]>
* meta: Use _mesa_unpack_format_to_base_format() to handle integer formatsAnuj Phogat2015-07-241-4/+2
| | | | | | | | | | Replace a call to mesa_base_tex_format() that handles only internal formats with a call to the new _mesa_unpack_format_to_base_format() function that handles allowed unpack formats and does not care for internal formats at all. Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Iago Toral Quiroga <[email protected]>
* mesa: Set green, blue channels to zero only for formats with these componentsAnuj Phogat2015-07-241-3/+10
| | | | | | | | | This is an optimization which avoids setting pixel transfer operations when not required. _mesa_ReadPixels falls back to slower path if transfer operations are set. Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Iago Toral Quiroga <[email protected]>
* meta: Don't do fragment color clamping in _mesa_meta_pbo_GetTexSubImageAnuj Phogat2015-07-241-0/+5
| | | | | | | | | | | | | | | _mesa_meta_pbo_GetTexSubImage() uses _mesa_meta_BlitFrameBuffer(), which will do fragment clamping if enabled. But fragment clamping doesn't affect ReadPixels and GetTexImage. Without this patch, piglit test arb_color_buffer_float-clear fails, when forced to use the meta pbo path. v2: Apply this fix to both glReadPixels and glGetTexImage. Cc: <[email protected]> Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Iago Toral Quiroga <[email protected]>
* meta: Abort meta pbo path if readpixels need signed-unsigned conversionAnuj Phogat2015-07-241-0/+26
| | | | | | | | | | | | | | | | Meta pbo path for ReadPixels rely on BlitFramebuffer which doesn't support signed to unsigned integer conversions and vice versa. Without this patch, piglit test fbo_integer_readpixels_sint_uint fails, when forced to use the meta pbo path. v2: Make need_signed_unsigned_int_conversion() a static function. (Iago) Bump up the comment and the commit message. (Jason) Signed-off-by: Anuj Phogat <[email protected]> Cc: <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> Reviewed-by: Iago Toral <[email protected]>
* meta: Fix transfer operations check in meta pbo path for readpixelsAnuj Phogat2015-07-241-4/+9
| | | | | | | | | | | | | | | | | | | Currently used ctx->_ImageTransferState check is not sufficient because it doesn't include the read color clamping enabled with GL_CLAMP_READ_COLOR. So, use the helper function _mesa_get_readpixels_transfer_ops(). Also, transfer operations don't affect glGetTexImage(). So, do the check only for glReadPixles. Without this patch, arb_color_buffer_float-readpixels test fails, when forced to use meta pbo path. V2: Add a comment and bump up the commit message. Signed-off-by: Anuj Phogat <[email protected]> Cc: <[email protected]> Reviewed-by: Iago Toral Quiroga <[email protected]>
* i965: Use updated kernel interface for accurate TIMESTAMP readsChris Wilson2015-07-243-17/+49
| | | | | | | | | | | | | | | | | | | | | | | | | | | | I was mistaken, I thought we already had fixed this in the kernel a couple of years ago. We had not, and the broken read (the hardware shifts the register output on 64bit kernels, but not on 32bit kernels) is now enshrined into the ABI. I also had the buggy architecture reversed, believing it to be 32bit that had the shifted results. On the basis of those mistakes, I wrote commit c8d3ebaffc0d7d915c1c19d54dba61fd1e57b338 Author: Chris Wilson <[email protected]> Date: Wed Apr 29 13:32:38 2015 +0100 i965: Query whether we have kernel support for the TIMESTAMP register once Now that we do have an extended register read interface for always reporting the full 36bit TIMESTAMP (irrespective of whether the hardware is buggy or not), make use of it and in the process fix my reversed detection of the buggy reads for unpatched kernels. Signed-off-by: Chris Wilson <[email protected]> Cc: Martin Peres <[email protected]> Cc: Kenneth Graunke <[email protected]> Cc: Michał Winiarski <[email protected]> Cc: Daniel Vetter <[email protected]> Tested-and-acked-by: Chris Forbes <[email protected]> Reviewed-by: Daniel Vetter <[email protected]>
* radeon: Silence GCC unused-but-set-variable warnings.Vinson Lee2015-07-231-1/+5
| | | | | | | | | | | | | | | | | | | | | | radeon_fbo.c: In function 'radeon_map_renderbuffer_s8z24': radeon_fbo.c:162:9: warning: variable 'ret' set but not used [-Wunused-but-set-variable] int ret; ^ radeon_fbo.c: In function 'radeon_map_renderbuffer_z16': radeon_fbo.c:200:9: warning: variable 'ret' set but not used [-Wunused-but-set-variable] int ret; ^ radeon_fbo.c: In function 'radeon_map_renderbuffer': radeon_fbo.c:242:8: warning: variable 'ret' set but not used [-Wunused-but-set-variable] int ret; ^ radeon_fbo.c: In function 'radeon_unmap_renderbuffer': radeon_fbo.c:419:14: warning: variable 'ok' set but not used [-Wunused-but-set-variable] GLboolean ok; ^ Signed-off-by: Vinson Lee <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* i965: add support for ARB_shader_subroutineDave Airlie2015-07-245-0/+13
| | | | | | | | This just adds some missing pieces to nir/i965, it is lightly tested on my Haswell. Reviewed-by: Kenneth Graunke <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* i965: fix warning since tess merge.Dave Airlie2015-07-231-0/+2
| | | | Signed-off-by: Dave Airlie <[email protected]>
* glsl: pass shader stage to lower_output_reads and handle tess controlIlia Mirkin2015-07-231-1/+1
| | | | | | | | | | | | | Tessellation control outputs can be read in directly without first having been written. Accessing these will require some special logic anyways, so just let them through. V2: Never lower tess control output reads, whether patch or not -- both can be read back by other threads. Signed-off-by: Ilia Mirkin <[email protected]> Signed-off-by: Chris Forbes <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* glsl: don't lower variable indexing on non-patch tessellation inputs/outputsMarek Olšák2015-07-231-3/+5
| | | | | | | | | | | | There is no way to lower them, because the array sizes are unknown at compile time. Based on a patch from: Fabian Bieler <[email protected]> v2: add comments Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Dave Airlie <[email protected]>
* mesa: add tessellation shader enumsFabian Bieler2015-07-232-1/+5
| | | | | | | Reviewed-by: Jordan Justen <[email protected]> Reviewed-by: Matt Turner <[email protected]> Reviewed-by: Ian Romanick <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* drirc: drop support for Heaven 3.0, fixes tessellation in 4.0Marek Olšák2015-07-231-20/+3
| | | | Reviewed-by: Kenneth Graunke <[email protected]>
* dri/common: remove unused drm_version variableEmil Velikov2015-07-225-34/+1
| | | | | | | | | | | | As of last commit the only user of it (radeon/r200) no longer uses it. As such let's remove it and cleanup the nasty hacks that we had in place to support this. v2: Leave LIBDRM_CFLAGS around. Signed-off-by: Emil Velikov <[email protected]> Reviewed-by: Michel Dänzer <[email protected]> (v1) Reviewed-by: Marek Olšák <[email protected]> (v1)
* radeon,r200: allow hyperz for radeon DRM module v2Emil Velikov2015-07-222-15/+4
| | | | | | | | | | The original code only half considered hyperz as an option. As per previous commit "major != 2 cannot occur" we can simply things, and allow users to set the option if they choose to do so. Signed-off-by: Emil Velikov <[email protected]> Reviewed-by: Michel Dänzer <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* radeon,r200: remove support for UMS radeon DRM moduleEmil Velikov2015-07-221-27/+17
| | | | | | | | | | | | | | As mentioned by Michel Dänzer "FWIW though, any code which is specific to radeon DRM major version 1 can be removed, because that's the UMS major version." and Marek Olšák "major != 2" can't occur. You don't have to check the major version at all and you can just assume it's always 2." Signed-off-by: Emil Velikov <[email protected]> Reviewed-by: Michel Dänzer <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* radeon,r200: remove unused variable texmicrotileEmil Velikov2015-07-224-8/+0
| | | | | | | | | | Dead since at least 2009 with commit ccf7814a315(radeon: major cleanups removing old dead codepaths.) Signed-off-by: Emil Velikov <[email protected]> Reviewed-by: Michel Dänzer <[email protected]> Reviewed-by: Marek Olšák <[email protected]> Reviewed-by: Roland Scheidegger <[email protected]>
* swrast: remove unneeded __NOT_HAVE_DRM_H defineEmil Velikov2015-07-221-1/+0
| | | | | | No longer applicable since the cleanup of dri_interface.h. Signed-off-by: Emil Velikov <[email protected]>
* dri/common: use HAVE_LIBDRM over __NOT_HAVE_DRM_HEmil Velikov2015-07-224-18/+5
| | | | | | See previous commit message for details. Signed-off-by: Emil Velikov <[email protected]>
* dri/swrast: automake: add LIBDRM_CFLAGSEmil Velikov2015-07-221-0/+1
| | | | | | | | | | | | | With the follow up commit we'll remove the __NOT_HAVE_DRM_H macro. As requested by Ian HAVE_LIBDRM will be used instead, which will lead to swrast including drm.h when libdrm package is available, even though we don't need/make use of the header. As the define is added after the AM_CFLAGS we cannnot use -UHAVE_LIBDRM, but instead let's just add LIBDRM_CFLAGS. The latter of which will expand to NULL when the libdrm package is not around. Signed-off-by: Emil Velikov <[email protected]>
* mesa: replace Driver.GetCompressedTexImage() w/ GetCompressedTexSubImage()Brian Paul2015-07-211-1/+1
| | | | | | | For now, pass offsets of zero and width/height/depth equal to the whole image. Reviewed-by: Ilia Mirkin <[email protected]>
* mesa: replace Driver.GetTexImage with GetTexSubImage()Brian Paul2015-07-214-24/+33
| | | | | | | | | | | | | | | The new driver hook has x/y/zoffset and width/height/depth parameters for the new glGetTextureSubImage() function. The meta code and gallium state tracker are updated to handle the new parameters. Callers to Driver.GetTexSubImage() pass in offsets=0 and sizes equal to the whole texture size. v2: update i965 driver code, s/GLint/GLsizei/ in GetTexSubImage hook Reviewed-by: Ilia Mirkin <[email protected]>
* meta: add offset, width, height parameters to decompress_texture_image()Brian Paul2015-07-211-5/+5
| | | | | | In preparation for decompressing texture sub images. Reviewed-by: Ilia Mirkin <[email protected]>
* meta: handle subimages in _mesa_meta_setup_texture_coords()Brian Paul2015-07-213-33/+65
| | | | | | v2: fix depth, total_depth mix-up in meta.h, per Laura Ekstrand. Reviewed-by: Anuj Phogat <[email protected]>
* Revert "i965/gen9: Plugin the code for selecting YF/YS tiling on skl+"Anuj Phogat2015-07-211-92/+17
| | | | | | | | | | | | | | Commit c9dbdc0 introduced some dead code which is supposed to be used once we have Yf/Ys tiling working and performing better. Ken reported the issue that static analysis tool now shows warnings due to the dead code. To fix these warnings, this patch reverts the changes made in commit c9dbdc0. It'll be better to add the Yf/Ys tiling selection code later, when we are ready to use it. Signed-off-by: Anuj Phogat <[email protected]> Acked-by: Kenneth Graunke <[email protected]>
* i965: Fix stride field for the result of emit_uniformize().Francisco Jerez2015-07-214-19/+26
| | | | | | | | | | | | | | | | | | | This is essentially the same problem fixed in an earlier patch for immediates. Setting the stride to zero will be particularly useful for my future SIMD lowering pass, because we will be able to just check whether the stride of a source register is zero and skip emitting the copies required to unzip it in that case. Instead of setting stride to zero in every caller of emit_uniformize() I've changed the function to return the result as its return value (previously it was being written into a caller-provided destination register), because this way we can enforce that the result is used with the correct regioning from the function itself. The changes to the prototype of its VEC4 counterpart are mainly for the sake of symmetry, VEC4 registers don't have stride. Reviewed-by: Samuel Iglesias Gonsálvez <[email protected]>
* i965/fs: Fix stride field for uniforms.Francisco Jerez2015-07-211-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This fixes essentially the same problem as for immediates. Registers of the UNIFORM file are typically accessed according to the formula: read_uniform(r, channel_index, array_index) = read_element(r, channel_index * 0 + array_index * 1) Which matches the general direct addressing formula for stride=0: read_direct(r, channel_index, array_index) = read_element(r, channel_index * stride + array_index * max{1, stride * width}) In either case if reladdr is present the access will be according to the composition of two register regions, the first one determining the per-channel array_index used for the second, like: read_indirect(r, channel_index, array_index) = read_direct(r, channel_index, read(r.reladdr, channel_index, array_index)) where: read(r, channel_index, array_index) = if r.reladdr == NULL then read_direct(r, channel_index, array_index) else read_indirect(r, channel_index, array_index) In conclusion we can handle uniforms consistently with the other register files if we set stride to zero. After lowering to a GRF using VARYING_PULL_CONSTANT_LOAD in demote_pull_constant_loads() the stride of the source is set to one again because the result of VARYING_PULL_CONSTANT_LOAD is generally non-uniform. Reviewed-by: Samuel Iglesias Gonsálvez <[email protected]>
* i965/fs: Fix stride for immediate registers.Francisco Jerez2015-07-212-0/+7
| | | | | | | | | | | | | | | | | | | When the width field was removed from fs_reg the BROADCAST handling code in opt_algebraic() started to miss a number of trivial optimization cases resulting in the ugly indirect-addressing sequence to be emitted unnecessarily for some variable-indexed texturing and UBO loads regardless of one of the sources of BROADCAST being immediate. Apparently the reason was that we were setting the stride field to one for immediates even though they are typically uniform. Width used to be set to one too which is why this optimization used to work previously until the "reg.width == 1" check was removed. The stride field of vector immediates is intentionally left equal to one, because they are strictly speaking not uniform. The assertion in fs_generator makes sure that immediates have the expected stride as consistency check. Reviewed-by: Samuel Iglesias Gonsálvez <[email protected]>
* i965/vec4: Fix liveness analysis with BRW_OPCODE_SELIago Toral Quiroga2015-07-211-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | We only consider a vgrf defined by a given block if the block writes to it unconditionally. So far we have been checking this by testing that the instruction is not predicated, however, in the case of BRW_OPCODE_SEL, the predication is used to select the value to write, not to decide if the write is actually done. The consequence of this was increased life spans for affected vgrfs, which could lead to additional register pressure. Since NIR generates selects for conditional writes this was causing massive register pressure in a handful of piglit and dEQP tests that had a large number of select operations with the NIR-vec4 backend. Fixes the following piglit tests with the NIR-vec4 backend: spec/glsl-1.50/execution/variable-indexing/vs-output-array-vec4-index-wr-before-gs spec/glsl-1.50/execution/variable-indexing/gs-input-array-vec4-index-rd spec/glsl-1.50/execution/variable-indexing/vs-output-array-vec2-index-wr-before-gs spec/glsl-1.50/execution/variable-indexing/vs-output-array-vec3-index-wr-before-gs spec/glsl-1.50/execution/variable-indexing/vs-output-array-float-index-wr-before-gs Fixes 80 dEQP tests with the NIR-vec4 backend in the following category: dEQP-GLES3.functional.ubo.* Reviewed-by: Francisco Jerez <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* mesa: Rename _mesa_lookup_enum_by_nr() to _mesa_enum_to_string().Kenneth Graunke2015-07-2026-53/+53
| | | | | | | Generated by sed; no manual changes. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Brian Paul <[email protected]>
* i965/nir/fs: removed unneeded support for global variablesAlejandro Piñeiro2015-07-203-14/+4
| | | | | | | As functions are inlined, and nir_lower_global_vars_to_local gets run, all global variables are lowered to local variables. Reviewed-by: Kenneth Graunke <[email protected]>
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-12 23:05:49 +0000