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* i965/nir/vec4: Implement the dot product operationAntia Puentes2015-08-031-0/+15
| | | | | | | | | Adds NIR ALU operations: * nir_op_fdot2 * nir_op_fdot3 * nir_op_fdot4 Reviewed-by: Jason Ekstrand <[email protected]>
* i965/nir/vec4: Implement conditional selectAntia Puentes2015-08-031-0/+6
| | | | | | | Adds NIR ALU operations: * nir_op_bcsel Reviewed-by: Jason Ekstrand <[email protected]>
* i965/nir/vec4: Implement linear interpolationAntia Puentes2015-08-031-0/+5
| | | | | | | Adds NIR ALU operation: * nir_op_flrp Reviewed-by: Jason Ekstrand <[email protected]>
* i965/vec4: Return the emitted instruction in emit_lrp()Antia Puentes2015-08-032-6/+6
| | | | | | | Needed in the NIR backend to set the "saturate" value of the instruction. Reviewed-by: Jason Ekstrand <[email protected]>
* i965/nir/vec4: Implement floating-point fused multiply-addAntia Puentes2015-08-031-0/+9
| | | | | | | Adds NIR ALU operation: * nir_op_ffma Reviewed-by: Jason Ekstrand <[email protected]>
* i965/nir/vec4: Implement "shift" operationsAntia Puentes2015-08-031-0/+12
| | | | | | | | | Adds NIR ALU operations: * nir_op_ishl * nir_op_ishr * nir_op_ushr Reviewed-by: Jason Ekstrand <[email protected]>
* i965/nir/vec4: Implement the "sign" operationAntia Puentes2015-08-031-0/+33
| | | | | | | | | | | Follows the vec4_visitor IR implementation but sets the saturate value in addition. Adds NIR ALU operations: * nir_op_fsign * nir_op_isign Reviewed-by: Jason Ekstrand <[email protected]>
* i965/nir/vec4: Implement bit operationsAntia Puentes2015-08-031-0/+62
| | | | | | | | | | | | | | | | | | Same implementation than the IR case. Adds NIR ALU operations: * nir_op_bitfield_reverse * nir_op_bit_count * nir_op_ufind_msb * nir_op_ifind_msb * nir_op_find_lsb * nir_op_ubitfield_extract * nir_op_ibitfield_extract * nir_op_bfm * nir_op_bfi * nir_op_bitfield_insert Reviewed-by: Jason Ekstrand <[email protected]>
* i965/nir/vec4: Implement pack/unpack operationsAntia Puentes2015-08-031-0/+44
| | | | | | | | | | | | | | | | * Lowered floating-point pack and unpack operations are not valid in VS. * Pack and unpack 2x16 operations should be handled by lower_packing_builtins. * Adds NIR ALU operations: * nir_op_pack_half_2x16 * nir_op_unpack_half_2x16 * nir_op_unpack_unorm_4x8 * nir_op_unpack_snorm_4x8 * nir_op_pack_unorm_4x8 * nir_op_pack_snorm_4x8 Reviewed-by: Jason Ekstrand <[email protected]>
* i965/nir/vec4: "noise" ops should already be loweredAntia Puentes2015-08-031-0/+18
| | | | | | Marked them as unreachable. Reviewed-by: Jason Ekstrand <[email protected]>
* i965/nir/vec4: Implement "bool<->int,float" format conversionAntia Puentes2015-08-031-0/+19
| | | | | | | | | | | | Used the same implementation than the vec4_visitor NIR. Adds NIR ALU operations: * nir_op_b2i * nir_op_b2f * nir_op_f2b * nir_op_i2b Reviewed-by: Jason Ekstrand <[email protected]>
* i965/nir/vec4: Implement logical operatorsAntia Puentes2015-08-031-0/+16
| | | | | | | | | | Adds NIR ALU operations: * nir_op_inot * nir_op_ixor * nir_op_ior * nir_op_iand Reviewed-by: Jason Ekstrand <[email protected]>
* i965/nir/vec4: Implement non-equality ops on vectorsAntia Puentes2015-08-031-0/+34
| | | | | | | | | | | | Adds NIR ALU operations: * nir_op_bany_fnequal2 * nir_op_bany_inequal2 * nir_op_bany_fnequal3 * nir_op_bany_inequal3 * nir_op_bany_fnequal4 * nir_op_bany_inequal4 Reviewed-by: Jason Ekstrand <[email protected]>
* i965/nir/vec4: Implement equality ops on vectorsAntia Puentes2015-08-031-0/+33
| | | | | | | | | | | | Adds NIR ALU operations: * nir_op_ball_fequal2 * nir_op_ball_iequal2 * nir_op_ball_fequal3 * nir_op_ball_iequal3 * nir_op_ball_fequal4 * nir_op_ball_iequal4 Reviewed-by: Jason Ekstrand <[email protected]>
* i965/nir/vec4: Implement non-vector comparison opsAntia Puentes2015-08-031-0/+14
| | | | | | | | | | | | | | | | Adds NIR ALU operations: * nir_op_flt * nir_op_ilt * nir_op_ult * nir_op_fge * nir_op_ige * nir_op_uge * nir_op_feq * nir_op_ieq * nir_op_fne * nir_op_ine Reviewed-by: Jason Ekstrand <[email protected]>
* i965/nir: Add utility method for comparisonsAntia Puentes2015-08-031-0/+39
| | | | | | | | | This method returns the brw_conditional_mod value used when emitting comparative ALU operations. It could be moved to brw_nir in the future to reuse it in fs_nir backend. Reviewed-by: Jason Ekstrand <[email protected]>
* i965/nir/vec4: Derivatives are not allowed in VSAntia Puentes2015-08-031-0/+8
| | | | Reviewed-by: Jason Ekstrand <[email protected]>
* i965/nir/vec4: Implement min/max operationsAntia Puentes2015-08-031-0/+14
| | | | | | | | | | | | Adds NIR ALU operations: * nir_op_fmin * nir_op_imin * nir_op_umin * nir_op_fmax * nir_op_imax * nir_op_umax Reviewed-by: Jason Ekstrand <[email protected]>
* i965/vec4: Return the emitted instruction in emit_minmax()Antia Puentes2015-08-032-3/+5
| | | | | | | Needed in the NIR backend to set the "saturate" value of the instruction. Reviewed-by: Jason Ekstrand <[email protected]>
* i965/nir/vec4: Implement various rounding functionsAntia Puentes2015-08-031-0/+35
| | | | | | | | | | | Adds NIR ALU operations: * nir_op_ftrunc * nir_op_fceil * nir_op_ffloor * nir_op_ffrac * nir_op_fround_even Reviewed-by: Jason Ekstrand <[email protected]>
* i965/nir/vec4: Implement carry/borrow for addition/subtractionAntia Puentes2015-08-031-0/+16
| | | | | | | | Adds NIR ALU operations: * nir_op_uadd_carry * nir_op_usub_borrow Reviewed-by: Jason Ekstrand <[email protected]>
* i965/nir/vec4: Implement more math operationsAntia Puentes2015-08-031-0/+52
| | | | | | | | | | | | | | | | | | | | Adds NIR ALU operations: * nir_op_frcp * nir_op_fexp2 * nir_op_flog2 * nir_op_fexp * nir_op_flog * nir_op_fsin * nir_op_fcos * nir_op_idiv * nir_op_udiv * nir_op_umod * nir_op_ldexp * nir_op_fsqrt * nir_op_frsq * nir_op_fpow Reviewed-by: Jason Ekstrand <[email protected]>
* i965/vec4: Return the last emitted instruction in emit_math()Antia Puentes2015-08-032-4/+7
| | | | | | | Needed in the NIR backend to set the "saturate" value of the instruction. Reviewed-by: Jason Ekstrand <[email protected]>
* i965/nir/vec4: Implement multiplicationAntia Puentes2015-08-031-0/+44
| | | | | | | | | | | | | Implementation based on the vec4_visitor IR implementation for the operations ir_binop_mul and ir_binop_imul_high. Adds NIR ALU operations: * nir_op_fmul * nir_op_imul * nir_op_imul_high * nir_op_umul_high Reviewed-by: Jason Ekstrand <[email protected]>
* i965/nir/vec4: Implement the addition operationAntia Puentes2015-08-031-0/+7
| | | | | | | | Adds NIR ALU operations: * nir_op_fadd * nir_op_iadd Reviewed-by: Jason Ekstrand <[email protected]>
* i965/nir/vec4: Implement int<->float format conversion opsAntia Puentes2015-08-031-0/+11
| | | | | | | | | | Adds NIR ALU operations: * nir_op_f2i * nir_op_f2u * nir_op_i2f * nir_op_u2f Reviewed-by: Jason Ekstrand <[email protected]>
* i965/nir/vec4: Lower "vecN" instructions and mark them unreachableAntia Puentes2015-08-032-0/+10
| | | | | | This enables NIR pass "lower_vec_to_movs" on shaders that work on vec4. Reviewed-by: Jason Ekstrand <[email protected]>
* i965/nir/vec4: Implement single-element "mov" operationsAntia Puentes2015-08-031-0/+13
| | | | | | | | Adds NIR ALU operations: * nir_op_imov * nir_op_fmov Reviewed-by: Jason Ekstrand <[email protected]>
* i965/nir: Disable alu_to_scalar pass on non-scalar shadersAlejandro Piñeiro2015-08-031-6/+10
| | | | | | | Disables nir_lower_alu_to_scalar when the shader stage being processed work on vec4 vectors, like the upcoming NIR->vec4 backend. Reviewed-by: Jason Ekstrand <[email protected]>
* i965/nir/vec4: Prepare source and destination registers for ALU operationsAntia Puentes2015-08-031-1/+18
| | | | | | | This patch resolves and initializes the destination and the source registers that are common to most ALU operations. Reviewed-by: Jason Ekstrand <[email protected]>
* i965/nir/vec4: Implement loading values from an UBOAntia Puentes2015-08-031-2/+59
| | | | | | | | | | | | | | | Based on the vec4_visitor IR implementation for the ir_binop_load_ubo operation. Notice that unlike the vec4_visitor IR, adding the !=0 comparison for UBO bools is not needed here because that comparison is already added by the nir_visitor when processing the ir_binop_load_ubo (in UBOs "true" is any value different from zero, but for us is ~0). Adds NIR instrinsics: * nir_intrinsic_load_ubo_indirect * nir_intrinsic_load_ubo Reviewed-by: Jason Ekstrand <[email protected]>
* i965/nir/vec4: Implement atomic counter intrinsics (read, inc and dec)Alejandro Piñeiro2015-08-031-2/+25
| | | | | | The implementation is based on its fs_nir counterpart. Reviewed-by: Jason Ekstrand <[email protected]>
* i965/nir/vec4: Implement load_uniform intrinsicIago Toral Quiroga2015-08-031-2/+24
| | | | | | | | | For the indirect case we need to take the index delivered by NIR and compute the parent uniform that we are accessing (the one that we uploaded to a surface) and the constant offset into that surface. Reviewed-by: Jason Ekstrand <[email protected]>
* i965/nir/vec4: Implement intrinsics that load system valuesAlejandro Piñeiro2015-08-031-6/+21
| | | | | | | | | | | | | These include: nir_intrinsic_load_vertex_id_zero_base nir_intrinsic_load_base_vertex nir_intrinsic_load_instance_id The source register is fetched from the nir_system_values map initialized during nir_setup_system_values stage. Reviewed-by: Jason Ekstrand <[email protected]>
* i965/nir/vec4: Implement store_output intrinsicEduardo Lima Mitev2015-08-032-3/+19
| | | | | | | | | | | | | | This implementation is based on the current URB setup in vec4_visitor, which requires the output register to be stored in the output_reg array at variable's original shader location index. But since nir_lower_io() pass uses the value in var->data.driver_location, we need to put there var->data.location instead, prior to calling nir_lower_io(), so that we end up with the correct index in const_index[0]. The driver_location is not used at all, so this patch also disables the nir_assign_var_locations pass on non-scalar shaders. Reviewed-by: Jason Ekstrand <[email protected]>
* i965/vec4: Make sure that register types always match during emit_urb_slot()Eduardo Lima Mitev2015-08-031-5/+10
| | | | | | | | | | | | Instead of relying on backends (currently vec4_visitor and soon NIR-vec4) to store registers in output_reg with the correct type, this patch makes sure that the common code in emit_urb_slot() always emit MOVs from output registers using the same type on source and destination. Since the actual type is not important, only that they match, we default to float. Reviewed-by: Jason Ekstrand <[email protected]>
* i965/nir/vec4: Implement load_input intrinsicEduardo Lima Mitev2015-08-031-2/+20
| | | | | | | The source register is fetched from the nir_inputs map built during nir_setup_inputs stage. Reviewed-by: Jason Ekstrand <[email protected]>
* i965/nir/vec4: Implement loop statements (nir_cf_node_loop)Eduardo Lima Mitev2015-08-031-1/+5
| | | | | | This is taken as-is from fs_nir. Reviewed-by: Jason Ekstrand <[email protected]>
* i965/nir/vec4: Implement conditional statements (nir_cf_node_if)Iago Toral Quiroga2015-08-031-1/+15
| | | | | | | | The same we do in the FS NIR backend, only that here we need to consider the number of components in the condition and adjust the swizzle accordingly. Reviewed-by: Jason Ekstrand <[email protected]>
* i965/nir/vec4: Add get_nir_dst() and get_nir_src() methodsEduardo Lima Mitev2015-08-032-0/+83
| | | | | | | | | | | | | These methods are essential for the implementation of the NIR->vec4 pass. They work similar to their fs_nir counter-parts. When processing instructions, these methods are invoked to resolve the brw registers (source or destination) corresponding to the NIR sources or destination. It uses the map of NIR register index to brw register for all registers locally allocated in a block. Signed-off-by: Samuel Iglesias Gonsalvez <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* i965/nir: Move brw_type_for_nir_type() to brw_nir to allow reuseEduardo Lima Mitev2015-08-033-18/+21
| | | | | | Upcoming NIR->vec4 pass can benefit from this method, so lets move it up. Reviewed-by: Jason Ekstrand <[email protected]>
* i965/nir/vec4: Implement load_const intrinsicEduardo Lima Mitev2015-08-033-2/+20
| | | | | | | | | Similar to fs_nir backend, a nir_local_values map will be filled with newly allocated registers as the load_const instrinsic instructions are processed. Later, get_nir_src() will fetch the registers from this map for sources that are ssa. Reviewed-by: Jason Ekstrand <[email protected]>
* i965/vec4: Add auxiliary func to build a writemask from a component sizeEduardo Lima Mitev2015-08-031-0/+6
| | | | | | | New method brw_writemask_for_size() will return a writemask with the first 'size' components activated. Reviewed-by: Jason Ekstrand <[email protected]>
* i965/nir: Dot not assign direct uniform locations first for vec4-based shadersIago Toral Quiroga2015-08-031-4/+10
| | | | | | | | | | In the vec4 backend we want uniform locations to be assigned consecutively since that way the offsets produced by nir_lower_io are exactly what we need to implement nir_intrinsic_load_uniform. Otherwise we would need a mapping to match the output of nir_lower_io to the actual uniform registers we need to use. Reviewed-by: Jason Ekstrand <[email protected]>
* nir/nir_lower_io: Add vec4 supportIago Toral Quiroga2015-08-031-6/+8
| | | | | | | | | | The current implementation operates in scalar mode only, so add a vec4 mode where types are padded to vec4 sizes. This will be useful in the i965 driver for its vec4 nir backend (and possbly other drivers that have vec4-based shaders). Reviewed-by: Jason Ekstrand <[email protected]>
* i965/nir: Pass a is_scalar boolean to brw_create_nir()Eduardo Lima Mitev2015-08-035-7/+12
| | | | | | | | | | | | The upcoming introduction of NIR->vec4 pass will require that some NIR lowering passes are enabled/disabled depending on the type of shader (scalar vs. vector). With this patch we pass a 'is_scalar' variable to the process of constructing the NIR, to let an external context decide how the shader should be handled. Reviewed-by: Jason Ekstrand <[email protected]>
* i965/nir/vec4: Add shader function implementationEduardo Lima Mitev2015-08-032-1/+11
| | | | | | | It basically allocates registers local to a function in a nir_locals map, then emits all its control-flow blocks. Reviewed-by: Jason Ekstrand <[email protected]>
* i965/nir/vec4: Add setup for system valuesAlejandro Piñeiro2015-08-032-1/+50
| | | | | | | | | Similar to other variable setups, system values will initialize the corresponding register inside a 'nir_system_values' map, which will then be queried later when processing the different system value intrinsics for the appropriate register. Reviewed-by: Jason Ekstrand <[email protected]>
* i965/vec4: Redefine make_reg_for_system_value() to allow reuse in NIR->vec4 passAlejandro Piñeiro2015-08-038-11/+19
| | | | | | | | | | | The new virtual method is more flexible, it has a signature: dst_reg *make_reg_for_system_value(int location, const glsl_type *type); v2 (Jason Ekstrand): Use the new version in unit tests so make check passes again Reviewed-by: Jason Ekstrand <[email protected]>
* i965/nir/vec4: Add setup of uniform variablesIago Toral Quiroga2015-08-032-3/+97
| | | | Reviewed-by: Jason Ekstrand <[email protected]>
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