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* radeon: oops remove debugging left on in previous patchDave Airlie2009-09-161-2/+0
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* radeon: use txformat to decide to emit rect tex state.Dave Airlie2009-09-161-4/+8
| | | | This is more logical, and fixes a TFP issue.
* mesa: move generate mipmap callsBrian Paul2009-09-157-122/+49
| | | | | | Per the suggestion in the Intel driver, move the calls to ctx->Driver.GenerateMipmap() into core Mesa so that drivers don't have to worry about it.
* radeon: don't build non-r600 span code on r600Alex Deucher2009-09-151-1/+5
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* r600: minor span cleanupsAlex Deucher2009-09-151-4/+3
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* mesa: remove incorrect texture state checkBrian Paul2009-09-151-6/+0
| | | | | | | Fixes incorrectly textured bitmap text in engine demo. It's incorrect to test the texture enable bits here since they may have been changed by disabling the shader above. Optimization is still possible but will have to be reexamined.
* Merge branch 'mesa_7_6_branch'Brian Paul2009-09-151-1/+1
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| * radeon: Remove structure allocation from iterator variable.Pauli Nieminen2009-09-111-1/+1
| | | | | | | | | | dma_bo varaible is only used for iterating so allocating memory for it only causes memory leaks.
* | r600: support position_invariant programsAndre Maasikas2009-09-151-12/+18
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* | r600: add span support for 1D tilesAlex Deucher2009-09-143-1/+223
| | | | | | | | | | | | | | | | | | | | | | 1D tile span support for depth/stencil/color/textures Z and stencil buffers are always tiled, so this fixes sw access to Z and stencil buffers. color and textures are currently linear, but this adds span support when we implement 1D tiling. This fixes the text in progs/demos/engine and progs/tests/z*
* | r600: fix warningAlex Deucher2009-09-141-0/+1
| | | | | | | | Noticed by rnoland on IRC.
* | intel: minor code clean-upsBrian Paul2009-09-141-11/+8
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* | intel: fix renderbuffer map/unmap regressionBrian Paul2009-09-141-14/+14
| | | | | | | | | | | | Commit 36dd53a3cded9d003ec418732b7fc93c1476aa9b caused a few regressions because the glReadBuffer() buffer wasn't getting mapped when GL_READ_BUFFER != GL_DRAW_BUFFER.
* | intel: remove unneeded driver function assignmentsBrian Paul2009-09-141-5/+0
| | | | | | | | | | These default swrast functions are already installed by _mesa_init_driver_functions().
* | i965: Move OPCODE_DDX/DDY to brw_wm_emit.c and make it actually work.Eric Anholt2009-09-115-102/+126
| | | | | | | | | | | | | | Previously, it was trying to mess around with the varying's WM setup data to produce a result. Along with not actually working when passed a varying, this wouldn't work if you did dFd[xy]() on a temporary. Instead, just calculate the derivative using the neighbors in the subspan.
* | r600: fix texcoords from constantsAndre Maasikas2009-09-111-40/+52
| | | | | | | | with some minor updates from Richard.
* | Revert "r600: support tex coords from constants"Alex Deucher2009-09-111-17/+45
| | | | | | | | | | | | This reverts commit 4099bb76148007f9ccb6c86838b2bf37ea42de56. Tex coord src has to be a GPR.
* | r600: support tex coords from constantsAlex Deucher2009-09-111-45/+17
| | | | | | | | Fixes neverball among other things.
* | r600: enable caching of vertex programsAndre Maasikas2009-09-116-62/+110
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* | i965: Enable loops in the VS.Eric Anholt2009-09-101-15/+38
| | | | | | | | | | | | Passes piglit glsl-vs-loop testcase. Bug #20171
* | mesa: nicer vertex setupBrian Paul2009-09-101-128/+138
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* | Merge branch 'mesa_7_6_branch'Brian Paul2009-09-105-44/+55
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| * intel: disable intel_stencil_drawpixels() for nowBrian Paul2009-09-101-0/+16
| | | | | | | | It doesn't work reliably even when all the prerequisite checks are made.
| * Fix merge failIan Romanick2009-09-101-13/+0
| | | | | | | | | | | | | | | | | | One of the conflicst from this merge was missed: commit 0c309bb494b6ee1c403442d1207743f749f95b6e Merge: c6c44bf d27d659 Author: Brian Paul <[email protected]> Date: Wed Sep 9 08:33:39 2009 -0600
| * mesa: need to set all stencil bits to 0 before setting the 1 bitsBrian Paul2009-09-101-0/+9
| | | | | | | | Plus, check for pixel transfer stencil index/offset.
| * Merge branch 'mesa_7_5_branch' into mesa_7_6_branchIan Romanick2009-09-102-1/+6
| |\ | | | | | | | | | | | | Conflicts: src/mesa/drivers/dri/intel/intel_context.c
| | * intel: add B43 chipset supportZhenyu Wang2009-09-102-1/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Zhenyu Wang <[email protected]> Signed-off-by: Ian Romanick <[email protected]> Hopefully this will be one of the last cherry-picks. (cherry picked from commit ca246dd186f9590f6d67038832faceb522138c20)
| * | i965: Fix relocation delta for WM surfaces.Eric Anholt2009-09-101-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | This was a regression in 0f328c90dbc893e15005f2ab441d309c1c176245. Bug #23688 Bug #23254 (cherry picked from commit 5604b27b9326ac542069a49ed9650c4b0d3e939a)
| * | radeon: Change debugging code to use macros instead of inline functions.Pauli Nieminen2009-09-102-43/+27
| | | | | | | | | | | | | | | | | | Variadic functions can't be inlined which makes debugging to have quite large function overead. Only aleternative method is to use variadic macros which are inlined so compiler can optimize debugging to minimize overhead.
| * | radeon: Add more verbose error message for failed command buffer.Pauli Nieminen2009-09-091-1/+3
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* | | intel: Don't forget to map the depth read buffer in spans.Eric Anholt2009-09-101-22/+28
| | | | | | | | | | | | This broke BlitFramebufferEXT(GL_DEPTH_BUFFER_BIT).
* | | r300: enable rb3d_discard_src_pixel_lte_threshold for more chips on dri2Alex Deucher2009-09-101-5/+1
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* | | r300: add full support for two sided stencil on r5xx for dri2Alex Deucher2009-09-104-4/+46
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* | | mesa: fix cut&paste typosMathias Frohlich2009-09-101-4/+4
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* | | i965: Fix relocation delta for WM surfaces.Eric Anholt2009-09-091-1/+1
| | | | | | | | | | | | | | | | | | | | | This was a regression in 0f328c90dbc893e15005f2ab441d309c1c176245. Bug #23688 Bug #23254
* | | i965: fix an overlooked merge conflictBrian Paul2009-09-091-13/+0
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* | | r600: check if textures are actually enabled before submissionAlex Deucher2009-09-092-56/+64
| | | | | | | | | | | | noticed by taiu on IRC.
* | | Merge branch 'mesa_7_6_branch'Brian Paul2009-09-096-2/+28
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| * | Merge branch 'mesa_7_5_branch' into mesa_7_6_branchBrian Paul2009-09-095-1/+24
| |\| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Conflicts: Makefile configs/default progs/glsl/Makefile src/gallium/auxiliary/util/u_simple_shaders.c src/gallium/state_trackers/glx/xlib/xm_api.c src/mesa/drivers/dri/i965/brw_draw_upload.c src/mesa/drivers/dri/i965/brw_vs_emit.c src/mesa/drivers/dri/intel/intel_context.h src/mesa/drivers/dri/intel/intel_pixel.c src/mesa/drivers/dri/intel/intel_pixel_read.c src/mesa/main/texenvprogram.c src/mesa/main/version.h
| | * i965: fix incorrect test for vertex position attributeBrian Paul2009-09-083-1/+4
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| | * i965: Fix warnings in intel_pixel_read.c.Eric Anholt2009-09-041-0/+4
| | | | | | | | | | | | (cherry picked from commit c80ce5ac90b1e0ac7a72cd41c314aa2000bfecf5)
| | * intel: Also get the DRI2 front buffer when doing front buffer reading.Eric Anholt2009-09-044-1/+29
| | | | | | | | | | | | (cherry picked from commit df70d3049a396af3601d2a1747770635a74120bb)
| | * intel: Update Mesa state before span setup in glReadPixels.Eric Anholt2009-09-043-3/+13
| | | | | | | | | | | | | | | | | | We could have mapped the wrong set of draw buffers. Noticed while looking into a DRI2 glean ReadPixels issue. (cherry picked from commit afc981ee46791838f3cb83e11eb33938aa3efc83)
| | * intel: Move intel_pixel_read.c to shared for use with i965.Eric Anholt2009-09-042-306/+307
| | | | | | | | | | | | (cherry picked from commit dcfe0d66bfff9a55741aee298b7ffb051a48f0d3)
| | * i965: Add missing state dependency of sf_unit on _NEW_BUFFERS.Eric Anholt2009-09-041-2/+4
| | | | | | | | | | | | (cherry picked from commit 99174e7630676307f618c252755a20ba61ad9158)
| | * intel: Align cubemap texture height to its padding requirements.Eric Anholt2009-09-041-0/+10
| | | | | | | | | | | | | | | (cherry picked from commit a70e1315846cd5e8d6f2b622821ff8262fe7179d) (cherry picked from commit 29e51c3872531366570d032147abad50f8a3c1af)
| | * intel: Align untiled region height to 2 according to 965 docs.Eric Anholt2009-09-041-0/+7
| | | | | | | | | | | | | | | | | | This may or may not be required pre-965, but it doesn't seem unlikely, and I'd rather be safe. (cherry picked from commit b053474378633249be0e9f24010650ffb816229a)
| | * i965: Fix source depth reg setting for FSes reading and writing to depth.Eric Anholt2009-09-043-1/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | For some IZ setups, we'd forget to account for the source depth register being present, so we'd both read the wrong reg, and write output depth to the wrong reg. Bug #22603. (cherry picked from commit f44916414ecd2b888c8a680d56b7467ccdff6886)
| | * i965: Respect CondSwizzle in OPCODE_IF.Eric Anholt2009-09-041-1/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | Fixes piglit glsl-vs-if-bool and progs/glsl/twoside, and will likely be useful for the looping code. Bug #18992 (cherry picked from commit 78c022acd0b37bf8b32f04313d76255255e769c1) (cherry picked from commit 63d7a2f53fb38e170f4e55f2b599e918edf2c512)
| | * i965: asst clean-ups, etc in brw_vs_emit()Brian Paul2009-09-041-11/+10
| | | | | | | | | | | | (cherry picked from commit fd7d764514c540987549c3ea88a2d669b0f0ea58)
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