aboutsummaryrefslogtreecommitdiffstats
path: root/src/mesa/drivers
Commit message (Collapse)AuthorAgeFilesLines
* i965/iris/perf: factor out frequency register captureLionel Landwerlin2019-12-181-22/+18
| | | | | | | Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Mark Janes <[email protected]> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3113> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3113>
* i965: expose MESA_FORMAT_B8G8R8X8_SRGB visualTapani Pälli2019-12-171-7/+14
| | | | | | | | | | | | | | | | | | Patch adds BGRX sRGB visuals, required format translation information to the __DRI_IMAGE_FOURCC_SXRGB8888 format and makes all BGRX visuals sRGB capable just like is done with BGRA. squashed patches from Yevhenii Kolesnikov: dri: Add __DRI_IMAGE_FOURCC_SXRGB8888 conversion i965: force visuals without alpha bits to use sRGB Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/1501 Cc: <[email protected]> Signed-off-by: Tapani Pälli <[email protected]> Signed-off-by: Yevhenii Kolesnikov <[email protected]> Reviewed-by: Lionel Landwerlin <[email protected]> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3077> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3077>
* dri: add __DRI_IMAGE_FORMAT_SXRGB8Tapani Pälli2019-12-171-0/+4
| | | | | | | | | Add format definition and required plumbing to create images. Cc: <[email protected]> Signed-off-by: Tapani Pälli <[email protected]> Reviewed-by: Lionel Landwerlin <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3077>
* i965/iris: perf-queries: don't invalidate/flush 3d pipelineLionel Landwerlin2019-12-131-1/+9
| | | | | | | | | | | | | | | | | | | Our current implementation of performance queries is fairly harsh because it completely flushes and invalidates the 3d pipeline caches at the beginning and end of each query. An argument can be made that this is how performance should be measured but it probably doesn't reflect what the application is actually doing and the actual cost of draw calls. A more appropriate approach is to just stall the pipeline at scoreboard, so that we measure the effect of a draw call without having the pipeline in a completely pristine state for every draw call. v2: Use end of pipe PIPE_CONTROL instruction for Iris (Ken) Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* st/glsl_to_nir: use nir based program resource list builderTimothy Arceri2019-12-131-2/+2
| | | | | | | | | | | | | | | | | Here we use the NIR based builder to add everything to the resource list execpt for SSO packed varyings. Since the details of those varyings get lost during packing we leave the special handing to the GLSL IR pass for now. In order to do this we add some bools to the build resource list functions. Using the NIR based resource list builder gets us a step closer to using a native NIR based linker. It should also be faster than the GLSL IR builder, one because the NIR optimisations should mean we add less entries due to better optimisations, and two because nir gives us better lists to work with and we don't need to walk the entire IR to find the resources. Ack-by: Alejandro Piñeiro <[email protected]>
* glsl: move nir_remap_dual_slot_attributes() call out of glsl_to_nir()Timothy Arceri2019-12-131-0/+8
| | | | | | | | | In order to be able to implement a NIR based glsl linker we need to build the program resource list with NIR. This change delays the remaping so that a later commit can call the NIR based resource list builder. Reviewed-by: Alejandro Piñeiro <[email protected]>
* i965: Enable GL_EXT_gpu_shader4 on Gen6+Jason Ekstrand2019-12-121-0/+1
| | | | | | | It's already enabled for all gallium drivers that support GLSL 1.40 or above and we already support everything in our compiler on SNB+ Reviewed-by: Ian Romanick <[email protected]>
* intel/decoder: Make get_state_size take a full 64-bit address and a baseKenneth Graunke2019-12-101-3/+4
| | | | | | | | | | | | i965 wants to use an offset from a base because everything is in a single buffer whose address may be relocated, and all base addresses are set to the start of that buffer. iris wants to use a full 64-bit address, because state lives in separate buffers which may be in the shader, surface, and dynamic memory zones, where addresses grow downward from the top of a 4GB zone, So it's very possible for a 32-bit offset to exist relative to multiple bases, leading to the wrong state size.
* blorp: Pass the VB size to the VF cache workaroundJason Ekstrand2019-12-051-0/+1
| | | | | Reviewed-by: Ivan Briano <[email protected]> Reviewed-by: Lionel Landwerlin <[email protected]>
* mesa: Silence unused parameter warningIan Romanick2019-12-046-10/+10
| | | | | | | | | | | | | Unused since e4da8b9c331 ("mesa/compiler: rework tear down of builtin/types"). src/mesa/main/context.c: In function ‘_mesa_free_context_data’: src/mesa/main/context.c:1321:54: warning: unused parameter ‘destroy_compiler_types’ [-Wunused-parameter] 1321 | _mesa_free_context_data(struct gl_context *ctx, bool destroy_compiler_types) | ^ Reviewed-by: Pierre-Eric Pelloux-Prayer <[email protected]> Reviewed-by: Eric Engestrom <[email protected]>
* i965: update Makefile.sources for perf changesJonathan Gray2019-11-291-2/+0
| | | | | | | | | | | | | | brw_performance_query_metrics.h was removed in 134e750e16bfc53480e0bba6f0ae3e1d2a7fb87c and brw_performance_query.h was removed in 8ae6667992ccca41d08884d863b8aeb22a4c4e65 remove reference to these files from Makefile.sources Signed-off-by: Jonathan Gray <[email protected]> Fixes: 134e750e16bfc53480e0 ("i965: extract performance query metrics") Fixes: 8ae6667992ccca41d088 ("intel/perf: move query_object into perf") Reviewed-by: Eric Engestrom <[email protected]>
* driconf, glsl: Add a vs_position_always_invariant optionKenneth Graunke2019-11-271-0/+3
| | | | | | | | | | | | | | | | | | | | Many applications use multi-pass rendering and require their vertex shader position to be computed the same way each time. Optimizations may consider, say, fusing a multiply-add based on global usage of an expression in a shader. But a second shader with the same expression may have different code, causing that optimization to make the other choice the second time around. The correct solution is for applications to mark their VS outputs 'invariant', indicating they need multiple shaders to compute that output in the same manner. However, most applications fail to do so. So, we add a new driconf option - vs_position_always_invariant - which forces the gl_Position output in vertex shaders to be marked invariant. Fixes: 7025dbe794b ("nir: Skip emitting no-op movs from the builder.") Reviewed-by: Eric Anholt <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* i965: Ensure that all 2101010 image imports can pass framebuffer completeness.Miguel Casas-Sanchez2019-11-191-2/+6
| | | | | | | | | | | Chrome OS would like to import and render to any supported format that has a corresponding display plane format, and this prevents throwing framebuffer incomplete for FBOs using these textures. See: crbug.com/949260 Reviewed-by: Tapani Pälli <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* Call shmget() with permission 0600 instead of 0777Brian Paul2019-11-181-1/+2
| | | | | | | | | | | | | | A security advisory (TALOS-2019-0857/CVE-2019-5068) found that creating shared memory regions with permission mode 0777 could allow any user to access that memory. Several Mesa drivers use shared- memory XImages to implement back buffers for improved performance. This path changes the shmget() calls to use 0600 (user r/w). Tested with legacy Xlib driver and llvmpipe. Cc: [email protected] Reviewed-by: Kristian H. Kristensen <[email protected]>
* intel/compiler: Add a flag to avoid compacting push constantsJason Ekstrand2019-11-181-0/+1
| | | | | | | In vec4, we can just not run the pass. In fs, things are a bit more deeply intertwined. Reviewed-by: Lionel Landwerlin <[email protected]>
* i965: Unify CC_STATE and BLEND_STATE atoms on Haswell as a workaroundDanylo Piliaiev2019-11-181-2/+35
| | | | | | | | | | | | | | | | | | | Re-emitting 3DSTATE_CC_STATE_POINTERS after emitting 3DSTATE_BLEND_STATE_POINTERS fixes the shadow flickering in SuperTuxCart and Tropico 6 which was seen only on Haswell. The reason for this is unknown and fix was found empirically. The closest mention in PRM is that it should improve performance. From the HSW PRM, volume 2b, page 823 (3DSTATE_BLEND_STATE_POINTERS): "When the BLEND_STATE pointer changes but not the CC_STATE pointer, driver needs to force a CC_STATE pointer change to improve blend performance in pixel backend." Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/1834 Fixes: eca4a654 ("i965: Disable dual source blending when shader doesn't support it on gen8+") Cc: <[email protected]> Signed-off-by: Danylo Piliaiev <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965/program_cache: Lift restriction on shader key sizeDanylo Piliaiev2019-11-121-12/+4
| | | | | | | | This will allow usage of packed structs which may have size not divisible by 4. Signed-off-by: Danylo Piliaiev <[email protected]> Reviewed-by: Lionel Landwerlin <[email protected]>
* Meson: Remove lib prefix from graw and osmesa when building with Mingw.Prodea Alexandru-Liviu2019-11-071-0/+2
| | | | | | | | | | | Also remove version sufix from osmesa swrast on Windows. v2: Make sure we don't remove lib prefix on *nix platforms. Signed-off-by: Prodea Alexandru-Liviu <[email protected]> Reviewed-by: Eric Engestrom <[email protected]> Cc: "19.3" <[email protected]>
* mesa: Prepare for the MESA_FORMAT_* enum to be sparse.Eric Anholt2019-11-071-0/+2
| | | | | | | | | To redefine MESA_FORMAT in terms of PIPE_FORMAT enums, we need to fix places where we iterated up to MESA_FORMAT_COUNT. I use _mesa_get_format_name(f) == NULL as the signal that it's not an enum value with a MESA_FORMAT. Reviewed-by: Marek Olšák <[email protected]>
* util: rename PIPE_ARCH_*_ENDIAN to UTIL_ARCH_*_ENDIANDylan Baker2019-11-057-14/+14
| | | | | | | | | | | As requested by Tim. This was generated with: grep 'PIPE_ARCH_.*_ENDIAN' -rIl | xargs sed -ie 's@PIPE_ARCH_\(.*\)_ENDIAN@UTIL_ARCH_\1_ENDIAN@'g v2: - add this patch Reviewed-by: Eric Engestrom <[email protected]>
* util/u_endian: set PIPE_ARCH_*_ENDIAN to 1Dylan Baker2019-11-057-14/+14
| | | | | | | | | | | | This will allow it to be used as a drop in replacement for _mesa_little_endian in a number of cases. v2: - Always define PIPE_ARCH_LITTLE_ENDIAN and PIPE_ARCH_BIG_ENDIAN, define the one that reflects the host system to 1 and the other to 0 - replace all uses of #ifdef, #ifndef, and #if defined() with #if and #if ! with PIPE_ARCH_*_ENDIAN Reviewed-by: Eric Engestrom <[email protected]>
* dri/osmesa: use preprocessor for selecting endian code pathsDylan Baker2019-11-051-6/+9
| | | | Reviewed-by: Eric Engestrom <[email protected]>
* r100: Use preprocessor to select big vs little endian pathsDylan Baker2019-11-053-46/+51
| | | | Reviewed-by: Eric Engestrom <[email protected]>
* r200: use preprocessor for big vs little endian checksDylan Baker2019-11-052-45/+38
| | | | | | | Instead of using a function at runtime we can just build the right code for the right platform. Reviewed-by: Eric Engestrom <[email protected]>
* radeon: replace xmlpool_options_h with idep_xmlconfig_headersEric Engestrom2019-10-311-2/+2
| | | | | Signed-off-by: Eric Engestrom <[email protected]> Acked-by: Dylan Baker <[email protected]>
* r200: replace xmlpool_options_h with idep_xmlconfig_headersEric Engestrom2019-10-311-2/+2
| | | | | Signed-off-by: Eric Engestrom <[email protected]> Acked-by: Dylan Baker <[email protected]>
* nouveau: replace xmlpool_options_h with idep_xmlconfig_headersEric Engestrom2019-10-311-2/+2
| | | | | Signed-off-by: Eric Engestrom <[email protected]> Acked-by: Dylan Baker <[email protected]>
* i915: replace xmlpool_options_h with idep_xmlconfig_headersEric Engestrom2019-10-311-2/+2
| | | | | Signed-off-by: Eric Engestrom <[email protected]> Acked-by: Dylan Baker <[email protected]>
* dri: replace xmlpool_options_h with idep_xmlconfig_headersEric Engestrom2019-10-311-2/+2
| | | | | Signed-off-by: Eric Engestrom <[email protected]> Acked-by: Dylan Baker <[email protected]>
* intel: Support HIZ_CCS in isl_surf_get_ccs_surfNanley Chery2019-10-282-8/+8
| | | | | | | Add an extra aux parameter which will be filled out with CCS if the first two isl_surf parameters fit the requirements for HiZ_CCS. Reviewed-by: Kenneth Graunke <[email protected]>
* i965/miptree: Avoid -Wswitch for the Gen12 aux modesNanley Chery2019-10-281-0/+3
| | | | | | | | Avoid the compiler warnings for the new enums that will be introduced in a future commit. Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Jordan Justen <[email protected]>
* util: rename list_empty() to list_is_empty()Timothy Arceri2019-10-281-1/+1
| | | | | | | This makes it clear that it's a boolean test and not an action (eg. "empty the list"). Reviewed-by: Eric Engestrom <[email protected]>
* i965: setup sized internalformat for MESA_FORMAT_R10G10B10A2_UNORMTapani Pälli2019-10-281-1/+9
| | | | | | | | | | | | | | | Commit d2b60e433e5 introduced restrictions (as per GLES spec) on the internal format. We need to setup a sized format for the texture image so framebuffers created with that are considered complete. This change fixes following Android CTS test in AHardwareBufferNativeTests category: SingleLayer_ColorTest_GpuColorOutputAndSampledImage_R10G10B10A2_UNORM Signed-off-by: Tapani Pälli <[email protected]> Fixes: d2b60e433e5 ("mesa/main: R10G10B10_(A2) formats are not color renderable in ES") Reviewed-by: Kenneth Graunke <[email protected]>
* intel/perf: move registers to their own headerLionel Landwerlin2019-10-232-1/+2
| | | | | | | Will conflict with the genxml RPSTAT register. Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Rafael Antognolli <[email protected]>
* mesa: Redefine the RG formats as array formats.Eric Anholt2019-10-203-10/+10
| | | | | | | | | This is the layout used in the GL API, and maps directly to PIPE formats with no endianness trickery. As with the LA change, this fixes big-endian fetching from texbos. Also cleans up some endian shenanigans in shader images. Reviewed-by: Marek Olšák <[email protected]>
* mesa: Replace MESA_FORMAT_L8A8/A8L8 UNORM/SNORM/SRGB with an array format.Eric Anholt2019-10-2010-27/+18
| | | | | | | | | | | | | | | | | The array format is what the GL API wants (fixing texbos on big-endian), and matches directly to gallium's corresponding array format. The only driver exposing A8L8 was radeon/r200 in big-endian, where the HW's underlying format was trying to read as array and we needed to flip things around to make our packed format come out right (note that while the radeon format tables had both AL and LA, ChooseTextureFormat would only pick one of them based on endianness). v2: Don't make r200/radeon use endian swaps. v3: Rebase on dropping the r200 _be/_le format table removal patch v4: reword commit message to explain why we can drop both formats from radeon. Reviewed-by: Marek Olšák <[email protected]> (v1)
* mesa: Replace the LA16_UNORM packed formats with one array format.Eric Anholt2019-10-202-2/+5
| | | | | | | | | | | The array format is what the GL API wants (and we made a mistake in the format returned for texbos on big-endian!), and it's exactly what the gallium-side PIPE_FORMAT_L16A16 is. The only downside is that dri_util tries to fall back to sampling RG16 using LA16, which doesn't have a match for big-endian any more. No HW drivers supported A16L16 anyway. Reviewed-by: Marek Olšák <[email protected]>
* radeon: Drop the unused first arg of OUT_BATCH_RELOC.Eric Anholt2019-10-209-24/+24
| | | | | | | This was a trap when trying to figure out how to fit data bits into the reloc. Reviewed-by: Marek Olšák <[email protected]>
* radeon: Fill in the TXOFFSET field containing the tile bits in our relocs.Eric Anholt2019-10-202-4/+5
| | | | | | | | | | The first arg to OUT_BATCH_RELOC is ignored, we actually wanted these in the third arg. They're always 0 so far, so it didn't matter. v2: Reword commit message that I don't end up using the tile bits, but keep the commit as a cleanup anyway. Reviewed-by: Marek Olšák <[email protected]> (v1)
* r100/r200: factor out txformat/txfilter setup from the TFP path.Eric Anholt2019-10-202-22/+10
| | | | | | | | | No matter what, we deref the texFormat from the table, except for a mistake in cpp=4 where we pulled a 0 out of the table either way. v2: Rebase on dropping r200 table deduplication patch. Reviewed-by: Marek Olšák <[email protected]> (v1)
* Revert "egl: Fixes transparency with EGL and X11."Hal Gentz2019-10-181-2/+0
| | | | This reverts commit 90a19074b4e1d4d8f8ababaade8170c05aeecffe.
* nir: support feeding state to nir_lower_clip_[vg]sErik Faye-Lund2019-10-171-1/+2
| | | | Reviewed-by: Marek Olšák <[email protected]>
* nir: support lowering clipdist to arraysErik Faye-Lund2019-10-171-1/+1
| | | | | | | | This allows us to make sure clipdist is emitted as a scalar array rather than two vec4s. This matches SPIR-V semantics, and will be useful for Zink. Reviewed-by: Marek Olšák <[email protected]>
* egl: Fixes transparency with EGL and X11.Hal Gentz2019-10-111-0/+2
| | | | | | | | | | | | | This commit does this by allowing both RGB and RGBA visuals to match with EGL configs. We also expose the `EGL_MESA_config_select_group` egl extension, which is similar to GLX's visual select group extension, to allow the RGBA visuals to get less priority. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=67676 Fixes: 049f343e8ac "egl: Allow 24-bit visuals for 32-bit RGBA8888 configs" Cc: [email protected] Reviewed-by: Adam Jackson <[email protected]> Signed-off-by: Hal Gentz <[email protected]>
* GL: drop symbols mangling supportEric Engestrom2019-10-102-8/+0
| | | | | | | | | | SCons and Meson have never supported that feature, and Autotools was deleted over 6 months ago and no-one complained yet, so it's pretty obvious nobody cares about it. Fixes: 95aefc94a941701616fd ("Delete autotools") Signed-off-by: Eric Engestrom <[email protected]> Acked-by: Dylan Baker <[email protected]>
* nir: add a strip parameter to nir_serializeMarek Olšák2019-10-101-1/+1
| | | | | | | so that drivers don't have to call nir_strip manually. Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Rob Clark <[email protected]>
* i965: Disable fast clears when running with INTEL_DEBUG=nofcCaio Marcelo de Oliveira Filho2019-10-092-0/+6
| | | | Reviewed-by: Rafael Antognolli <[email protected]>
* meta: leak of shader program when decompressing tex-imagesSergii Romantsov2019-10-091-0/+1
| | | | | | CC: Kenneth Graunke <[email protected]> Reviewed-by: Lionel Landwerlin <[email protected]> Signed-off-by: Sergii Romantsov <[email protected]>
* i965: Enable EXT_demote_to_helper_invocationCaio Marcelo de Oliveira Filho2019-09-301-0/+2
| | | | Reviewed-by: Kenneth Graunke <[email protected]>
* intel: Increase Gen11 compute shader scratch IDs to 64.Kenneth Graunke2019-09-231-1/+13
| | | | | | | | | | | | | | | | | | | | | | | From the MEDIA_VFE_STATE docs: "Starting with this configuration, the Maximum Number of Threads must be set to (#EU * 8) for GPGPU dispatches. Although there are only 7 threads per EU in the configuration, the FFTID is calculated as if there are 8 threads per EU, which in turn requires a larger amount of Scratch Space to be allocated by the driver." It's pretty clear that we need to increase this for scratch address calculations, because the FFTID has a certain bit-pattern. The quote above seems to indicate that we should increase the actual thread count programmed in MEDIA_VFE_STATE as well, but we think the intention is to only bump the scratch space. Fixes GPU hangs in Bioshock Infinite and Synmark's CSDof on Icelake 8x8. Fixes: 5ac804bd9ac ("intel: Add a preliminary device for Ice Lake") Reviewed-by: Matt Turner <[email protected]>
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-14 06:37:54 +0000