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* radeon: Use PRINTLIKE macro.Matt Turner2014-09-251-8/+1
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* mesa: Replace a priori knowledge of gcc attributes with configure tests.Matt Turner2014-09-251-6/+0
| | | | | | | | Note that I had to add support for testing the packed attribute to m4/ax_gcc_func_attribute.m4. Reviewed-by: Jason Ekstrand <[email protected]> [C bits] Reviewed-by: Ian Romanick <[email protected]>
* mesa: Replace a priori knowledge of gcc builtins with configure tests.Matt Turner2014-09-251-1/+1
| | | | | | | | | | | | | | Presumbly this will let clang and other compilers use the built-ins as well. Notice two changes specifically: - in _mesa_next_pow_two_64(), always use __builtin_clzll and add a static assertion that this is safe. - in macros.h, remove the clang-specific definition since it should be able to detect __builtin_unreachable in configure. Reviewed-by: Jason Ekstrand <[email protected]> [C bits] Reviewed-by: Ian Romanick <[email protected]>
* i965/compaction: Document instruction compaction capabilities.Matt Turner2014-09-251-0/+35
| | | | | | Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* i965: Emit ELSE/ENDIF JIP with type D on Gen 7.Matt Turner2014-09-251-2/+2
| | | | | | | | | | The spec says the type must be W (JIP is 16-bits after all), but we've been emitting it with a UD type all along and have experienced no adverse effects. Changing the type to D allows ELSE and ENDIF instructions to be compacted. Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* i965/compaction: Support compaction of control flow instructions.Matt Turner2014-09-251-14/+16
| | | | | | | | | | | | We're currently emitting compactable control flow instruction the wrong types, preventing their compaction. The next patch will fix this and actually enable compaction. On chips that cannot compact control flow instructions, attempts to find a match in the datatype table will fail. Acked-by: Kenneth Graunke <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* i965/compaction: Add support for G45.Matt Turner2014-09-251-15/+24
| | | | | Acked-by: Kenneth Graunke <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* i965: Add BRW_OPCODE_NENOP for G45.Matt Turner2014-09-252-2/+4
| | | | | Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* i965/compaction: Add support for Gen5.Matt Turner2014-09-251-5/+210
| | | | | | Acked-by: Kenneth Graunke <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> Acked-by: Ian Romanick <[email protected]>
* i965/compaction: Reduce size of compacted_counts[] array.Matt Turner2014-09-251-22/+37
| | | | | | | | | The array was previously indexed in units of brw_compact_inst (8-bytes), but before compaction all instructions are uncompacted, so every odd element was unused. Acked-by: Kenneth Graunke <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* i965/compaction: Use sizeof brw_inst/brw_compact_inst.Matt Turner2014-09-251-15/+17
| | | | | Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* i965/compaction: Increment offset in for loop.Matt Turner2014-09-251-3/+2
| | | | | | Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* i965/compaction: Make src_offset local to the for loop.Matt Turner2014-09-251-8/+4
| | | | | Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* i965/compaction: Remove unnecessary is-compacted? check.Matt Turner2014-09-251-2/+3
| | | | | | | | Used to pass over previously compacted instructions in this loop, but no longer. No point in checking. Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* i965/compaction: Don't set UIP on ELSE on Gen < 8.Matt Turner2014-09-251-1/+2
| | | | | Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* i965/compaction: Rework 3-src compaction logic.Matt Turner2014-09-251-5/+9
| | | | | | | | | It may be possible to create a contrived example in which a 3-src instruction would have been compacted on Gen < 8. I'd rather not discover it in the wild. Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* i965/sf: Disable instruction compaction.Matt Turner2014-09-251-1/+4
| | | | | | | | Currently a no-op, since instruction compaction isn't implemented for the generations that have a programmable strips-and-fans unit. Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* i965: Set JumpCount, not JIP, on ENDIF on Gen 6.Matt Turner2014-09-251-4/+7
| | | | | | | | Despite what the Sandybridge PRM says, ENDIF has Jump Count in <dst>, not JIP in <src1>. (The same mistake appears about WHILE as well). Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* i965/vec4: Call calculate_cfg() in test programs to avoid crashing.Matt Turner2014-09-242-0/+2
| | | | Reported-by: Mark Janes <[email protected]>
* mesa: Drop _mesa_getenv() wrapper.Matt Turner2014-09-242-14/+14
| | | | | | Reviewed-by: Ian Romanick <[email protected]> Reviewed-by: Jose Fonseca <[email protected]> Reviewed-by: Emil Velikov <[email protected]>
* mesa: Use realloc() instead of _mesa_realloc() and remove the latter.Matt Turner2014-09-241-2/+1
| | | | Reviewed-by: Ian Romanick <[email protected]>
* i965: Add and use functions to get next/prev blocks.Matt Turner2014-09-246-20/+73
| | | | Reviewed-by: Topi Pohjolainen <[email protected]>
* i965: Call insert and remove functions from exec_node directly.Matt Turner2014-09-243-14/+11
| | | | Reviewed-by: Topi Pohjolainen <[email protected]>
* i965: Make instruction lists local to the bblocks.Matt Turner2014-09-2412-92/+115
| | | | Reviewed-by: Topi Pohjolainen <[email protected]>
* i965/cfg: Add note about double-loop macros and break behavior.Matt Turner2014-09-241-0/+6
| | | | Reviewed-by: Topi Pohjolainen <[email protected]>
* i965: Replace initialization loops with memset().Matt Turner2014-09-242-15/+5
| | | | Reviewed-by: Topi Pohjolainen <[email protected]>
* i965/vec4: Don't iterate between blocks with inst->next/prev.Matt Turner2014-09-241-21/+9
| | | | | | The register coalescing portion of this patch hurts three shaders in Guacamelee by one instruction each, but examining the diff makes me believe that what we were generating was (perhaps harmlessly) incorrect.
* i965/fs: Don't iterate between blocks with inst->next/prev.Matt Turner2014-09-245-47/+34
| | | | | | When instruction lists are per-basic block, this won't work. Reviewed-by: Topi Pohjolainen <[email protected]>
* i965/cfg: Add macros to iterate through a block given a starting point.Matt Turner2014-09-241-0/+10
| | | | Reviewed-by: Topi Pohjolainen <[email protected]>
* i965/fs: Make count_to_loop_end() use basic blocks.Matt Turner2014-09-241-15/+16
| | | | | | | When the instructions aren't in a flat list, this wouldn't have worked. Also, this should be faster. Reviewed-by: Topi Pohjolainen <[email protected]>
* i965/vec4: Don't use instruction list after calculating the cfg.Matt Turner2014-09-245-14/+15
| | | | Reviewed-by: Topi Pohjolainen <[email protected]>
* i965/fs: Don't use instruction list after calculating the cfg.Matt Turner2014-09-243-22/+22
| | | | | | | | The only trick is changing a break into a return true in register coalescing, since the macro is actually a double loop, and break will do something different than you expect. (Wish I'd realized that earlier!) Reviewed-by: Topi Pohjolainen <[email protected]>
* i965: Remove now unneeded calls to calculate_cfg().Matt Turner2014-09-2412-39/+4
| | | | | | | Now that nothing invalidates the CFG, we can calculate_cfg() immediately after emit_fb_writes()/emit_thread_end() and never again. Reviewed-by: Topi Pohjolainen <[email protected]>
* i965: Remove cfg-invalidating parameter from invalidate_live_intervals.Matt Turner2014-09-2420-40/+34
| | | | | | Everything has been converted to preserve the CFG. Reviewed-by: Topi Pohjolainen <[email protected]>
* i965: Preserve the CFG in instruction scheduling.Matt Turner2014-09-241-32/+42
| | | | Reviewed-by: Topi Pohjolainen <[email protected]>
* i965/vec4: Preserve CFG in spill_reg().Matt Turner2014-09-244-38/+56
| | | | Reviewed-by: Topi Pohjolainen <[email protected]>
* i965/vec4: Preserve the CFG in a few more places.Matt Turner2014-09-241-7/+16
| | | | Reviewed-by: Topi Pohjolainen <[email protected]>
* i965/fs: Preserve the CFG in a few more places.Matt Turner2014-09-242-15/+21
| | | | Reviewed-by: Topi Pohjolainen <[email protected]>
* i965: Restructure debug flagsKristian Høgsberg2014-09-242-60/+60
| | | | | | | | | | | This cleans up the debug flags to be consistently indented, use bit shifting instead of hex-values and fixes a bug where the new DEBUG_NO8 flag used the same value as the DEBUG_VUE flag. This was hidden by the numbers not being aligned. Also removes gaps in the range where DEBUG_IOCTL (0x4) and DEBUG_REGION (0x400) used to be. Signed-off-by: Kristian Høgsberg <[email protected]> Reviewed-by: Chris Forbes <[email protected]>
* mesa: Move register_allocate.c to util.Eric Anholt2014-09-234-4/+4
| | | | | | | | | | | | | The r300 gallium driver is using it outside of the Mesa tree, and I wanted to do so for vc4 as well. Rather than make the multiple-definitions problem even more complicated, just move it to more-shared code. v2: Don't forget to delete the symlink in r300 (review by Matt). Delete more r300-helper references (review by Emil) Don't prefix util/ header inclusion with "util/" (review by Emil) Reviewed-by: Matt Turner <[email protected]> (v1) Reviewed-by: Emil Velikov <[email protected]> (v1)
* meta: Fix error paths in meta_copy_image.cJuha-Pekka Heikkila2014-09-231-0/+9
| | | | | | | | If _mesa_get_tex_image() return NULL there is already error set in context. Other error pats free allocated texture. Signed-off-by: Juha-Pekka Heikkila <[email protected]> Reviewed-by: Anuj Phogat <[email protected]>
* meta: Avoid null access on setup_glsl_msaa_blit_shader()Juha-Pekka Heikkila2014-09-231-11/+13
| | | | | | | On default fallback path there was null access on src_rb Signed-off-by: Juha-Pekka Heikkila <[email protected]> Reviewed-by: Anuj Phogat <[email protected]>
* i965: Add extra null check in intel_bufferobj_alloc()Juha-Pekka Heikkila2014-09-231-0/+3
| | | | | | | Check calloc returned requested memory. Signed-off-by: Juha-Pekka Heikkila <[email protected]> Reviewed-by: Anuj Phogat <[email protected]>
* i965: Avoid null access in intelMakeCurrent()Juha-Pekka Heikkila2014-09-231-3/+7
| | | | | | | separate two null checks connected with && to their own if branches. Signed-off-by: Juha-Pekka Heikkila <[email protected]> Reviewed-by: Anuj Phogat <[email protected]>
* i965: in set_read_rb_tex_image() check _mesa_meta_bind_rb_as_tex_image() did ↵Juha-Pekka Heikkila2014-09-232-5/+18
| | | | | | | | | | | succeed Check if _mesa_meta_bind_rb_as_tex_image() did give the texture. If no texture was given there is already either GL_INVALID_VALUE or GL_OUT_OF_MEMORY error set in context. Signed-off-by: Juha-Pekka Heikkila <[email protected]> Reviewed-by: Topi Pohjolainen <[email protected]>
* i915: Fix black buffers when importing prime fdsAndreas Pokorny2014-09-231-0/+2
| | | | | | | | | Width and Height of the imported image was never initialized from the imported bo. Cc: 10.2 10.3 <[email protected]> Signed-off-by: Andreas Pokorny <[email protected]> Reviewed-by: Daniel Stone <[email protected]>
* i965/fs: Remove direct fs_visitor brw_wm_prog_key dependenceJordan Justen2014-09-225-9/+36
| | | | | | | | Instead we store a void pointer to the key, and cast it to brw_wm_prog_key for fragment shader specific code paths. Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Anuj Phogat <[email protected]>
* i965/fs: Use brw_sampler_prog_key_data instead of brw_wm_prog_key::texJordan Justen2014-09-221-12/+29
| | | | | | | | | | This helps: 1. Reduce the need to have fs_visitor::key's type be brw_wm_prog_key* 2. Align the code to allow brw_sampler_prog_key_data to be pulled out of other prog_key types for different stages. Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Anuj Phogat <[email protected]>
* i965/fs: Remove direct fs_visitor brw_wm_prog_data dependenceJordan Justen2014-09-223-21/+56
| | | | | | | | Instead we store a brw_stage_prog_data pointer, and cast it to brw_wm_prog_data for fragment shader specific code paths. Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Anuj Phogat <[email protected]>
* i965/gen6: Enable GL 3.3 and GLSL 3.30Chris Forbes2014-09-202-9/+2
| | | | | | | | | | | | Tested on my snb-gt2: 4 tests skip->pass in spec/EXT_texture_array 51 tests skip->pass in spec.glsl-3.30 4 tests skip->pass in spec/!OpenGL 3.3 No regressions; no skip->fail changes. Signed-off-by: Chris Forbes <[email protected]> Reviewed-by: Jordan Justen <[email protected]>
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