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* i965: Consign COORD_REPLACE VS hacks to Pre-Gen6.Paul Berry2013-02-203-11/+34
| | | | | | | | | | | | | | | | | | | | | | | | | Pre-Gen6, the SF thread requires exact matching between VS output slots (aka VUE slots) and FS input slots, even when the corresponding VS output slot is unused due to being overwritten by point coordinate replacement (glTexEnvi(GL_POINT_SPRITE, GL_COORD_REPLACE, GL_TRUE)). As a result, we have a special hack in the VS to ensure when any texture coordinate is subject to point coordinate replacement, it is always allocated space in the VUE, even if it isn't written to by the VS. This hack isn't needed from Gen6 onwards, since SF (Gen7: SBE) swizzling has the ability to insert the point coordinate into gl_TexCoord[] without needing a corresponding unused VUE slot. Note that no modification of SF setup code is required for this patch--get_attr_override() already does the right thing. However, we make a slight comment change to clarify why this works. In addition to eliminating unnecessary VS recompiles and saving precious URB space on Gen6+, this will save us the trouble of having to adjust this hack when we implement geometry shaders. Reviewed-by: Kenneth Graunke <[email protected]>
* gles2: a stub implementation for GL_EXT_discard_framebufferTapani Pälli2013-02-201-0/+1
| | | | | | | | | | | This patch implements a stub for GL_EXT_discard_framebuffer with required checks listed by the extension specification. This extension is required by GLBenchmark 2.5 when compiled with OpenGL ES 2.0 as the rendering backend. Signed-off-by: Tapani Pälli <[email protected]> Reviewed-by: Brian Paul <[email protected]> Reviewed-and-tested-by: Chad Versace <[email protected]>
* i965/fs: Enable CSE on uniform pull constant loads.Eric Anholt2013-02-191-0/+3
| | | | | | | | Improves on a major performance regression for the dolphin wii emulator from its move to using UBOs. Performance in the UBO codepath (as replayed through apitrace) is up 21.1% +/- 2.3% (n=26/29). Reviewed-by: Kenneth Graunke <[email protected]>
* i965/fs: Only do CSE when the dst types match.Eric Anholt2013-02-191-1/+2
| | | | | | | | | | We could potentially do some CSE even when the dst types aren't the same on gen6 where there is no implicit dst type conversion iirc, or in the case of uniform pull constant loads where the dst type doesn't impact what's stored. But it's not worth worrying about. Reviewed-by: Kenneth Graunke <[email protected]> NOTE: This is a candidate for the 9.1 branch.
* i965/fs: Delay setup of uniform loads until after pre-regalloc scheduling.Eric Anholt2013-02-193-27/+66
| | | | | | | | This should fix the register allocation explosion on the GLES 3.0 test on gen6. It also gives us an instruction that will fit our CSE handling. Reviewed-by: Kenneth Graunke <[email protected]> NOTE: This is a candidate for the 9.1 branch.
* i965/fs: Fix copy propagation with smearing.Eric Anholt2013-02-191-1/+2
| | | | | | | | | | We were correctly relaying the smear from MOV's src, but if the MOV didn't do a smear, we don't want to smash the smear value from the instruction being propagated into. Prevents a regression in the upcoming UBO change. Reviewed-by: Kenneth Graunke <[email protected]> NOTE: This is a candidate for the 9.1 branch.
* i965/fs: Add a bit more instruction dumping useful for upcoming work.Eric Anholt2013-02-191-1/+30
| | | | Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Remove unused userclip flags.Paul Berry2013-02-193-5/+0
| | | | | | | | | | brw_vs_prog_data::userclip hasn't been used since commit f0cecd4 (i965: Move VUE map computation to once at VS compile time). brw_gs_prog_key::userclip_active hasn't been used since commit 9f3d321 (i965: Make the userclip flag for the VUE map come from VS prog data). Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Fix leak in blorp CopyTexSubImage2DChristopher James Halse Rogers2013-02-161-2/+2
| | | | | | | | | | | | | | | _mesa_delete_renderbuffer does not call the driver-specific renderbuffer delete function, so the blorp code was leaking the Intel-specific bits, including some GEM objects. Call the renderbuffer's ->Delete() method instead, which does the right thing. Fixes Unity rapidly sending the machine into the arms of the OOM-killer Note: This is a candidate for the 9.1 branch. Reviewed-by: Eric Anholt <[email protected]>
* i965/fs: Do a general SEND dependency workaround for the original 965.Eric Anholt2013-02-153-42/+229
| | | | | | | | | | | | | We'd been ad-hoc inserting instructions in some SEND messages with no knowledge of when it was required (so extra instructions), but not all SENDs (so not often enough). This should do much better than that, though it's still flow-control-ignorant. v2: Use BRW_MAX_MRF instead of magic numbers. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=58960 Reviewed-by: Kenneth Graunke <[email protected]> NOTE: Candidate for the stable branches.
* i965/gen7: Set up all samplers even if samplers are sparsely used.Eric Anholt2013-02-141-1/+1
| | | | | | | | | | | | | | | | | In GLSL, sampler indices are allocated contiguously from 0. But in the case of ARB_fragment_program (and possibly fixed function), an app that uses texture 0 and 2 will use sampler indices 0 and 2, so we were only allocating space for samplers 0 and 1 and setting up sampler 0. We would read garbage for sampler 2, resulting in flickering textures and an angry simulator. Fixes bad rendering in 0 A.D. and ETQW. This was fixed for pre-gen7 by 28f4be9eb91b12a2c6b1db6660cca71a98c486ec Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=25201 Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=58680 Reviewed-by: Kenneth Graunke <[email protected]> NOTE: This is a candidate for stable branches.
* intel: Allow blit readpixels even when the pack alignment is set.Eric Anholt2013-02-131-9/+4
| | | | | | | | | | The default alignment is 4, so this fast path was rarely hit. Rather than introduce logic to handle alignment, just use the Mesa core function. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=46632 Cc: [email protected] Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Remove writemask support from brw_SAMPLE().Eric Anholt2013-02-135-109/+18
| | | | | | | | | | The code was rather broken for non-XYZW on 8-wide, but all of our callers were using XYZW anyway. For my experiments with using writemask on texturing, I've been using manual header setup in the compiler backends, since we want to actually know what registers are written for optimization and register allocation. Reviewed-by: Kenneth Graunke <[email protected]>
* i965/fs: Use a helper function for checking for flow control instructions.Eric Anholt2013-02-133-23/+22
| | | | | | | In 2 of our checks, we were missing BREAK and CONTINUE. NOTE: Candidate for the stable branches. Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Re-enable the -RHW workaround for original gen4 chips.Eric Anholt2013-02-131-12/+8
| | | | | | | | Fixes broken clipping in supertuxkart and presumably many other applications. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=51471 NOTE: Candidate for the stable branches. Reviewed-by: Kenneth Graunke <[email protected]>
* i965/gen4: Work around missing sRGB RGB DXT1 support.Eric Anholt2013-02-133-4/+20
| | | | | | | | | | | The hardware just doesn't support it. I suspect this was a regression from the move to fixed MESA_FORMATs for compressed textures and that previously we were storing uncompressed for this or something. Fixes GPU hangs in piglit "texwrap GL_EXT_texture_sRGB-s3tc bordercolor swizzled" on my GM965. Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Use derived state for Haswell's 3DSTATE_VF packet.Kenneth Graunke2013-02-121-2/+2
| | | | | | | | | | | Otherwise, we fail to correctly handle GL_PRIMITIVE_RESTART_FIXED_INDEX. Fixes gles3conform's primitive_restart_mode test. NOTE: This is a candidate for the 9.1 branch. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* radeon: Remove dead STANDALONE_MMIO definesMatt Turner2013-02-112-3/+0
| | | | | | | | | | | | These were, at some point in the past, used to request that Xorg's compiler.h export a static inline xf86ReadMmio32 instead of a function pointer. compiler.h only has this option for DEC Alpha. But Xorg's compiler.h isn't being included by either of these two files and the radeon driver still works on Alpha, so the definitions are dead and not needed. Reviewed-by: Michel Dänzer <[email protected]>
* i965: Add missing dirty bits to INTEL_DEBUG=state arrays.Kenneth Graunke2013-02-111-0/+7
| | | | | | | | These are more recent additions, and no one remembered to update the INTEL_DEBUG=state code. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* i965: Reorganize brw_bits to match the order in brw_context.h.Kenneth Graunke2013-02-111-5/+5
| | | | | | | | | | This reorders the "brw_bits" array in brw_state_upload.c to match the order of the #defines in brw_context.h. Otherwise, it's really hard to see if any are missing. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* i965: Use BRW_NEW_CONTEXT for gen7_disable rather than BRW_NEW_BATCH.Kenneth Graunke2013-02-111-1/+1
| | | | | | | | These don't need to be re-disabled on every batch if we're using hardware contexts. (If we're not, this is equivalent.) Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* i965: Remove some stale comments about the brw_constant_buffer atom.Eric Anholt2013-02-112-12/+0
| | | | | | | These have been wrong since f428255bde93a452a7cdd48fba21839c99beb6cb back in 2009! Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Simplify VS push constant upload code since removal of old path.Eric Anholt2013-02-111-7/+11
| | | | | | | | | | We used to have clip planes optionally included in the push constants, resulting in a variable amount of data uploaded, but no more. This also means less wasted space in the batch for our push constants. v2: Update _NEW_TRANSFORM state bit information. Reviewed-by: Kenneth Graunke <[email protected]> (v1)
* i965: Add perf debug for a corner case.Eric Anholt2013-02-111-0/+3
| | | | Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Fix access mode of index buffer rebase.Eric Anholt2013-02-111-1/+1
| | | | | | | It doesn't matter with our current implementation of MapBufferRange, but it was wrong -- the result pointer is read by intel_upload_data(). Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Fix indentation of index buffer rebase code.Eric Anholt2013-02-111-9/+9
| | | | Reviewed-by: Kenneth Graunke <[email protected]>
* intel: Do not expose OES_compressed_ETC1_RGB8_texture or ↵Ian Romanick2013-02-081-2/+2
| | | | | | | | | | | | | | ARB_texture_rgb10_a2ui pre-GEN4 Older hardware cannot do ARB_texture_rgb10_a2ui, and the translation code for OES_compressed_ETC1_RGB8_texture was never implemented in the i915 driver. NOTE: This is a candidate for all stable branches. Signed-off-by: Ian Romanick <[email protected]> Reviewed-by: Anuj Phogat <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* intel: Ensure variable intel is used in i915 builds.Vinson Lee2013-02-081-1/+1
| | | | | | | | Fixes unused pointer value defect reported by Coverity. Signed-off-by: Vinson Lee <[email protected]> Reviewed-by: Brian Paul <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* Consolidate some redundant definitions of ARRAY_SIZE() macro.Paul Berry2013-02-084-6/+2
| | | | | | | | | | | | | | | | | | | | | Previous to this patch, there were 13 identical definitions of this macro in Mesa source. That's ridiculous. This patch consolidates 6 of them to a single definition in src/mesa/main/macros.h. Unfortunately, I wasn't able to eliminate the remaining definitions, since they occur in places that don't include src/mesa/main/macros.h: - include/pci_ids/pci_id_driver_map.h - src/egl/drivers/dri2/egl_dri2.h - src/egl/main/egldefines.h - src/gbm/main/backend.c - src/gbm/main/gbm.c - src/glx/glxclient.h - src/mapi/mapi/stub.c I'm open to suggestions as to how to deal with the remaining redundancy. Reviewed-by: Kenneth Graunke <[email protected]>
* intel/pre-gen6: Disable EXT_framebuffer_multisample.Paul Berry2013-02-083-12/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Previously, the i965 driver enabled EXT_framebuffer_multisample even on pre-gen6 chipsets. However, since we don't support multisampling on these chips, we set GL_MAX_SAMPLES=1 (the minimum allowed by EXT_framebuffer_multisample), and if the client ever requested a multisample buffer, we quietly supplied them with a single-sampled buffer instead. After some discussion on the mailing list (see thread "ext_framebuffer_multisample: check for num_samples<=1"), it's clear that this was the wrong approach. The correct approach is to only expose EXT_framebuffer_multisample when we truly support multisampling; that frees us to set a sensible value of GL_MAX_SAMPLES=0 on other chipsets, so that we never have to deal with a client requesting a multisample buffer when multisampling isn't supported. This change causes the following piglit tests to be skipped on chipsets prior to Gen6: - "ARB_framebuffer_sRGB/blit {renderbuffer,texture} {linear,linear_to_srgb,srgb,srgb_to_linear} {downsample,msaa,upsample} {disabled,enabled}" - EXT_framebuffer_multisample/blit-mismatched-formats - EXT_framebuffer_multisample/blit-mismatched-sizes - EXT_framebuffer_multisample/dlist - EXT_framebuffer_multisample/interpolation 0 * - EXT_framebuffer_multisample/minmax - EXT_framebuffer_multisample/negative-copypixels - EXT_framebuffer_multisample/negative-copyteximage - EXT_framebuffer_multisample/negative-max-samples - EXT_framebuffer_multisample/negative-mismatched-samples - EXT_framebuffer_multisample/negative-readpixels - EXT_framebuffer_multisample/renderbuffer-samples - EXT_framebuffer_multisample/renderbufferstorage-samples - EXT_framebuffer_multisample/samples This is expected, since the above tests exercise MSAA functionality, and shouldn't be run on systems prior to Gen6. Reviewed-by: Eric Anholt <[email protected]>
* i965: Set UniformBufferOffsetAlignment to sizeof(vec4)Ian Romanick2013-02-071-0/+1
| | | | | | | | | | | This matches the behavior of the Windows driver, but a bspec reference should would be nice. NOTE: This is a candidate for the 9.0 and 9.1 branches. Signed-off-by: Ian Romanick <[email protected] Reviewed-by: Eric Anholt <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965/blorp: Support blits between ARGB and XRGB formats.Kenneth Graunke2013-02-061-14/+12
| | | | | | | | | | | | | | | Now that we have support for overriding alpha to 1.0, we can handle blitting between these formats in either direction. For now, we only support two XRGB formats: MESA_FORMAT_XRGB8888 and MESA_FORMAT_RGBX8888_REV. Most places only appear to worry about the former, so ignore the latter for now. We can always add it later. NOTE: This is a candidate for the 9.1 branch. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Ian Romanick <[email protected]> Tested-by: Martin Steigerwald <[email protected]>
* i965/blorp: Support overriding destination alpha to 1.0.Kenneth Graunke2013-02-061-0/+19
| | | | | | | | | | | | | | | | | | | | Currently, Blorp requires the source and destination formats to be equal. However, we'd really like to be able to blit between XRGB and ARGB formats; our BLT engine paths have supported this for a long time. For ARGB -> XRGB, nothing needs to occur: the missing alpha is already interpreted as 1.0. For XRGB -> ARGB, we need to smash the alpha channel to 1.0 when writing the destination colors. This is fairly straightforward with blending. For now, this code is never used, as the source and destination formats still must be equal. The next patch will relax that restriction. NOTE: This is a candidate for the 9.1 branch. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Ian Romanick <[email protected]> Tested-by: Martin Steigerwald <[email protected]>
* i965: Implement CopyTexSubImage2D via BLORP (and use it by default).Kenneth Graunke2013-02-065-8/+154
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The BLT engine has many limitations. Currently, it can only blit X-tiled buffers (since we don't have a kernel API to whack the BLT tiling mode register), which means all depth/stencil operations get punted to meta code, which can be very CPU-intensive. Even if we used the BLT engine, it can't blit between buffers with different tiling modes, such as an X-tiled non-MSAA ARGB8888 texture and a Y-tiled CMS ARGB8888 renderbuffer. This is a fundamental limitation, and the only way around that is to use BLORP. Previously, BLORP only handled BlitFramebuffer. This patch adds an additional frontend for doing CopyTexSubImage. It also makes it the default. This is partly to increase testing and avoid hiding bugs, and partly because the BLORP path can already handle more cases. With trivial extensions, it should be able to handle everything the BLT can. This helps PlaneShift massively, which tries to CopyTexSubImage2D between depth buffers whenever a player casts a spell. Since these are Y-tiled, we hit meta and software ReadPixels paths, eating 99% CPU while delivering ~1 FPS. This is particularly bad in an MMO setting because people cast spells all the time. It also helps Xonotic in 4X MSAA mode. At default power management settings, I measured a 6.35138% +/- 0.672548% performance boost (n=5). (This data is from v1 of the patch.) No Piglit regressions on Ivybridge (v3) or Sandybridge (v2). v2: Create a fake intel_renderbuffer to wrap the destination texture image and then reuse do_blorp_blit rather than reimplementing most of it. Remove unnecessary clipping code and conditional rendering check. v3: Reuse formats_match() to centralize checks; delete temporary renderbuffers. Reorganize the code. v4: Actually copy stencil when dealing with separate stencil buffers but packed depth/stencil formats. Tested by a new Piglit test. NOTE: This is a candidate for the 9.1 branch. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Paul Berry <[email protected]> [v4] Reviewed-by: Ian Romanick <[email protected]> [v3] Reviewed-and-tested-by: Carl Worth <[email protected]> [v2] Tested-by: Martin Steigerwald <[email protected]> [v3]
* mesa: fixup inconsistent naming of RG16 formatsMarek Olšák2013-02-062-3/+3
| | | | Reviewed-by: Brian Paul <[email protected]>
* i965: Disable write masking when setting up texturing m0.Eric Anholt2013-02-042-1/+4
| | | | | | | | | | v2/Kayden: Also disable write masking in the vec4 backend. Fixes 78 oglconform glsl-bif-tex-* subcases. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Paul Berry <[email protected]> [v1] Reviewed-by: Eric Anholt <[email protected]> [v2]
* intel: Fix regression in intel_create_image_from_name stride handlingTapani Pälli2013-02-041-1/+1
| | | | | | | | | Strangely, the DRIimage interface we have passes the pitch in pixels instead of bytes, which anholt missed in the change to using bytes for region pitch. Signed-off-by: Tapani Pälli <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* i965: Fix segfaults from 45a28a927ab7f29ff325b9326d386a39ba538c18Eric Anholt2013-02-042-2/+4
| | | | | | If you look up a level that isn't in the miptree, you crash. Reviewed-by: Chad Versace <[email protected]>
* intel: make sure to setup image dimension in image_from_planar setupAbdiel Janulgue2013-02-041-0/+1
| | | | | | | | Fixes: https://bugs.freedesktop.org/show_bug.cgi?id=60212 Tested-by: Scott Moreau <[email protected]> Tested-by: Tiago Vignatti <[email protected]> Reviewed-by: Chad Versace <[email protected]> Signed-off-by: Abdiel Janulgue <[email protected]>
* i965: Fix the SF Vertex URB Read Length calculation for Gen7 platforms.Kenneth Graunke2013-02-031-16/+16
| | | | | | | | | | | | | | | | | | | Ivybridge doesn't appear to have the same errata as Sandybridge; no corruption was observed by setting it to more than the minimal correct value. It's possible that we were simply lucky, since the URB entries are 1024-bit on Ivybridge vs. 512-bit Sandybridge. Or perhaps the underlying hardware issue is fixed. Either way, we may as well program the minimum value since it's now readily available, likely to be more efficient, and possibly more correct. v2: Use GEN7_SBE_* defines rather than GEN6_SF_*. (A copy and paste mistake.) They're the same, but using the right names is better. NOTE: This is a candidate for all stable branches. Reviewed-by: Paul Berry <[email protected]> Signed-off-by: Kenneth Graunke <[email protected]>
* i965: Fix the SF Vertex URB Read Length calculation for Sandybridge.Kenneth Graunke2013-02-031-16/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | (This commit message was primarily written by Paul Berry, who explained what's going on far better than I would have.) Previous to this patch, we thought that the only restrictions on 3DSTATE_SF's URB read length were (a) it needs to be large enough to read all the VUE data that the SF needs, and (b) it can't be so large that it tries to read VUE data that doesn't exist. Since the VUE map already tells us how much VUE data exists, we didn't bother worrying about restriction (a); we just did the easy thing and programmed the read length to satisfy restriction (b). However, we didn't notice this erratum in the hardware docs: "[errata] Corruption/Hang possible if length programmed larger than recommended". Judging by the context surrounding this erratum, it's pretty clear that it means "URB read length must be exactly the size necessary to read all the VUE data that the SF needs, and no larger". Which means that we can't program the read length based on restriction (b)--we have to program it based on restriction (a). The URB read size needs to precisely match the amount of data that the SF consumes; it doesn't work to simply base it on the size of the VUE. Thankfully, the PRM contains the precise formula the hardware expects. Fixes random UI corruption in Steam's "Big Picture Mode", random terrain corruption in PlaneShift, and Piglit's fbo-5-varyings test. NOTE: This is a candidate for all stable branches. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=56920 Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=60172 Tested-by: Jordan Justen <[email protected]> (v1/Piglit) Tested-by: Martin Steigerwald <[email protected]> (PlaneShift) Reviewed-by: Paul Berry <[email protected]> Signed-off-by: Kenneth Graunke <[email protected]>
* i965: Compute the maximum SF source attribute.Kenneth Graunke2013-02-033-4/+12
| | | | | | | | | | The maximum SF source attribute is necessary to compute the Vertex URB read length properly, which will be done in the next commit. NOTE: This is a candidate for all stable branches. Reviewed-by: Paul Berry <[email protected]> Tested-by: Martin Steigerwald <[email protected]> Signed-off-by: Kenneth Graunke <[email protected]>
* i965: Refactor Gen6+ SF attribute override code.Kenneth Graunke2013-02-031-12/+13
| | | | | | | | | | | The next patch will benefit from easy access to the source attribute number and whether or not we're swizzling. It doesn't want the final attr_override DWord form, however. NOTE: This is a candidate for all stable branches. Reviewed-by: Paul Berry <[email protected]> Tested-by: Martin Steigerwald <[email protected]> Signed-off-by: Kenneth Graunke <[email protected]>
* i965: Remove dead field brw_wm_prog_data::error.Kenneth Graunke2013-02-031-1/+0
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* i965: Remove dead field brw_context::constant_map.Kenneth Graunke2013-02-031-1/+0
| | | | This was used by the old VS backend, but that's long gone.
* swrast: Fix memory leak.Vinson Lee2013-02-011-0/+1
| | | | | | | Fixes resource leak defect reported by Coverity. Signed-off-by: Vinson Lee <[email protected]> Reviewed-by: Brian Paul <[email protected]>
* intel: implement create image from textureAbdiel Janulgue2013-02-011-21/+138
| | | | | | | | | | | | | | | | | Save miptree level info to DRIImage: - Appropriately-aligned base offset pointing to the image - Additional x/y adjustment offsets from above. v8: -Bump intelImageExtension version v9: -Don't use internal _eglError but implement error reporting in new DRI inteface instead. This fixes Android build problems based on feedback from Adrian M Negreanu and Chad Versace. -Move the non-tile-aligned check and error-reporting to intel_set_texture_image_region v10: -Don't #include "egl/main/eglcurrent.h". [chadv] Reviewed-by: Eric Anholt <[email protected]> (v6) Acked-by: Chad Versace <[email protected]> (v10) Signed-off-by: Abdiel Janulgue <[email protected]>
* intel: Account for mt->offset in intel_miptree_mapAbdiel Janulgue2013-02-011-2/+2
| | | | | | | | | | | We need to take account the offset from original bo when using glTexSubImage() and other functions that manipulate the subregion of an exported texture. Offsets are appended to mapped region address and when blitting from a source region. Reviewed-by: Eric Anholt <[email protected]> Reviewed-by: Chad Versace <[email protected]> Signed-off-by: Abdiel Janulgue <[email protected]>
* intel: Create a miptree using offsets in intel_set_texture_image_regionAbdiel Janulgue2013-02-011-7/+53
| | | | | | | | | | | | | | | | When binding a region to a texture image, re-create the miptree base-level considering the offset and dimension information exported by DRIImage. v8: - Move the alignment surface address checks from the image-from-texture code to the texture-from-image side. This allows the error reporting to conform to OES_EGL_Image and to prevent mixing up EGL and GL errors. Reported by Chad Versace. - Addressed an existing issue in renderbuffer case where there is a a possibility of creating EGL images out of depthstencil textures which isn't really possible. This was spotted by Eric earlier. Reviewed-by: Eric Anholt <[email protected]> (v6) Reviewed-by: Chad Versace <[email protected]> (v8) Signed-off-by: Abdiel Janulgue <[email protected]>
* i965: Account for offsets when updating SURFACE_STATE.Abdiel Janulgue2013-02-012-2/+21
| | | | | | | | | If the offsets are present, this lets us specify a particular level and slice in a shared region using the base level of an exported mip-map tree. Reviewed-by: Eric Anholt <[email protected]> Reviewed-by: Chad Versace <[email protected]> Signed-off-by: Abdiel Janulgue <[email protected]>
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