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* i965: Throw out guts of struct brw_instruction.Matt Turner2014-06-261-644/+1
| | | | | Signed-off-by: Matt Turner <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Convert brw_gs_emit.c to the new brw_inst API.Matt Turner2014-06-261-3/+4
| | | | | Signed-off-by: Matt Turner <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Convert brw_disasm.c to the new brw_inst API.Matt Turner2014-06-261-341/+316
| | | | | | | | | | | | | | | | | | v2: (by Kenneth Graunke) - Fix disassembly of Gen4-5 SEND messages to print base MRF correctly. - Only print URB opcode on Gen5+, to match previous output (besides, there is only one opcode AFAICT.) - Only print the low 3 bits of msg_control, to match previous output. (We probably should decode all the fields, but hadn't previously due to the brw_instruction structure definition splitting out bits 4/5 for last_render_target and slot_group_select.) - Fix 3-source MRF/GRF file decoding on Sandybridge. - Fix compression code to use qtr_control rather than cmpt_control (which is compaction, not compression). Signed-off-by: Matt Turner <[email protected]> Signed-off-by: Kenneth Graunke <[email protected]> [v2] Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Pass brw rather than gen to brw_disassemble_inst().Matt Turner2014-06-265-33/+33
| | | | | | | We will need it in order to use the new brw_inst API. Signed-off-by: Matt Turner <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Convert brw_eu_compact.c to the new brw_inst API.Matt Turner2014-06-261-105/+104
| | | | | | | | v2: Use brw_inst_bits rather than pulling out individual fields and reassembling them. Signed-off-by: Matt Turner <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Extend is_haswell checks to gen >= 8 in Gen4-7 generators.Kenneth Graunke2014-06-262-7/+7
| | | | | | | | | We're going to use fs_generator/vec4_generator for Gen8+ code soon, thanks to the new brw_instruction API. When we do, we'll generally want to take the Haswell paths on Gen8+ as well. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* i965: Convert test_eu_compact.c to the new brw_inst API.Kenneth Graunke2014-06-261-22/+19
| | | | | Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* i965: Convert vec4_generator to the new brw_inst API.Kenneth Graunke2014-06-261-8/+8
| | | | | Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* i965: Convert fs_generator to the new brw_inst API.Kenneth Graunke2014-06-261-9/+9
| | | | | Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* i965: Convert Gen4-5 clipping code to the new brw_inst API.Kenneth Graunke2014-06-264-41/+52
| | | | | Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* i965: Convert brw_sf_emit.c to the new brw_inst API.Kenneth Graunke2014-06-261-3/+4
| | | | | Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* i965: Convert brw_eu_emit.c to the new brw_inst API.Kenneth Graunke2014-06-261-482/+461
| | | | | | | | | | | v2: - Fix IF -> ELSE patching on Sandybridge. - Don't set base_mrf on Gen6+ in OWord Block Read functions. (Although - the old code did this universally, it shouldn't have - the field - doesn't exist on Gen6+ and just got overwritten by the SFID anyway.) Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* i965: Convert brw_eu.[ch] to use the new brw_inst API.Kenneth Graunke2014-06-262-16/+19
| | | | | | | v2: Don't set flag_reg_nr prior to Gen7 (as it doesn't exist). Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* i965: Introduce a new brw_inst API.Kenneth Graunke2014-06-261-0/+707
| | | | | | | | | | | | | | | | | | | This is similar to gen8_instruction, and will eventually replace it. For now nothing uses this, but we can incrementally convert. The new API takes the existing brw_instruction pointers to ease conversion; when done, we can simply drop the old structure and rename struct brw_instruction -> brw_inst. v2: (by Matt Turner) Make JIP/UIP functions take a signed argument. v3: (by Kenneth Graunke) - Make Gen4-6 jump target functions take a signed argument. - Fix indirect align1 AddrImm bits on Gen4-7. - Fix SFID on Sandybridge to use bits 27:24. Signed-off-by: Kenneth Graunke <[email protected]> [v1, v3+] Signed-off-by: Matt Turner <[email protected]> [v2] Reviewed-by: Matt Turner <[email protected]>
* i965: Pass brw into next_offset().Kenneth Graunke2014-06-263-9/+12
| | | | | | | | The new brw_inst API is going to require a brw pointer in order to access fields (so it can do generation checks). Plumb it in now. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* i965: Remove unneeded VS workaround stalls on Baytrail.Greg Hunt2014-06-264-6/+6
| | | | | | | | | | | | | According to the workarounds list, these stalls aren't needed on production Baytrail systems. Piglit confirms that as well. These cause a small slowdown when we are sending a large number of small batches to the GPU. Removing these improves performance by up to 5% on some CPU bound SynMark tests (Batch[4-7], DrvState1, HdrBloom, Multithread, ShMapPcf). Signed-off-by: Gregory Hunt <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965/fs: Check variable_storage return value in fs_visitor::visitJuha-Pekka Heikkila2014-06-261-0/+6
| | | | | | | check variable_storage() found the requested fs_reg. Signed-off-by: Juha-Pekka Heikkila <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* i965: Handle miptree creation failure in intel_alloc_texture_storage()Juha-Pekka Heikkila2014-06-261-0/+3
| | | | | | | | Check intel_miptree_create() return value before using it as a pointer. Signed-off-by: Juha-Pekka Heikkila <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* i965: Check calloc return value in gather_statistics_results()Juha-Pekka Heikkila2014-06-261-1/+14
| | | | | | | | Check calloc return value and report on error, also later skip results handling if there was no memory to store results to. Signed-off-by: Juha-Pekka Heikkila <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* i965/vec4: Try constant propagate after copy propagate made progress.Matt Turner2014-06-251-2/+4
| | | | Reviewed-by: Kenneth Graunke <[email protected]>
* i965/vec4: Make try_copy_propagate() static.Matt Turner2014-06-252-7/+4
| | | | | | | Now that can_do_source_mods() isn't part of the visitor, this doesn't need to be either. Reviewed-by: Kenneth Graunke <[email protected]>
* i965/vec4: Rename try_copy/constant_propagat{ion,e} to match the fs.Matt Turner2014-06-252-8/+8
| | | | Reviewed-by: Kenneth Graunke <[email protected]>
* i965/vec4: Constant propagate into 2-src math instructions on Gen8.Matt Turner2014-06-251-2/+9
| | | | Reviewed-by: Kenneth Graunke <[email protected]>
* i965/fs: Constant propagate into 2-src math instructions on Gen8.Matt Turner2014-06-251-2/+9
| | | | | | | total instructions in shared programs: 1878133 -> 1876986 (-0.06%) instructions in affected programs: 153007 -> 151860 (-0.75%) Reviewed-by: Kenneth Graunke <[email protected]>
* i965/fs: Make try_constant_propagate() static.Matt Turner2014-06-252-3/+2
| | | | Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Make can_do_source_mods() a member of the instruction classes.Matt Turner2014-06-256-14/+12
| | | | | | | Pretty nonsensical to have it as a method of the visitor just for access to brw. Reviewed-by: Kenneth Graunke <[email protected]>
* i965/fs: Don't fix_math_operand() on Gen >= 8.Matt Turner2014-06-241-2/+4
| | | | | | Reviewed-by: Ben Widawsky <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* i965/vec4: Don't fix_math_operand() on Gen >= 8.Matt Turner2014-06-241-2/+6
| | | | | | | | The emit_math?_gen? functions serve to implement workarounds for the math instruction, none of which exist on Gen8+. Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* i965/vec4: Don't return void from a void function.Matt Turner2014-06-241-4/+4
| | | | | | Reviewed-by: Ben Widawsky <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* i965: Don't emit SURFACE_STATEs for gather workarounds on Broadwell.Kenneth Graunke2014-06-232-8/+15
| | | | | | | | | | | | | As far as I can tell, Broadwell doesn't need any of the SURFACE_STATE workarounds for textureGather() bugs, so there's no need to emit a second set of identical copies. To keep things simple, just point the gather surface index base to the same place as the texture surface index base. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Chris Forbes <[email protected]> Cc: "10.2" <[email protected]>
* i965: Allow the blorp blit between BGR and RGBNeil Roberts2014-06-231-7/+21
| | | | | | | | | | | | | | | | | | | | Previously the blorp blitter would only be used if the format is identical or there is only a difference between whether there is an alpha component or not. This patch makes it also allow the blorp blitter if the only difference is the ordering of the RGB components (ie, RGB or BGR). This is particularly useful since commit 61e264f4fcdba3623 because Mesa now prefers RGB ordering for textures but the window system buffers are still created as BGR. That means that the blorp blitter won't be used for the (probably) common case of blitting from a texture to the window system buffer. This doesn't cause any regressions in the FBO piglit tests on Haswell. On Sandybridge it causes the fbo-blit-stretch test to fail but that is only because it was failing anyway before the above commit and that commit hid the problem. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=68365 Reviewed-by: Matt Turner <[email protected]>
* i915: Fix gen2 texblend setupVille Syrjälä2014-06-231-1/+1
| | | | | | | | | | | | | | | | | Fix an off by one in the texture unit walk during texblend setup on gen2. This caused the last enabled texunit to be skipped resulting in totally messed up texturing. This is a regression introduced here: commit 1ad443ecdd694dd9bf3c4a5050d749fb80db6fa2 Author: Eric Anholt <[email protected]> Date: Wed Apr 23 15:35:27 2014 -0700 i915: Redo texture unit walking on i830. Reviewed-by: Ian Romanick <[email protected]> Cc: "10.2" <[email protected]> Signed-off-by: Ville Syrjälä <[email protected]>
* i965: Save meta stencil blit programs in the context.Kenneth Graunke2014-06-212-8/+13
| | | | | | | | | | | | | | | | | | | | | | | When the last context in a share group is destroyed, the hash table containing all of the shader programs (ctx->Shared->ShaderObjects) is destroyed, throwing away all of the shader programs. Using a static variable to store program IDs ends up holding on to them after this, so we think we still have a compiled program, when it actually got destroyed. _mesa_UseProgram then hits GL errors, since no program by that ID exists. Instead, store the program IDs in the context, so we know to recompile if our context gets destroyed and the application creates another one. Fixes es3conform tests when run without -minfmt (where it creates separate contexts for testing each visual). Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=77865 Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]> Reviewed-by: Ian Romanick <[email protected]> Cc: "10.2" <[email protected]>
* meta: Respect the driver's maximum number of draw buffersIan Romanick2014-06-181-2/+2
| | | | | | | | | | | | | | | Commit c1c1cf5f9 added infrastructure for saving and restoring draw buffer state. However, it universially used MAX_DRAW_BUFFERS, but many drivers support far fewer than that at limit. For example, the radeon and i915 drivers only support 1. Using MAX_DRAW_BUFFERS causes meta to generate GL errors. Signed-off-by: Ian Romanick <[email protected]> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=80115 Reviewed-by: Kenneth Graunke <[email protected]> Tested-by: Kenneth Graunke <[email protected]> [on Broadwell] Tested-by: [email protected] Cc: "10.2" <[email protected]>
* i965/vec4: unit test for copy propagation and writemaskChia-I Wu2014-06-181-0/+30
| | | | | | | | This unit test demonstrates a subtle bug fixed by 4ddf51db6af36736d5d42c1043eeea86e47459ce. Signed-off-by: Chia-I Wu <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* i965/vec4/gs: Silence warning about unused 'success' in release build.Matt Turner2014-06-171-0/+1
| | | | | Reviewed-by: Tapani Pälli <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* i965/disasm: Mark three_source_reg_encoding[] static.Matt Turner2014-06-171-1/+1
| | | | | Reviewed-by: Tapani Pälli <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* i965/blorp: Remove unused 'brw' member.Matt Turner2014-06-171-2/+0
| | | | | Reviewed-by: Tapani Pälli <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* i965/blorp: Mark branch unreachable to silence uninitialized var warning.Matt Turner2014-06-171-0/+1
| | | | | Reviewed-by: Tapani Pälli <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* i965: Silence warning about unused brw in release builds.Matt Turner2014-06-171-2/+1
| | | | | Reviewed-by: Tapani Pälli <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* i965: Mark backend_instruction and bblock_t as structs.Matt Turner2014-06-172-2/+2
| | | | | | | | | They have to be marked as structs for C code elsewhere. bblock_t is already defined as a struct, and all of backend_instruction's fields are public anyway. Reviewed-by: Tapani Pälli <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* i965: Use standard SSE intrinsics instead of gcc built-ins.Matt Turner2014-06-171-5/+7
| | | | | | | | Let's this file compile with clang. Reviewed-by: Frank Henigman <[email protected]> Reviewed-by: Tapani Pälli <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* mesa: Mark default case unreachable to silence warning.Matt Turner2014-06-171-0/+1
| | | | | | | | Warned about 'coord' being undefined in the default case, which is unreachable. Reviewed-by: Tapani Pälli <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* Revert "i965: Add 'wait' instruction support"Matt Turner2014-06-173-34/+0
| | | | | | This reverts commit 20be3ff57670529a410b30a1008a71e768d08428. No evidence of ever being used.
* i965/fs: Optimize SEL with the same sources into a MOV.Matt Turner2014-06-171-1/+7
| | | | | | instructions in affected programs: 474 -> 462 (-2.53%) Reviewed-by: Kenneth Graunke <[email protected]>
* i965/fs: Perform CSE on texture operations.Matt Turner2014-06-171-1/+10
| | | | | | | | Helps Unigine Tropics and some (old) gstreamer shaders in shader-db. instructions in affected programs: 792 -> 744 (-6.06%) Reviewed-by: Kenneth Graunke <[email protected]>
* i965/fs: Copy propagate from load_payload.Matt Turner2014-06-171-0/+22
| | | | | But only into non-load_payload instructions. Otherwise we would prevent register coalescing from combining identical payloads.
* i965/fs: Perform CSE on load_payload instructions if it's not a copy.Matt Turner2014-06-171-0/+18
| | | | | | | | | | | | | | Since CSE creates instructions, if we let CSE generate things register coalescing can't remove, bad things will happen. Only let CSE combine non-copy load_payloads. E.g., allow CSE to handle this load_payload vgrf4+0, vgrf5, vgrf6 but not this load_payload vgrf4+0, vgrf5+0, vgrf5+1
* i965/fs: Support register coalescing on LOAD_PAYLOAD operands.Matt Turner2014-06-171-10/+54
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* i965/fs: Emit load_payload instead of multiple MOVs for large VGRFs.Matt Turner2014-06-171-12/+21
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