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* glsl: Add a new ir_txs (textureSize) opcode to ir_texture.Kenneth Graunke2011-08-231-1/+5
| | | | | | | | One unique aspect of TXS is that it doesn't have a coordinate. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Ian Romanick <[email protected]> Reviewed-by: Dave Airlie <[email protected]>
* intel: Abort when DRI2 separate stencil handshake failsChad Versace2011-08-221-0/+7
| | | | | | | | | | When intel_context requires separate stencil but the DRI2 separate stencil handshake fails, then abort and emit an error instructing the user to upgrade the DDX to 2.16.0. CC: Eric Anholt <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Signed-off-by: Chad Versace <[email protected]>
* i965/gen7: Use align1 mode to set URB_WRITE_HWORD channel enables.Kenneth Graunke2011-08-201-0/+3
| | | | | | | Makes the new vertex shader backend work on Ivybridge. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* i965/fs: Don't double-convert integer/boolean uniforms.Kenneth Graunke2011-08-191-16/+20
| | | | | | | | | | | | | When ctx->Const.NativeIntegers is set, Core Mesa loads integer/boolean uniforms directly, rather than loading the floating point equivalent. So, when that's set, we don't need to perform any conversions. Unfortunately, we can't properly support native integers with the old vertex shader backend, so this patch leaves them disabled for now. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Ian Romanick <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* i965/fs: Change incorrect use of 'struct fs_reg' to simply 'fs_reg'.Kenneth Graunke2011-08-191-1/+1
| | | | | | It's actually a class. Signed-off-by: Kenneth Graunke <[email protected]>
* i965/vs: Implement proper register allocation instead of 1:1 mapping.Eric Anholt2011-08-192-1/+155
| | | | | | Fixes vs-atan-* and several others. This is not the real solution we eventually want, which will pack floats, vec2s, and vec3s into vec4 registers, but this code should provide the framework for that.
* i965/vs: Add simple dead code elimination.Eric Anholt2011-08-193-0/+38
| | | | | This is copied right from the fragment shader. It is needed for real register allocation to work correctly.
* i965/vs: Copy the live intervals calculation over from the FS.Eric Anholt2011-08-194-0/+139
| | | | | | This is a rather pessimistic calculation, since it doesn't distinguish individual channels of a vec4, or elements of an array, but should be a minimum start for register allocation.
* i965/vs: Remove stale comment about compressed instructions.Eric Anholt2011-08-191-1/+0
| | | | | This was copy'n'paste from the fragment shader, and didn't make sense here.
* meta: use fallback mipmap generation for 1D/2D texture arraysBrian Paul2011-08-191-2/+5
| | | | | | | We could do 1D/2D arrays with textured quad rendering, but it'll take some work (as with 3D textures). Reviewed-by: Ian Romanick <[email protected]>
* mesa: Declare _mesa_meta_begin()/end() as publicChad Versace2011-08-192-142/+147
| | | | | | | | | | | Declare _mesa_meta_begin()/end() in meta.h so that drivers can write custom meta-ops (such as HiZ resolves for i965). This necessitates moving the the META_* macros into meta.h. To prevent naming collisions, this commit renames each macro to be MESA_META_*. Reviewed-by: Brian Paul <[email protected]> Signed-off-by: Chad Versace <[email protected]>
* i965/fs: Fix 32-bit integer multiplication.Eric Anholt2011-08-172-1/+22
| | | | | | | | | The MUL opcode does a 16bit * 32bit multiply, and we need to do the MACH to get the top 16bit * 32bit added in. Fixes fs-op-mult-int-*, fs-op-mult-ivec* Reviewed-by: Kenneth Graunke <[email protected]>
* xmlpool.h: fix a typoLauri Kasanen2011-08-171-1/+1
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* xmlconfig: Make the error message more informativeLauri Kasanen2011-08-171-1/+1
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* i965/vs: Fix multiplies to actually do 32-bit multiplies.Eric Anholt2011-08-162-1/+22
| | | | Fixes vs-op-mult-int-int and friends.
* i965/vs: Add support for conversion of FIXED_HW_REG src_reg to/from dst_reg.Eric Anholt2011-08-161-0/+2
| | | | This was quietly occurring in some emit code I produced, and failed.
* i965/vs: Fix memory leak of ralloc context for the visitor.Eric Anholt2011-08-161-0/+1
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* i965/vs: Fix condition code for scalar expression all_equals.Eric Anholt2011-08-161-1/+1
| | | | Fixes vs-op-eq-bool-bool.
* i965/vs: Don't assertion fail on vertex texturing.Eric Anholt2011-08-161-1/+6
| | | | | | The linker will reject the program, but we need to survive until then. Fixes abort in glsl1-2D Texture lookup with explicit lod (Vertex shader)
* i965/gen6: Force WHILE exec size to 8.Eric Anholt2011-08-161-4/+2
| | | | | | | | | | We can't just look at the instruction that happens to appear at the start of the loop, because it might be some other exec size and cause us to only loop on the first N channels. We always want 8 in our current code (since 16 doesn't work so we don't do 16-wide fragment in that case). Fixes loop-03.vert, which was triggering the assertions.
* i965/vs: Remove remaining use of foreach_iter.Eric Anholt2011-08-162-9/+5
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* i965/vs: Fix abs/negate handling on attributes.Eric Anholt2011-08-161-2/+9
| | | | Fixes glsl-vs-neg-attribute and glsl-vs-abs-attribute.
* i965/vs: Avoid generating a MOV for most ir_assignment handling.Eric Anholt2011-08-162-0/+73
| | | | | Removes an average of 11.5% of instructions in 54% of vertex shaders in shader-db.
* i965/vs: Run the shader backend at link time and return compile failures.Eric Anholt2011-08-166-20/+54
| | | | | | Link failure is something that shouldn't happen, but we sometimes want it during development. The precompile also allows analysis of shader codegen with shader-db.
* i965: Fix assertion failure on a loop consisting of while (true) { break }.Eric Anholt2011-08-161-1/+1
| | | | | On enabling the precompile step in the VS, we tripped over this assertion failure in glsl-link-bug-30552.
* i965/vs: Fix the trivial register allocator's failure path.Eric Anholt2011-08-162-3/+5
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* i965/vs: Add support for if(any(bvec)) on gen6.Eric Anholt2011-08-161-4/+8
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* i965/vs: Add support for GL_FIXED attributes.Eric Anholt2011-08-161-0/+12
| | | | Fixes arb_es2_compatibility-fixed-type
* i965/vs: Clamp vertex color outputs when required by ARB_color_buffer_float.Eric Anholt2011-08-161-1/+10
| | | | Fixes glsl-vs-vertex-color.
* i965/vs: Fix access of attribute arrays.Eric Anholt2011-08-161-1/+2
| | | | | By leaving out the column index, we were reading an unallocated attribute on glsl-mat-attribute.
* i965/vs: Fix builtin uniform setup.Eric Anholt2011-08-161-3/+2
| | | | | I want to intelligently pack them at some point, but for now we have the params set up in groups of 4. Fixes glsl-vs-normalscale.
* i965/vs: Add support for loops.Eric Anholt2011-08-161-32/+21
| | | | | This is copied from brw_fs.cpp, instead of doing the temporary IR generation that ir_to_mesa does. Fixes glsl-vs-loop and friends.
* i965/vs: Add support for ir_binop_pow.Eric Anholt2011-08-163-7/+70
| | | | Fixes vs-pow-float-float.
* i965/vs: Respect the gen6 limitation that math opcodes can't be align16.Eric Anholt2011-08-162-2/+33
| | | | Fixes vs-acos-vec3 and friends.
* i965/vs: Fix implementation of ir_unop_any.Eric Anholt2011-08-161-1/+3
| | | | We were inheriting whatever previous predicate existed.
* i965/vs: Slightly improve the trivial reg allocator to skip unused regs.Eric Anholt2011-08-161-2/+24
| | | | | | | This fixes most of the regressions in the vs array test set from the varying array indexing work, since the giant array that was originally allocated in virtual GRF space never gets used and is only ever read/stored from scratch space.
* i965: Add gen6 disassembly for DP render cache messages.Eric Anholt2011-08-161-3/+46
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* i965/vs: Enable variable array indexing in the VS.Eric Anholt2011-08-161-5/+7
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* i965/vs: Add support for scratch read/write codegen.Eric Anholt2011-08-162-2/+151
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* i965: Make some EU emit code for DP read/write messages non-static.Eric Anholt2011-08-162-22/+49
| | | | | | | | We keep building these strange interfaces for DP read/write where there's a helper function with some partially-specific, partially-general controls, which is used in exactly one place in code generation. Making these public will let us set up those instructions in the one place they're to be generated.
* i965/vs: Move virtual GRFs with array accesses to them to scratch space.Eric Anholt2011-08-164-1/+186
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* i965/vs: Reserve MRF 14/15 for array loads/register unspilling.Eric Anholt2011-08-161-6/+14
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* i965/vs: Track the variable index of array accesses.Eric Anholt2011-08-162-4/+16
| | | | This isn't used currently, as we lower all array accesses.
* i965: Add remaining scratch space setup emit to unit states.Eric Anholt2011-08-164-3/+35
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* i965: Set up allocation of a VS scratch space if required.Eric Anholt2011-08-165-22/+47
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* i965: Remove dead brw->wm.max_threads field.Eric Anholt2011-08-161-1/+0
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* i965/vs: Add support for VUEs larger than a single URB write.Eric Anholt2011-08-161-8/+34
| | | | Fixes glsl-max-varyings.
* i965/vs: Avoid generating extra moves when setting up large ir_constants.Eric Anholt2011-08-162-51/+28
| | | | | We were also screwing up the types in the process, and just not emitting moves was easier.
* i965/vs: Fix types of varying outputs.Eric Anholt2011-08-161-0/+1
| | | | | | | | | For structs/arrays/matrices, they were ending up as uint because we forgot to set them. All varyings in GLSL 1.20 are of base type float, so just force the matter here (which gets inherited at emit_urb_writes() time). Fixes vs-varying-array-mat2-col-rd.
* i965/vs: Handle assignment of structures/arrays/matrices better.Eric Anholt2011-08-162-21/+51
| | | | | This gets the right types on the instructions, as well as emitting minimal swizzles/writemasks.
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