aboutsummaryrefslogtreecommitdiffstats
path: root/src/mesa/drivers
Commit message (Collapse)AuthorAgeFilesLines
* intel: Add missing header to intel_context.c.Vinson Lee2010-07-301-0/+1
| | | | | Fixes "implicit declaration of function _mesa_get_incomplete_framebuffer" warning.
* intel: Add missing header.Vinson Lee2010-07-291-0/+1
| | | | Add context.h for NEED_SECONDARY_COLOR symbol.
* dri: Add missing header to dri_metaops.c.Vinson Lee2010-07-291-0/+1
| | | | Add context.h for FLUSH_VERTICES symbol.
* intel: Declare the various tracked state variables using "extern"Kristian Høgsberg2010-07-291-62/+62
|
* intel: Don't depend on context config values when picking texture formatsKristian Høgsberg2010-07-291-24/+12
|
* r600: since 8744c36e added asserts - use another random register for shader ↵Andre Maasikas2010-07-291-1/+1
| | | | with no output
* intel: Implement EGL_KHR_surfaceless extensionKristian Høgsberg2010-07-281-7/+20
|
* intel: Remove unused intel/server filesKristian Høgsberg2010-07-275-397/+2
|
* i965: Fix reversed naming of the operations in compute-to-mrf optimization.Eric Anholt2010-07-263-6/+11
| | | | | Also fix up comments, so that the difference between the two passes is clarified.
* i965: Clean up a few magic numbers to use brw_defines.h defs.Eric Anholt2010-07-263-18/+20
|
* i965: Use MIN2, MAX2 instead of rolling our own.Eric Anholt2010-07-261-15/+12
|
* i965: Fold the "is arithmetic" bit of 965 opcodes into the opcode list.Eric Anholt2010-07-261-50/+26
|
* i965: Remove some duped register size/count definitionsEric Anholt2010-07-262-34/+26
|
* i965: Move the GRF-to-MRF optimizations to brw_optimize.c.Eric Anholt2010-07-263-619/+618
|
* i965: Improve (i.e. remove) some grf-to-mrf unnecessary movesBenjamin Segovia2010-07-261-2/+626
| | | | | | | | | | | | | | | | | | | | | | | | | Several routines directly analyze the grf-to-mrf moves from the Gen binary code. When it is possible, the mov is removed and the message register is directly written in the arithmetic instruction Also redundant mrf-to-grf moves are removed (frequently for example, when sampling many textures with the same uv) Code was tested with piglit, warsow and nexuiz on an Ironlake machine. No regression was found there Note that the optimizations are *deactivated* on Gen4 and Gen6 since I did test them properly yet. No reason there are bugs but who knows The optimizations are currently done in branch free programs *only*. Considering branches is more complicated and there are actually two paths: one for branch free programs and one for programs with branches Also some other optimizations should be done during the emission itself but considering that some code is shader between vertex shaders (AOS) and pixel shaders (SOA) and that we may have branches or not, it is pretty hard to both factorize the code and have one good set of strategies
* i965: Allow VS MOVs to use immediate constants.Eric Anholt2010-07-261-0/+1
| | | | | Clarifies program assembly, and with a little tweak to always use constant_map, we could cut down on constant buffer payload.
* i965: Cleanly fail programs with unsupported array access.Eric Anholt2010-07-231-1/+28
| | | | | This should be more useful for developers and for bug triaging than just generating wrong code.
* i965: Add support for VS relative addressing of temporary arrays.Eric Anholt2010-07-231-2/+49
| | | | Fixes glsl-vs-arrays. Bug #27388.
* i965: Respect VS/VP point size result when enabled.Eric Anholt2010-07-221-3/+4
| | | | Fixes glsl-vs-point-size.
* i965: Fix the disasm output for da16 src widths.Eric Anholt2010-07-221-1/+1
| | | | | | This has confused me twice now. It's a fixed width of 4 (usually a region description of <4,4,1>), not 1. If it was 1, we'd have been skipping all over register space.
* i965: Avoid extra MOV in VS indirect register reads.Eric Anholt2010-07-221-15/+16
|
* i965: Fix up VS temporary array access for fixed index offset != 0.Eric Anholt2010-07-221-1/+1
|
* r600: Flip point sprite coordinates when rendering to an FBO.Henri Verbeet2010-07-221-1/+3
| | | | This supersedes http://lists.freedesktop.org/archives/mesa-dev/2010-July/001442.html.
* i965: In the VS, multiply the address reg by the appropriate register size.Eric Anholt2010-07-211-27/+14
| | | | | | | | | | | | The ARL value is increments of vec4 in the register file. But PROGRAM_TEMPORARY or PROGRAM_INPUT are stored as vec4s interleaved between the two verts being executed (thus a vec8 each), compared to PROGRAM_STATE_VAR being packed vec4s. Fixes: glsl-vs-arrays-2 glsl-vs-mov-after-deref (without regressing glsl-vs-arrays-3)
* i965: Clean up brw_dp_READ_4_vs() now that it has fewer options to support.Eric Anholt2010-07-213-52/+31
|
* i965: Support relative addressed VS constant reads using the appropriate msg.Eric Anholt2010-07-213-31/+66
| | | | | The previous support was overly complicated by trying to use the same 1-OWORD message for both offsets.
* i965: Fix the DP read msg_control definitions other than plain OWORD.Eric Anholt2010-07-211-6/+16
|
* i965: Clean up dead code from the VS get_constant/get_reladdr_constant split.Eric Anholt2010-07-211-3/+1
|
* i956: Set the execution size correctly for scratch space writes.Eric Anholt2010-07-211-2/+2
| | | | | | | | Otherwise, the second half isn't written, and we end up reading back black. Fixes the remaining junk drawn in glsl-max-varyings, and will likely help with a number of large real-world shaders.
* i965: Set the GEM domain flags for the scratch space.Eric Anholt2010-07-211-1/+1
| | | | | | They go into the render cache, so while we don't care about their contents after execution, failing to note them could cause the writes to be flushed over important buffer contents later.
* i965: Use the pretty define for 4-oword DP reads.Eric Anholt2010-07-211-1/+1
|
* i965: Set the send commit bit on register spills as required pre-gen6.Eric Anholt2010-07-211-9/+32
| | | | Otherwise, the subsequent read may not get the written value.
* i965: Add disasm for dataport reads (register unspilling).Eric Anholt2010-07-211-1/+22
|
* i965: Remove an unused variable.Carl Worth2010-07-211-1/+0
| | | | To quiet a compiler warning.
* radeon: Remove unnecessary header.Vinson Lee2010-07-201-1/+0
|
* mesa: call ctx->Driver.ChooseTextureFormat() only when necessary.Brian Paul2010-07-201-6/+3
| | | | | | | | | | | | | | | | | | | When defining mipmap level 'L' and level L-1 exists and the new level's internalFormat matches level L-1's internalFormat, then use the same hw format. Otherwise, do the regular ctx->Driver.ChooseTextureFormat() call. This avoids a problem where we end up choosing different hw formats for different mipmap levels depending on how the levels are defined (glTexImage vs. glCopyTexImage vs. glGenerateMipmap, etc). The root problem is the ChooseTextureFormat() implementation in some drivers uses the user's glTexImage format/type parameters in the choosing heuristic. Later mipmap levels might be generated with different calls (ex: glCopyTexImage()) so we don't always have format/type info and the driver may choose a different format. For more background info see the July 2010 mesa-dev thread "Bug in _mesa_meta_GenerateMipmap"
* glx: Remove support for MESA_swap_frame_usageKristian Høgsberg2010-07-197-42/+0
| | | | | The extension never worked, the implementation returns GLX_BAD_CONTEXT when enabling the frame tracking.
* glx: Drop support for GLX_MESA_allocate_memoryKristian Høgsberg2010-07-194-154/+0
| | | | Only r200 implemented it.
* i965: Mostly fix glsl-max-varyings.Eric Anholt2010-07-191-10/+20
| | | | | | | | There was confusion on both the size of message we can send, and on what the URB destination offset means. The remaining problems appear to be due to spilling of regs in the fragment shader being broken.
* i965: Clean up message register setup in emit_vertex_write().Eric Anholt2010-07-191-7/+7
|
* i965: Reduce repeated calculation of the attribute-offset-in-VUE.Eric Anholt2010-07-194-24/+19
| | | | | | This cleans up some chipset dependency sprinkled around, and fixes a potential overflow of the attribute offset array for many vertex results.
* i965: Clarify the nr_regs calculation in brw_clip.cEric Anholt2010-07-191-3/+8
|
* i965: Don't set up VUE space for the disabled user clip distances on gen6.Eric Anholt2010-07-192-8/+14
|
* r600: fix typo in r700 assemblerAlex Deucher2010-07-151-1/+1
| | | | | | Noticed by Henri Verbeet on IRC. NOTE: This is a candidate for the 7.8 branch.
* radeon: Also flush if it's not the current context that's being destroyed.Henri Verbeet2010-07-151-1/+1
| | | | | | | This avoids calling radeonFlush() during context destruction, when ctx->DrawBuffer would be NULL. NOTE: This is a candidate for the 7.8 branch.
* radeon: allow driconf vblank settings with dri2Alex Deucher2010-07-151-0/+1
| | | | | | | fixes: https://bugs.freedesktop.org/show_bug.cgi?id=28771 NOTE: This is a candidate for the 7.8 branch.
* r300/compiler: fix swizzling in the transformation of Abs modifiersMarek Olšák2010-07-141-2/+2
|
* r300/compiler: implement the Abs source operand modifier for vertex shadersMarek Olšák2010-07-131-4/+55
|
* r300/compiler: emulate SIN/COS/SCS in r3xx-r4xx vertex shadersMarek Olšák2010-07-131-1/+7
| | | | Despite the docs, the corresponding hardware instructions are r5xx-only.
* Merge branch 'master' of git://anongit.freedesktop.org/mesa/mesaMaciej Cencora2010-07-121-1/+1
|\
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-02 17:35:40 +0000