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* i965: Delete a batch size assertion that isn't very useful.Kenneth Graunke2017-09-141-3/+0
| | | | | | | | | | | This assertion prevents you from doing intel_batchbuffer_require_space with a size so huge it won't fit in the batchbuffer. This doesn't seem like a common mistake, and I've never seen the assert to be useful. Soon, I hope to have batches grow, at which point this won't make sense. Reviewed-by: Matt Turner <[email protected]> Reviewed-by: Chris Wilson <[email protected]>
* i965/screen: Implement queryDmaBufFormatModifierAttirbsJason Ekstrand2017-09-141-1/+23
| | | | | Reviewed-by: Emil Velikov <[email protected]> Reviewed-by: Daniel Stone <[email protected]>
* i965/screen: Report the correct number of image planesJason Ekstrand2017-09-141-1/+8
| | | | | | | | | For non-CCS images, we were reporting just one plane even though they may have multiple in the case of YUV. Reviewed-by: Ben Widawsky <[email protected]> Reviewed-by: Emil Velikov <[email protected]> Reviewed-by: Daniel Stone <[email protected]>
* dri/radeon: use ARRAY_SIZE macroEric Engestrom2017-09-141-1/+3
| | | | | Signed-off-by: Eric Engestrom <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* i965: Add an INTEL_DEBUG=submit option for printing batch statistics.Kenneth Graunke2017-09-131-1/+1
| | | | | | | | | | | | | | | | | | | When a batch is submitted, INTEL_DEBUG=bat prints a message indicating which part of the code triggered the flush, and some statistics about the batch/state buffer utilization. It also decodes the batchbuffer in debug builds...which is so much output that it drowns out the utilization messages, if that's all you care about. INTEL_DEBUG=submit now just does the utilization messages. INTEL_DEBUG=bat continues to do both (as the message is a good indicator that we're starting decode of a new batch). v2: Rename from "flush" to "submit" (suggested by Chris) because we might want "flush" for PIPE_CONTROL debugging someday. Reviewed-by: Chris Wilson <[email protected]>
* i965: do not fallback to linear tiling for stencil surfacesIago Toral Quiroga2017-09-121-4/+7
| | | | | | | | | | | | | | | | | | | | | | | | We were skipping this fallback for depth, but not for stencil which the hardware always requires to be W-tiled. Also, make the checks for whether we need to apply retiling strategies based on usage instead of tiling flags, which is safer and more explicit. This fixes a regression in a CTS test introduced with commit 4ea63fab77f0 that started applying re-tiling stencil surfaces in certain scenarios. v2: discard retiling based on usage fields instead of tiling flags. This is safer and more explicit. v3: Add a comment indicating that texturing of stencil in gen7 requires an Y-tiled copy (Topi). Fixes: KHR-GL45.direct_state_access.renderbuffers_storage Reviewed-by: Topi Pohjolainen <[email protected]>
* i965/tex: add missing includeEric Engestrom2017-09-101-0/+1
| | | | | | | | | | | src/mesa/drivers/dri/i965/intel_tex.h:52:40: warning: ‘enum intel_miptree_create_flags’ declared inside parameter list will not be visible outside of this definition or declaration enum intel_miptree_create_flags flags); ^~~~~~~~~~~~~~~~~~~~~~~~~~ Fixes: cadcd89278edcda8aba2 "i965/tex: Change the flags type on create_for_teximage" Signed-off-by: Eric Engestrom <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* i965: Don't special case the batchbuffer when reference counting.Kenneth Graunke2017-09-081-11/+4
| | | | | | | | | | | | We don't need to special case the batch - when we add the batch to the validation list, we can simply increase the refcount to 2, and when we make a new batch, we'll drop it back down to 1 (when unreferencing all buffers in the validation list). The final reference is still held by brw->batch.bo, as it was before. This removes the special case from a bunch of loops. Reviewed-by: Chris Wilson <[email protected]>
* i965: expose RGBA visuals only on AndroidEmil Velikov2017-09-061-1/+22
| | | | | | | | | | | | | | | | | | | | | As Marek pointed out in earlier commit - exposing RGBA on other platforms introduces ~500 Visuals, which are not tested. Note that this does not quite happen, yet. Reason being that the GLX code does not check the masks - see scaralEqual(). Thus as we fix that, we'll run into the issue described. v2: Rebase, while keeping loaderPrivate v3: Beef-up commit message, getCapability() returns unsigned (Tapani) Fixes: 1bf703e4ea5 ("dri_interface,egl,gallium: only expose RGBA visuals on Android") Cc: Tomasz Figa <[email protected]> Cc: Chad Versace <[email protected]> Cc: Marek Olšák <[email protected]> Signed-off-by: Emil Velikov <[email protected]> Reviewed-by: Tapani Pälli <[email protected]>
* genxml: Make Border Color Pointer an address on Gen4-5, not an offset.Kenneth Graunke2017-09-021-6/+4
| | | | Reviewed-by: Jason Ekstrand <[email protected]>
* i965: Inline emit_reloc in __genx_combine_addressKenneth Graunke2017-09-021-12/+5
| | | | | | One less layer of baklava. Reviewed-by: Jason Ekstrand <[email protected]>
* i965: Fix crash in fallback GTT mapping.Kenneth Graunke2017-09-021-2/+4
| | | | | | | We can't perf_debug without a context. Cc: [email protected] Reviewed-by: Anuj Phogat <[email protected]>
* i965: Fix state flagging of Gen6 SOL programs.Kenneth Graunke2017-09-022-19/+6
| | | | | | | | | | | | | | | | | | | It doesn't seem like the old code could possibly work. 1. brw_gs_state_dirty made us bail unless one of these flags were set: _NEW_TEXTURE, BRW_NEW_GEOMETRY_PROGRAM, BRW_NEW_TRANSFORM_FEEDBACK 2. If there was no geometry program, we called brw_upload_ff_gs_prog()3 3. That checked brw_ff_gs_state_dirty and bailed unless these were set: _NEW_LIGHT, BRW_NEW_PRIMITIVE, BRW_NEW_TRANSFORM_FEEDBACK, BRW_NEW_VS_PROG_DATA. 4. brw_ff_gs_prog_key pv_first and attr fields were set based on data depending on _NEW_LIGHT and BRW_NEW_VS_PROG_DATA. This means that if we needed a FF GS program, and changed the VS outputs or provoking vertex mode, we'd fail to notice that we needed to emit a new program. Reviewed-by: Jordan Justen <[email protected]>
* i965: Drop useless gen6_brw_upload_ff_gs_prog() wrapper.Kenneth Graunke2017-09-023-7/+1
| | | | | | gen6...brw? Drop some baklava layers. Reviewed-by: Jordan Justen <[email protected]>
* i965: Move BATCH_SZ define into intel_batchbuffer.c.Kenneth Graunke2017-09-012-1/+2
| | | | | | It's only used in one file. Reviewed-by: Chris Wilson <[email protected]>
* i965: Drop batch_size argument from brw_bufmgr_init().Kenneth Graunke2017-09-013-4/+3
| | | | | | This is dead code and hasn't been used in a long time. Reviewed-by: Chris Wilson <[email protected]>
* i965: Rename brw_bo::offset64 to gtt_offset.Chris Wilson2017-09-013-12/+35
| | | | | | | | | | | | | | | | | We can drop the meaningless "64" suffix - libdrm_intel originally had an "offset" field that was an "unsigned long" which was the wrong size, and we couldn't remove/alter that field without breaking ABI, so we had to add a uint64_t "offset64" field. "gtt_offset" is also more descriptive than "offset". (Patch originally written by Ken, but Chris suggested a better name and supplied the giant comment making up the bulk of the patch, so I changed the authorship to him.) Acked-by: Kenneth Graunke <[email protected]> Reviewed-by: Chris Wilson <[email protected]>
* i965: Drop the BRW_BATCH_STRUCT macro.Kenneth Graunke2017-09-012-4/+1
| | | | | | | It's used in exactly one place these days, and not much simpler than just calling intel_batchbuffer_data directly. Reviewed-by: Chris Wilson <[email protected]>
* i965: Don't double count the batch in aperture_space.Kenneth Graunke2017-09-011-1/+1
| | | | | | | | | intel_batchbuffer_reset calls add_exec_bo on the batch right away, which adds in the batch BO size. Fixes: 29ba502a4e28 ("i965: Use I915_EXEC_BATCH_FIRST when available.") Reviewed-by: Chris Wilson <[email protected]>
* i965: Use BLORP for buffer object stall avoidance blits instead of BLT.Kenneth Graunke2017-08-301-11/+11
| | | | | | | | Improves performance of GFXBench4 tests at 1024x768 on a Kabylake GT2: - Manhattan 3.1 by 1.32134% +/- 0.322734% (n=8). - Car Chase by 1.25607% +/- 0.291262% (n=5). Reviewed-by: Jason Ekstrand <[email protected]>
* i965: Always flush caches after blitting to a GL buffer object.Kenneth Graunke2017-08-301-1/+3
| | | | | | | | | | | | | | | | | When we blit data into a buffer object, we may need to invalidate any caches that might contain stale data, so the new data becomes visible. For example, if the buffer object is bound as a vertex buffer, we need to invalidate the vertex fetch cache. While this flushing was missing, it usually happened implicitly for non-obvious reasons: we're usually on the render ring, and calling intel_emit_linear_blit() would require switching to the BLT ring, causing an implicit flush. This likely provoked the kernel to do PIPE_CONTROLs on our behalf. Although, Gen4-5 wouldn't have this behavior. At any rate, we should do it ourselves. Reviewed-by: Jason Ekstrand <[email protected]>
* i965: Add PIPE_CONTRTOL_DATA_CACHE flush to brw_emit_mi_flush().Kenneth Graunke2017-08-301-0/+1
| | | | | | | | | Although we're phasing out brw_emit_mi_flush(), we still use it in some places in order to "flush everything". In a number of those places, we write data to a buffer that we may then bind as an image surface, SSBO, or atomic buffer. Those usages require us to flush the data cache. Reviewed-by: Jason Ekstrand <[email protected]>
* i965: Add a brw_blorp_copy_buffers() command.Kenneth Graunke2017-08-302-0/+29
| | | | | | | | This exposes the new blorp_copy_buffer() functionality to i965. It should be a drop-in replacement for intel_emit_linear_blit() (other than the arguments being backwards, for consistency with BLORP). Reviewed-by: Jason Ekstrand <[email protected]>
* i965: drop unused brw->needs_unlit_centroid_workaroundLionel Landwerlin2017-08-302-11/+0
| | | | | | Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Samuel Iglesias Gonsálvez <[email protected]> Reviewed-by: Emil Velikov <[email protected]>
* i965: drop brw->has_surface_tile_offset in favor of devinfo'sLionel Landwerlin2017-08-305-8/+9
| | | | | | Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Samuel Iglesias Gonsálvez <[email protected]> Reviewed-by: Emil Velikov <[email protected]>
* i965: drop unused brw->no_simd8Lionel Landwerlin2017-08-301-1/+0
| | | | | | Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Samuel Iglesias Gonsálvez <[email protected]> Reviewed-by: Emil Velikov <[email protected]>
* i965: drop unused brw->has_plnLionel Landwerlin2017-08-302-2/+0
| | | | | | Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Samuel Iglesias Gonsálvez <[email protected]> Reviewed-by: Emil Velikov <[email protected]>
* i965: drop brw->must_use_separate_stencil in favor of devinfo'sLionel Landwerlin2017-08-304-4/+5
| | | | | | Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Samuel Iglesias Gonsálvez <[email protected]> Reviewed-by: Emil Velikov <[email protected]>
* i965: drop unused brw->has_negative_rhw_bugLionel Landwerlin2017-08-302-2/+0
| | | | | | Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Samuel Iglesias Gonsálvez <[email protected]> Reviewed-by: Emil Velikov <[email protected]>
* i965: drop unused brw->has_compr4Lionel Landwerlin2017-08-302-2/+0
| | | | | | Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Samuel Iglesias Gonsálvez <[email protected]> Reviewed-by: Emil Velikov <[email protected]>
* i965: drop brw->has_llc in favor of devinfo->has_llcLionel Landwerlin2017-08-307-8/+8
| | | | | | Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Samuel Iglesias Gonsálvez <[email protected]> Reviewed-by: Emil Velikov <[email protected]>
* i965: drop brw->is_broxtonLionel Landwerlin2017-08-304-5/+2
| | | | | | | | | We need to take some take here as brw->is_broxton has been used to check whether the device is a low power gen9 (aka Atom gen9 platform). Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Samuel Iglesias Gonsálvez <[email protected]> Reviewed-by: Emil Velikov <[email protected]>
* i965: drop brw->is_cherryview in favor of devinfo->is_cherryviewLionel Landwerlin2017-08-303-4/+4
| | | | | | Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Samuel Iglesias Gonsálvez <[email protected]> Reviewed-by: Emil Velikov <[email protected]>
* i965: drop brw->is_haswell in favor of devinfo->is_haswellLionel Landwerlin2017-08-3023-44/+45
| | | | | | Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Samuel Iglesias Gonsálvez <[email protected]> Reviewed-by: Emil Velikov <[email protected]>
* i965: drop brw->is_baytrail in favor of devinfo->is_baytrailLionel Landwerlin2017-08-308-13/+13
| | | | | | Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Samuel Iglesias Gonsálvez <[email protected]> Reviewed-by: Emil Velikov <[email protected]>
* i965: drop brw->is_g4x in favor of devinfo->is_g4xLionel Landwerlin2017-08-308-12/+10
| | | | | | Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Samuel Iglesias Gonsálvez <[email protected]> Reviewed-by: Emil Velikov <[email protected]>
* i965: drop brw->gt in favor of devinfo->gtLionel Landwerlin2017-08-305-8/+5
| | | | | | Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Samuel Iglesias Gonsálvez <[email protected]> Reviewed-by: Emil Velikov <[email protected]>
* i965: drop brw->gen in favor of devinfo->genLionel Landwerlin2017-08-3047-311/+506
| | | | | | Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Samuel Iglesias Gonsálvez <[email protected]> Reviewed-by: Emil Velikov <[email protected]>
* i965: add 2xMSAA 16xMSAA modes to DRI configs.Kevin Rogovin2017-08-301-5/+18
| | | | | | | | | | | For Gen8, add 2xMSAA. For Gen9, add 2xMSAA and 16xMSAA. Special thanks to Eero Tamminen for reporting rasterizer numbers being twice what it should be for 2xMSAA under a benchmark. V2: Make pointer name less ugly + add 2xMSAA for Gen8 Reviewed-by: Kenneth Graunke <[email protected]>
* Revert "i965: add 2xMSAA and 16xMSAA to DRI configs for Gen9."Kenneth Graunke2017-08-301-10/+3
| | | | | | | | | This reverts commit f6d38785e8b28a6dd303884798b823e289817741. Kevin's original patch accidentally didn't add 2x for Gen8; he sent a v2 with a bunch of style fixes shortly after I pushed the original patch, not knowing it was coming. Let's just revert this one, apply v2, and move on.
* i965: Bump the initial program cache size from 4kB to 16kB.Kenneth Graunke2017-08-291-1/+1
| | | | | | | | | | | | | | | | Our initial size of 4kB is way too small to do anything useful, so we end up growing it at least a few times. We may as well start it larger. Some data points: - Dinoshade (from Mesa Demos): hit 8kB. - Chromium 60: hit 16kB after browsing a few things in Google Docs. - GFXBench4 TRex/Manhattan 3.1: hit 128kB - Unigine Valley 1.0: hit 512kB It might make sense to start it even larger. Acked-by: Matt Turner <[email protected]>
* i965: Issue performance warnings when growing the program cacheKenneth Graunke2017-08-291-0/+3
| | | | | | | This involves a bunch of unnecessary copying, a batch flush, and state re-emission. Reviewed-by: Matt Turner <[email protected]>
* i965: add 2xMSAA and 16xMSAA to DRI configs for Gen9.Kevin Rogovin2017-08-291-3/+10
| | | | | | | | | Special thanks to Eero Tamminen for reporting rasterizer numbers being twice what it should be for 2xMSAA under a benchmark. Signed-off-by: Kevin Rogovin <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Add $(WNO_OVERRIDE_INIT) to AM_CFLAGSMatt Turner2017-08-291-0/+1
| | | | | | | | brw_surface_formats.c and genX_blorp_exec.c do this a lot, causing lots of warnings from clang. Reviewed-by: Emil Velikov <[email protected]> Reviewed-by: Eric Engestrom <[email protected]>
* i965: Mark functions used conditionally as UNUSEDMatt Turner2017-08-292-3/+3
| | | | | | | | The functions we're marking as UNUSED in genX_state_upload.c are used only when compiling for particular generations. Reviewed-by: Emil Velikov <[email protected]> Reviewed-by: Eric Engestrom <[email protected]>
* i965: Explicitly cast between different enumsMatt Turner2017-08-291-4/+4
| | | | | | | | | | | | | Fixes warnings like warning: implicit conversion from enumeration type 'enum isl_format' to different enumeration type 'enum GEN10_SURFACE_FORMAT' [-Wenum-conversion] .SourceElementFormat = ISL_FORMAT_R32_UINT, ^~~~~~~~~~~~~~~~~~~ Reviewed-by: Emil Velikov <[email protected]> Reviewed-by: Eric Engestrom <[email protected]>
* i965: Remove some 'inline' keywordsMatt Turner2017-08-291-7/+7
| | | | | | | | | brw_texture_view_sane() is only used by an assert()... No difference in the resulting binary with gcc-6.3.0 or clang-4.0. Reviewed-by: Emil Velikov <[email protected]> Reviewed-by: Eric Engestrom <[email protected]>
* i965: Fix whitespace issues in intel_buffer_objects.c.Kenneth Graunke2017-08-281-31/+29
| | | | Convert tabs to spaces and rewrap one long line.
* i965: Use GEN_GEN and GEN_IS_HASWELL in genX_state_upload.c code.Kenneth Graunke2017-08-251-4/+4
| | | | | | | | We were using brw->gen, brw->is_haswell, and devinfo->gen in a few places, when we could just use GEN_GEN and GEN_IS_HASWELL, which are evaluated at compile time. Reviewed-by: Eduardo Lima Mitev <[email protected]>
* mesa: Implement GL_ARB_polygon_offset_clampAdam Jackson2017-08-251-1/+1
| | | | | | | | | | | Semantically identical to the EXT version (whose string is still valid for GLES), so rename the bit but expose both extension strings. (Suggested by Ilia Mirkin and Ian Romanick.) v3: Fix the entrypoint alias in GL4x.xml (Ilia) Signed-off-by: Adam Jackson <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
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