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* [intel] Add some doxygen notes on what the bufmgr_fake block members mean.Eric Anholt2007-11-161-2/+11
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* [intel] Add a simple relocation cache to the fake buffer manager.Eric Anholt2007-11-161-35/+91
| | | | | This is required for 965 performance, as it avoids a lot of repeated data uploads of the state caches due to surface offsets in them.
* [intel] Assert against 0-sized buffers in dri_bufmgr_fake.c.Eric Anholt2007-11-161-0/+4
| | | | They shouldn't be created, and this often helps catch stupid issues.
* [intel] Add support for multiple levels of relocation in bufmgr_fake.Eric Anholt2007-11-162-73/+163
| | | | | This is required for 965 support, which has relocations in other places than just the batchbuffer.
* [i915] Push locking in intelClearWithTris down inside meta_draw_poly.Eric Anholt2007-11-162-85/+72
| | | | | | | | | The lock coverage and checks for cliprects were unneeded since the batchbuffer will have INTEL_BATCH_CLIPRECTS anyway. It appeared to be a leftover from intelClearWithBlit. This makes the locking requirements of i915 meta_draw_quad match i965 meta_draw_quad.
* fix bogus assumption if ddx has set up surface reg for z bufferRoland Scheidegger2007-11-151-2/+1
| | | | | | | | this is wrong since even if ddx has not set up a surface reg to cover the z buffer we should pretend it has on those rv100 chips since they presumably do not do z buffer tiling if not using hyperz, so we can use linear addressing just the same. Doesn't seem to fix #13080, but it's wrong anyway and the bug almost certainly broke newer non-tcl chips.
* i965: correct the opcode of XY_SETUP_BLT_CMD. fix bug #12730Xiang, Haihao2007-11-121-1/+1
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* [i915] Remove old frontbuffer rotation hack.Eric Anholt2007-11-0911-564/+8
| | | | | | This was replaced in previous releases of xserver/dri/libGL by reporting the damage to the frontbuffer so that the server and driver could handle it appropriately.
* [intel] By default, output batchbuffer decode to stderr like other debug info.Eric Anholt2007-11-091-1/+1
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* [intel] Initialize a depth buffer if the visual has depth 24 but no stencil.Eric Anholt2007-11-091-15/+28
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* [intel] Move over files that will be shared with 965-fbo work.Eric Anholt2007-11-0945-8055/+8072
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* code clean-ups, reformattingBenno Schulenberg2007-11-091-11/+8
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* recreate from changed gl_API.xmlRoland Scheidegger2007-11-091-36/+12
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* fix Unichrome/Blender crash, bug 13142Benno Schulenberg2007-11-081-2/+4
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* r200: Re-expose SetTexOffset functionality.Michel Dänzer2007-11-061-1/+7
| | | | This seems to have been mismerged with the DRI interface changes.
* r200: Fix SetTexOffset format for 16 bit pixmaps/textures.Michel Dänzer2007-11-061-6/+6
| | | | Use symbolic array indices to clarify.
* Renamed the R300_VAP_UNKNOWN_221C to R300_VAP_CLIP_CNTL.Oliver McFadden2007-11-055-10/+15
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* r300: initial user clipping for TCL pathsDave Airlie2007-11-054-1/+84
| | | | | I've no idea if this code might break something or how it should interact with vertex shaders, it makes the clip demo work for me
* fix typoBrian2007-11-031-1/+1
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* r300: move more vap registers out of non tcl pathsDave Airlie2007-11-033-14/+16
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* r300: fix misnumber registerDave Airlie2007-11-031-1/+1
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* r300: fix texwrap border colorDave Airlie2007-11-031-1/+1
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* nouveau: ppc, swap fragment programs on big endian systems.Dave Airlie2007-11-013-5/+16
| | | | Thanks to the PS3 RSX project for figuring this out.
* i915: make i915 use the cached mappings for batch/buffer objects.Dave Airlie2007-11-013-5/+4
| | | | This should restore gears speed on 9xx hardware
* Alias glStencilOpSeparateATI with glStencilOpSeparate.Brian2007-10-301-9/+3
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* Finish up ATI_separate_stencilBrian2007-10-301-0/+22
| | | | | | Add entrypoints to glapi XML file and regenerate files. Implement glStencilOpSeparateATI(). Consolidate some code in stencil.c
* More vblank cleanups.Michel Dänzer2007-10-3026-129/+147
| | | | | | | | * Fix crash at context creation in most drivers supporting vblank. * Don't pass vblank sequence or flags to functions that get passed the drawable private already. * Attempt to initialize vblank related drawable private fields just once per drawable. May need more work in some drivers.
* [i915] Include header to pick up intel_ttm_bo_create_from_handle() proto.Eric Anholt2007-10-291-0/+1
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* Merge branch 'origin'Eric Anholt2007-10-2976-334/+2302
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| * Refactor and fix core vblank supportJesse Barnes2007-10-2948-147/+293
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Consolidate support for synchronizing to and retrieving vblank counters. Also fix the core vblank code to return monotonic MSC counters, which are required by some GLX extensions. Adding support for multiple pipes to a low level driver is fairly easy, the Intel 965 driver provides simple example code (see intel_buffers.c:intelWindowMoved()). The new code bumps the media stream counter extension version to 2 and adds a new getDrawableMSC callback. This callback takes a drawablePrivate pointer, which is used to calculate the MSC value seen by clients based on the actual vblank counter(s) returned from the kernel. The new drawable private fields are as follows: - vblSeq - used for tracking vblank counts for buffer swapping - vblFlags - flags (e.g. current pipe), updated by low level driver - msc_base - MSC counter from the last time the current pipe changed - vblank_base - kernel DRM vblank counter from the last time the pipe changed Using the above variables, the core vblank code (in vblank.c) can calculate a monotonic MSC value. The low level DRI drivers are responsible for updating the current pipe (by setting VBLANK_FLAG_SECONDARY for example in vblFlags) along with msc_base and vblank_base whenever the pipe associated with a given drawable changes (again, see intelWindowMoved for an example of this). Drivers should fill in the GetDrawableMSC DriverAPIRec field to point to driDrawableGetMSC32 and add code for pipe switching as outlined above to fully support the new scheme.
| * Merge branch '965-glsl'Zou Nan hai2007-10-2620-158/+1851
| |\ | | | | | | | | | | | | | | | | | | Conflicts: src/mesa/drivers/dri/i965/brw_sf.h src/mesa/drivers/dri/i965/intel_context.c
| | * Non Square MatrixZou Nan hai2007-10-091-0/+2
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| | * fix for prev commitZou Nan hai2007-10-091-2/+2
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| | * INT supportZou Nan hai2007-10-091-3/+3
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| | * shadow sampler fix.Zou Nan hai2007-10-092-1/+13
| | | | | | | | | | | | | | | 1. spec requite result (0, 0, 0, 1) instead of (0, 0, 0, 0) 2. support shadow sampler in simd8
| | * Only vertex program fix, bypass tnl vertex programZou Nan hai2007-10-081-1/+1
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| | * fragment shader function call fix, gl_FragCoord fixZou Nan hai2007-09-302-3/+8
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| | * support continue, fix conditionalZou Nan hai2007-09-293-2/+66
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| | * fixZou Nan hai2007-09-281-2/+0
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| | * support nested function call in pixel shaderZou Nan hai2007-09-282-11/+26
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| | * handle INT op, still require high level handle of integer to be correctZou Nan hai2007-09-271-0/+22
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| | * fix issue when only fragment shader or vertex shader is usedZou Nan hai2007-09-271-5/+12
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| | * ARB_shader_object ARB_vertex_shader ARB_fragment_shader in 965-glsl branchZou Nan hai2007-09-181-0/+6
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| | * fix double free in 965-glsl branchZou Nan hai2007-09-183-0/+6
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| | * DDX DDY support, not very accurateZou Nan hai2007-07-243-1/+103
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| | * Fix SOP in fragment shader, brick is ok now.Zou Nan hai2007-07-171-2/+4
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| | * Merge branch 'master' of git+ssh://[email protected]/git/mesa/mesa ↵Zou Nan hai2007-07-1733-911/+1211
| | |\ | | | | | | | | | | | | into 965-glsl
| | * | Use ProgramStringNotifyZou Nan hai2007-07-171-27/+0
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| | * | support "discard";Zou Nan hai2007-07-052-0/+16
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| | * | Merge branch 'master' of git+ssh://[email protected]/git/mesa/mesa ↵Zou Nan hai2007-07-04167-8355/+8203
| | |\ \ | | | | | | | | | | | | | | | into 965-glsl
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